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[uboot] porting cvitek asic chips:

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1. add cvitek folders to u-boot-2021.10
	2. add cv183x/cv182x part
	3. add cv181x/cv180x part

Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
This commit is contained in:
sam.xiang
2023-02-22 13:43:23 +08:00
parent f8fc109960
commit 3a4bcfca2f
244 changed files with 41355 additions and 1273 deletions
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171
u-boot-2021.10/include/dt-bindings/clock/cv180x-clock.h Normal file
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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: cv181x-clock.h
* Description:
*/
#ifndef __DT_BINDINGS_CLK_CV180X_H__
#define __DT_BINDINGS_CLK_CV180X_H__
#define CV180X_CLK_MPLL 0
#define CV180X_CLK_TPLL 1
#define CV180X_CLK_FPLL 2
#define CV180X_CLK_MIPIMPLL 3
#define CV180X_CLK_A0PLL 4
#define CV180X_CLK_DISPPLL 5
#define CV180X_CLK_CAM0PLL 6
#define CV180X_CLK_CAM1PLL 7
#define CV180X_CLK_A53 8
#define CV180X_CLK_CPU_AXI0 9
#define CV180X_CLK_CPU_GIC 10
#define CV180X_CLK_XTAL_A53 11
#define CV180X_CLK_TPU 12
#define CV180X_CLK_TPU_FAB 13
#define CV180X_CLK_AHB_ROM 14
#define CV180X_CLK_DDR_AXI_REG 15
#define CV180X_CLK_RTC_25M 16
#define CV180X_CLK_TEMPSEN 17
#define CV180X_CLK_SARADC 18
#define CV180X_CLK_EFUSE 19
#define CV180X_CLK_APB_EFUSE 20
#define CV180X_CLK_DEBUG 21
#define CV180X_CLK_XTAL_MISC 22
#define CV180X_CLK_AXI4_EMMC 23
#define CV180X_CLK_EMMC 24
#define CV180X_CLK_100K_EMMC 25
#define CV180X_CLK_AXI4_SD0 26
#define CV180X_CLK_SD0 27
#define CV180X_CLK_100K_SD0 28
#define CV180X_CLK_AXI4_SD1 29
#define CV180X_CLK_SD1 30
#define CV180X_CLK_100K_SD1 31
#define CV180X_CLK_SPI_NAND 32
#define CV180X_CLK_500M_ETH0 33
#define CV180X_CLK_AXI4_ETH0 34
#define CV180X_CLK_500M_ETH1 35
#define CV180X_CLK_AXI4_ETH1 36
#define CV180X_CLK_APB_GPIO 37
#define CV180X_CLK_APB_GPIO_INTR 38
#define CV180X_CLK_GPIO_DB 39
#define CV180X_CLK_AHB_SF 40
#define CV180X_CLK_SDMA_AXI 41
#define CV180X_CLK_SDMA_AUD0 42
#define CV180X_CLK_SDMA_AUD1 43
#define CV180X_CLK_SDMA_AUD2 44
#define CV180X_CLK_SDMA_AUD3 45
#define CV180X_CLK_APB_I2C 46
#define CV180X_CLK_APB_WDT 47
#define CV180X_CLK_PWM 48
#define CV180X_CLK_APB_SPI0 49
#define CV180X_CLK_APB_SPI1 50
#define CV180X_CLK_APB_SPI2 51
#define CV180X_CLK_APB_SPI3 52
#define CV180X_CLK_CAM0_200 53
#define CV180X_CLK_UART0 54
#define CV180X_CLK_APB_UART0 55
#define CV180X_CLK_UART1 56
#define CV180X_CLK_APB_UART1 57
#define CV180X_CLK_UART2 58
#define CV180X_CLK_APB_UART2 59
#define CV180X_CLK_UART3 60
#define CV180X_CLK_APB_UART3 61
#define CV180X_CLK_UART4 62
#define CV180X_CLK_APB_UART4 63
#define CV180X_CLK_APB_I2S0 64
#define CV180X_CLK_APB_I2S1 65
#define CV180X_CLK_APB_I2S2 66
#define CV180X_CLK_APB_I2S3 67
#define CV180X_CLK_AXI4_USB 68
#define CV180X_CLK_APB_USB 69
#define CV180X_CLK_125M_USB 70
#define CV180X_CLK_33K_USB 71
#define CV180X_CLK_12M_USB 72
#define CV180X_CLK_AXI4 73
#define CV180X_CLK_AXI6 74
#define CV180X_CLK_DSI_ESC 75
#define CV180X_CLK_AXI_VIP 76
#define CV180X_CLK_SRC_VIP_SYS_0 77
#define CV180X_CLK_SRC_VIP_SYS_1 78
#define CV180X_CLK_DISP_SRC_VIP 79
#define CV180X_CLK_AXI_VIDEO_CODEC 80
#define CV180X_CLK_VC_SRC0 81
#define CV180X_CLK_H264C 82
#define CV180X_CLK_H265C 83
#define CV180X_CLK_JPEG 84
#define CV180X_CLK_APB_JPEG 85
#define CV180X_CLK_APB_H264C 86
#define CV180X_CLK_APB_H265C 87
#define CV180X_CLK_CAM0 88
#define CV180X_CLK_CAM1 89
#define CV180X_CLK_CSI_MAC0_VIP 90
#define CV180X_CLK_CSI_MAC1_VIP 91
#define CV180X_CLK_ISP_TOP_VIP 92
#define CV180X_CLK_IMG_D_VIP 93
#define CV180X_CLK_IMG_V_VIP 94
#define CV180X_CLK_SC_TOP_VIP 95
#define CV180X_CLK_SC_D_VIP 96
#define CV180X_CLK_SC_V1_VIP 97
#define CV180X_CLK_SC_V2_VIP 98
#define CV180X_CLK_SC_V3_VIP 99
#define CV180X_CLK_DWA_VIP 100
#define CV180X_CLK_BT_VIP 101
#define CV180X_CLK_DISP_VIP 102
#define CV180X_CLK_DSI_MAC_VIP 103
#define CV180X_CLK_LVDS0_VIP 104
#define CV180X_CLK_LVDS1_VIP 105
#define CV180X_CLK_CSI0_RX_VIP 106
#define CV180X_CLK_CSI1_RX_VIP 107
#define CV180X_CLK_PAD_VI_VIP 108
#define CV180X_CLK_1M 109
#define CV180X_CLK_SPI 110
#define CV180X_CLK_I2C 111
#define CV180X_CLK_PM 112
#define CV180X_CLK_TIMER0 113
#define CV180X_CLK_TIMER1 114
#define CV180X_CLK_TIMER2 115
#define CV180X_CLK_TIMER3 116
#define CV180X_CLK_TIMER4 117
#define CV180X_CLK_TIMER5 118
#define CV180X_CLK_TIMER6 119
#define CV180X_CLK_TIMER7 120
#define CV180X_CLK_APB_I2C0 121
#define CV180X_CLK_APB_I2C1 122
#define CV180X_CLK_APB_I2C2 123
#define CV180X_CLK_APB_I2C3 124
#define CV180X_CLK_APB_I2C4 125
#define CV180X_CLK_WGN 126
#define CV180X_CLK_WGN0 127
#define CV180X_CLK_WGN1 128
#define CV180X_CLK_WGN2 129
#define CV180X_CLK_KEYSCAN 130
#define CV180X_CLK_AHB_SF1 131
#define CV180X_CLK_VC_SRC1 132
#define CV180X_CLK_SRC_VIP_SYS_2 133
#define CV180X_CLK_PAD_VI1_VIP 134
#define CV180X_CLK_CFG_REG_VIP 135
#define CV180X_CLK_CFG_REG_VC 136
#define CV180X_CLK_AUDSRC 137
#define CV180X_CLK_APB_AUDSRC 138
#define CV180X_CLK_VC_SRC2 139
#define CV180X_CLK_PWM_SRC 140
#define CV180X_CLK_AP_DEBUG 141
#define CV180X_CLK_SRC_RTC_SYS_0 142
#define CV180X_CLK_PAD_VI2_VIP 143
#define CV180X_CLK_CSI_BE_VIP 144
#define CV180X_CLK_VIP_IP0 145
#define CV180X_CLK_VIP_IP1 146
#define CV180X_CLK_VIP_IP2 147
#define CV180X_CLK_VIP_IP3 148
#define CV180X_CLK_C906_0 149
#define CV180X_CLK_C906_1 150
#define CV180X_CLK_SRC_VIP_SYS_3 151
#define CV180X_CLK_SRC_VIP_SYS_4 152
#define CV180X_CLK_IVE_VIP 153
#define CV180X_CLK_RAW_VIP 154
#define CV180X_CLK_OSDC_VIP 155
#define CV180X_CLK_CSI_MAC2_VIP 156
#define CV180X_CLK_CAM0_VIP 157
#endif /* __DT_BINDINGS_CLK_CV180X_H__ */

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u-boot-2021.10/include/dt-bindings/clock/cv181x-clock.h Normal file
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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
*
* File Name: cv181x-clock.h
* Description:
*/
#ifndef __DT_BINDINGS_CLK_CV181X_H__
#define __DT_BINDINGS_CLK_CV181X_H__
#define CV181X_CLK_MPLL 0
#define CV181X_CLK_TPLL 1
#define CV181X_CLK_FPLL 2
#define CV181X_CLK_MIPIMPLL 3
#define CV181X_CLK_A0PLL 4
#define CV181X_CLK_DISPPLL 5
#define CV181X_CLK_CAM0PLL 6
#define CV181X_CLK_CAM1PLL 7
#define CV181X_CLK_A53 8
#define CV181X_CLK_CPU_AXI0 9
#define CV181X_CLK_CPU_GIC 10
#define CV181X_CLK_XTAL_A53 11
#define CV181X_CLK_TPU 12
#define CV181X_CLK_TPU_FAB 13
#define CV181X_CLK_AHB_ROM 14
#define CV181X_CLK_DDR_AXI_REG 15
#define CV181X_CLK_RTC_25M 16
#define CV181X_CLK_TEMPSEN 17
#define CV181X_CLK_SARADC 18
#define CV181X_CLK_EFUSE 19
#define CV181X_CLK_APB_EFUSE 20
#define CV181X_CLK_DEBUG 21
#define CV181X_CLK_XTAL_MISC 22
#define CV181X_CLK_AXI4_EMMC 23
#define CV181X_CLK_EMMC 24
#define CV181X_CLK_100K_EMMC 25
#define CV181X_CLK_AXI4_SD0 26
#define CV181X_CLK_SD0 27
#define CV181X_CLK_100K_SD0 28
#define CV181X_CLK_AXI4_SD1 29
#define CV181X_CLK_SD1 30
#define CV181X_CLK_100K_SD1 31
#define CV181X_CLK_SPI_NAND 32
#define CV181X_CLK_500M_ETH0 33
#define CV181X_CLK_AXI4_ETH0 34
#define CV181X_CLK_500M_ETH1 35
#define CV181X_CLK_AXI4_ETH1 36
#define CV181X_CLK_APB_GPIO 37
#define CV181X_CLK_APB_GPIO_INTR 38
#define CV181X_CLK_GPIO_DB 39
#define CV181X_CLK_AHB_SF 40
#define CV181X_CLK_SDMA_AXI 41
#define CV181X_CLK_SDMA_AUD0 42
#define CV181X_CLK_SDMA_AUD1 43
#define CV181X_CLK_SDMA_AUD2 44
#define CV181X_CLK_SDMA_AUD3 45
#define CV181X_CLK_APB_I2C 46
#define CV181X_CLK_APB_WDT 47
#define CV181X_CLK_PWM 48
#define CV181X_CLK_APB_SPI0 49
#define CV181X_CLK_APB_SPI1 50
#define CV181X_CLK_APB_SPI2 51
#define CV181X_CLK_APB_SPI3 52
#define CV181X_CLK_CAM0_200 53
#define CV181X_CLK_UART0 54
#define CV181X_CLK_APB_UART0 55
#define CV181X_CLK_UART1 56
#define CV181X_CLK_APB_UART1 57
#define CV181X_CLK_UART2 58
#define CV181X_CLK_APB_UART2 59
#define CV181X_CLK_UART3 60
#define CV181X_CLK_APB_UART3 61
#define CV181X_CLK_UART4 62
#define CV181X_CLK_APB_UART4 63
#define CV181X_CLK_APB_I2S0 64
#define CV181X_CLK_APB_I2S1 65
#define CV181X_CLK_APB_I2S2 66
#define CV181X_CLK_APB_I2S3 67
#define CV181X_CLK_AXI4_USB 68
#define CV181X_CLK_APB_USB 69
#define CV181X_CLK_125M_USB 70
#define CV181X_CLK_33K_USB 71
#define CV181X_CLK_12M_USB 72
#define CV181X_CLK_AXI4 73
#define CV181X_CLK_AXI6 74
#define CV181X_CLK_DSI_ESC 75
#define CV181X_CLK_AXI_VIP 76
#define CV181X_CLK_SRC_VIP_SYS_0 77
#define CV181X_CLK_SRC_VIP_SYS_1 78
#define CV181X_CLK_DISP_SRC_VIP 79
#define CV181X_CLK_AXI_VIDEO_CODEC 80
#define CV181X_CLK_VC_SRC0 81
#define CV181X_CLK_H264C 82
#define CV181X_CLK_H265C 83
#define CV181X_CLK_JPEG 84
#define CV181X_CLK_APB_JPEG 85
#define CV181X_CLK_APB_H264C 86
#define CV181X_CLK_APB_H265C 87
#define CV181X_CLK_CAM0 88
#define CV181X_CLK_CAM1 89
#define CV181X_CLK_CSI_MAC0_VIP 90
#define CV181X_CLK_CSI_MAC1_VIP 91
#define CV181X_CLK_ISP_TOP_VIP 92
#define CV181X_CLK_IMG_D_VIP 93
#define CV181X_CLK_IMG_V_VIP 94
#define CV181X_CLK_SC_TOP_VIP 95
#define CV181X_CLK_SC_D_VIP 96
#define CV181X_CLK_SC_V1_VIP 97
#define CV181X_CLK_SC_V2_VIP 98
#define CV181X_CLK_SC_V3_VIP 99
#define CV181X_CLK_DWA_VIP 100
#define CV181X_CLK_BT_VIP 101
#define CV181X_CLK_DISP_VIP 102
#define CV181X_CLK_DSI_MAC_VIP 103
#define CV181X_CLK_LVDS0_VIP 104
#define CV181X_CLK_LVDS1_VIP 105
#define CV181X_CLK_CSI0_RX_VIP 106
#define CV181X_CLK_CSI1_RX_VIP 107
#define CV181X_CLK_PAD_VI_VIP 108
#define CV181X_CLK_1M 109
#define CV181X_CLK_SPI 110
#define CV181X_CLK_I2C 111
#define CV181X_CLK_PM 112
#define CV181X_CLK_TIMER0 113
#define CV181X_CLK_TIMER1 114
#define CV181X_CLK_TIMER2 115
#define CV181X_CLK_TIMER3 116
#define CV181X_CLK_TIMER4 117
#define CV181X_CLK_TIMER5 118
#define CV181X_CLK_TIMER6 119
#define CV181X_CLK_TIMER7 120
#define CV181X_CLK_APB_I2C0 121
#define CV181X_CLK_APB_I2C1 122
#define CV181X_CLK_APB_I2C2 123
#define CV181X_CLK_APB_I2C3 124
#define CV181X_CLK_APB_I2C4 125
#define CV181X_CLK_WGN 126
#define CV181X_CLK_WGN0 127
#define CV181X_CLK_WGN1 128
#define CV181X_CLK_WGN2 129
#define CV181X_CLK_KEYSCAN 130
#define CV181X_CLK_AHB_SF1 131
#define CV181X_CLK_VC_SRC1 132
#define CV181X_CLK_SRC_VIP_SYS_2 133
#define CV181X_CLK_PAD_VI1_VIP 134
#define CV181X_CLK_CFG_REG_VIP 135
#define CV181X_CLK_CFG_REG_VC 136
#define CV181X_CLK_AUDSRC 137
#define CV181X_CLK_APB_AUDSRC 138
#define CV181X_CLK_VC_SRC2 139
#define CV181X_CLK_PWM_SRC 140
#define CV181X_CLK_AP_DEBUG 141
#define CV181X_CLK_SRC_RTC_SYS_0 142
#define CV181X_CLK_PAD_VI2_VIP 143
#define CV181X_CLK_CSI_BE_VIP 144
#define CV181X_CLK_VIP_IP0 145
#define CV181X_CLK_VIP_IP1 146
#define CV181X_CLK_VIP_IP2 147
#define CV181X_CLK_VIP_IP3 148
#define CV181X_CLK_C906_0 149
#define CV181X_CLK_C906_1 150
#define CV181X_CLK_SRC_VIP_SYS_3 151
#define CV181X_CLK_SRC_VIP_SYS_4 152
#define CV181X_CLK_IVE_VIP 153
#define CV181X_CLK_RAW_VIP 154
#define CV181X_CLK_OSDC_VIP 155
#define CV181X_CLK_CSI_MAC2_VIP 156
#define CV181X_CLK_CAM0_VIP 157
#endif /* __DT_BINDINGS_CLK_CV181X_H__ */

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u-boot-2021.10/include/dt-bindings/dma/cv180x-dmamap.h Normal file
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#ifndef __DT_BINDINGS_CV180X_DMAMAP_H__
#define __DT_BINDINGS_CV180XS_DMAMAP_H__
#define CVI_I2S0_RX 0
#define CVI_I2S0_TX 1
#define CVI_I2S1_RX 2
#define CVI_I2S1_TX 3
#define CVI_I2S2_RX 4
#define CVI_I2S2_TX 5
#define CVI_I2S3_RX 6
#define CVI_I2S3_TX 7
#define CVI_UART0_RX 8
#define CVI_UART0_TX 9
#define CVI_UART1_RX 10
#define CVI_UART1_TX 11
#define CVI_UART2_RX 12
#define CVI_UART2_TX 13
#define CVI_UART3_RX 14
#define CVI_UART3_TX 15
#define CVI_SPI0_RX 16
#define CVI_SPI0_TX 17
#define CVI_SPI1_RX 18
#define CVI_SPI1_TX 19
#define CVI_SPI2_RX 20
#define CVI_SPI2_TX 21
#define CVI_SPI3_RX 22
#define CVI_SPI3_TX 23
#define CVI_I2C0_RX 24
#define CVI_I2C0_TX 25
#define CVI_I2C1_RX 26
#define CVI_I2C1_TX 27
#define CVI_I2C2_RX 28
#define CVI_I2C2_TX 29
#define CVI_I2C3_RX 30
#define CVI_I2C3_TX 31
#define CVI_I2C4_RX 32
#define CVI_I2C4_TX 33
#define CVI_TDM0_RX 34
#define CVI_TDM0_TX 35
#define CVI_TDM1_RX 36
#define CVI_AUDSRC 37
#define CVI_SPI_NAND 38
#define CVI_SPI_NOR 39
#define CVI_UART4_RX 40
#define CVI_UART4_TX 41
#define CVI_SPI_NOR1 42
#endif

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u-boot-2021.10/include/dt-bindings/dma/cv181x-dmamap.h Normal file
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#ifndef __DT_BINDINGS_CV181X_DMAMAP_H__
#define __DT_BINDINGS_CV181X_DMAMAP_H__
#define CVI_I2S0_RX 0
#define CVI_I2S0_TX 1
#define CVI_I2S1_RX 2
#define CVI_I2S1_TX 3
#define CVI_I2S2_RX 4
#define CVI_I2S2_TX 5
#define CVI_I2S3_RX 6
#define CVI_I2S3_TX 7
#define CVI_UART0_RX 8
#define CVI_UART0_TX 9
#define CVI_UART1_RX 10
#define CVI_UART1_TX 11
#define CVI_UART2_RX 12
#define CVI_UART2_TX 13
#define CVI_UART3_RX 14
#define CVI_UART3_TX 15
#define CVI_SPI0_RX 16
#define CVI_SPI0_TX 17
#define CVI_SPI1_RX 18
#define CVI_SPI1_TX 19
#define CVI_SPI2_RX 20
#define CVI_SPI2_TX 21
#define CVI_SPI3_RX 22
#define CVI_SPI3_TX 23
#define CVI_I2C0_RX 24
#define CVI_I2C0_TX 25
#define CVI_I2C1_RX 26
#define CVI_I2C1_TX 27
#define CVI_I2C2_RX 28
#define CVI_I2C2_TX 29
#define CVI_I2C3_RX 30
#define CVI_I2C3_TX 31
#define CVI_I2C4_RX 32
#define CVI_I2C4_TX 33
#define CVI_TDM0_RX 34
#define CVI_TDM0_TX 35
#define CVI_TDM1_RX 36
#define CVI_AUDSRC 37
#define CVI_SPI_NAND 38
#define CVI_SPI_NOR 39
#define CVI_UART4_RX 40
#define CVI_UART4_TX 41
#define CVI_SPI_NOR1 42
#endif

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u-boot-2021.10/include/dt-bindings/reset/cv180x-resets.h Normal file
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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: cvi_template.h
* Description:
*/
#ifndef __DT_BINDINGS_RST_CV180X_H__
#define __DT_BINDINGS_RST_CV180X_H__
#define RST_MAINRST_AP 0
#define RST_SECONDRST_AP 1
#define RST_DDR 2
#define RST_H264C 3
#define RST_JPEG 4
#define RST_H265C 5
#define RST_VIPSYS 6
#define RST_TDMA 7
#define RST_TPU 8
#define RST_TPUSYS 9
#define RST_TSM 10
#define RST_USB 11
#define RST_ETH0 12
#define RST_ETH1 13
#define RST_NAND 14
#define RST_EMMC 15
#define RST_SD0 16
#define RST_SD1 17
#define RST_SDMA 18
#define RST_I2S0 19
#define RST_I2S1 20
#define RST_I2S2 21
#define RST_I2S3 22
#define RST_UART0 23
#define RST_UART1 24
#define RST_UART2 25
#define RST_UART3 26
#define RST_I2C0 27
#define RST_I2C1 28
#define RST_I2C2 29
#define RST_I2C3 30
#define RST_I2C4 31
#define RST_PWM0 32
#define RST_PWM1 33
#define RST_PWM2 34
#define RST_PWM3 35
#define RST_PWM4 36
#define RST_PWM5 37
#define RST_PWM6 38
#define RST_PWM7 39
#define RST_SPI0 40
#define RST_SPI1 41
#define RST_SPI2 42
#define RST_SPI3 43
#define RST_GPIO0 44
#define RST_GPIO1 45
#define RST_GPIO2 46
#define RST_EFUSE 47
#define RST_WDT 48
#define RST_AHBRST_ROM 49
#define RST_SPIC 50
#define RST_TEMPSEN 51
#define RST_SARADC 52
#define RST_PCIERST_CDMA 53
#define RST_PCIERST_SMMU 54
#define RST_PCIERST_PCIE 55
#define RST_PCIERST_FABS 56
#define RST_PCIERST_IRQ 57
#define RST_COMBORST_PHY0 58
#define RST_COMBORST_PHY1 59
#define RST_USB1 60
#define RST_SPIRST_NAND 61
#define RST_SE 62
#define RST_RTCRST_SWRST_ONLY 63
#define RST_CPUCORE0 64
#define RST_CPUCORE1 65
#define RST_CPUCORE2 66
#define RST_CPUCORE3 67
#define RST_DSIPHY 68
#define RST_DSIPHYRST_APB 69
#define RST_CSIPHY0 70
#define RST_CSIPHY0RST_APB 71
#define RST_CSIPHY1 72
#define RST_CSIPHY1RST_APB 73
#define RST_UART4 74
#define RST_GPIO3 75
#define RST_SYSTEM 76
#define RST_TIMER 77
#define RST_TIMER0 78
#define RST_TIMER1 79
#define RST_TIMER2 80
#define RST_TIMER3 81
#define RST_TIMER4 82
#define RST_TIMER5 83
#define RST_TIMER6 84
#define RST_TIMER7 85
#define RST_WGN0 86
#define RST_WGN1 87
#define RST_WGN2 88
#define RST_KEYSCAN 89
#define RST_SPIC1 90
#define RST_AUDDAC 91
#define RST_AUDDACRST_APB 92
#define RST_AUDADC 93
#define RST_AUDADCRST_APB 94
#define RST_VCSYS 95
#define RST_ETHPHY 96
#define RST_ETHPHYRST_APB 97
#define RST_AUDSRC 98
#define RST_AUTO_CLEAR_CPUCORE0 99
#define RST_AUTO_CLEAR_CPUCORE1 100
#define RST_AUTO_CLEAR_CPUCORE2 101
#define RST_AUTO_CLEAR_CPUCORE3 102
#define RST_AUTO_CLEAR_MAINRST_AP 103
#define RST_AUTO_CLEAR_SECONDRST_AP 104
#define CLK_RST_A53 0
#define CLK_RST_50M_A53 1
#define CLK_RST_AHB_ROM 2
#define CLK_RST_AXI_SRAM 3
#define CLK_RST_DDR_AXI 4
#define CLK_RST_EFUSE 5
#define CLK_RST_APB_EFUSE 6
#define CLK_RST_AXI_EMMC 7
#define CLK_RST_EMMC 8
#define CLK_RST_100K_EMMC 9
#define CLK_RST_AXI_SD 10
#define CLK_RST_SD 11
#define CLK_RST_100K_SD 12
#define CLK_RST_500M_ETH0 13
#define CLK_RST_AXI_ETH0 14
#define CLK_RST_500M_ETH1 15
#define CLK_RST_AXI_ETH1 16
#define CLK_RST_AXI_GDMA 17
#define CLK_RST_APB_GPIO 18
#define CLK_RST_APB_GPIO_INTR 19
#define CLK_RST_GPIO_DB 20
#define CLK_RST_AXI_MINER 21
#define CLK_RST_AHB_SF 22
#define CLK_RST_SDMA_AXI 23
#define CLK_RST_SDMA_AUD 24
#define CLK_RST_APB_I2C 25
#define CLK_RST_APB_WDT 26
#define CLK_RST_APB_JPEG 27
#define CLK_RST_JPEG_AXI 28
#define CLK_RST_AXI_NF 29
#define CLK_RST_APB_NF 30
#define CLK_RST_NF 31
#define CLK_RST_APB_PWM 32
#define CLK_RST_RV 33
#define CLK_RST_APB_SPI 34
#define CLK_RST_TPU_AXI 35
#define CLK_RST_UART_500M 36
#define CLK_RST_APB_UART 37
#define CLK_RST_APB_I2S 38
#define CLK_RST_AXI_USB 39
#define CLK_RST_APB_USB 40
#define CLK_RST_125M_USB 41
#define CLK_RST_33K_USB 42
#define CLK_RST_12M_USB 43
#define CLK_RST_APB_VIDEO 44
#define CLK_RST_VIDEO_AXI 45
#define CLK_RST_VPP_AXI 46
#define CLK_RST_APB_VPP 47
#define CLK_RST_AXI1 48
#define CLK_RST_AXI2 49
#define CLK_RST_AXI3 50
#define CLK_RST_AXI4 51
#define CLK_RST_AXI5 52
#define CLK_RST_AXI6 53
#endif /* _DT_BINDINGS_RST_CV180X_H_ */

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/*
* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
*
* File Name: cvi_template.h
* Description:
*/
#ifndef __DT_BINDINGS_RST_CV181X_H__
#define __DT_BINDINGS_RST_CV181X_H__
#define RST_MAINRST_AP 0
#define RST_SECONDRST_AP 1
#define RST_DDR 2
#define RST_H264C 3
#define RST_JPEG 4
#define RST_H265C 5
#define RST_VIPSYS 6
#define RST_TDMA 7
#define RST_TPU 8
#define RST_TPUSYS 9
#define RST_TSM 10
#define RST_USB 11
#define RST_ETH0 12
#define RST_ETH1 13
#define RST_NAND 14
#define RST_EMMC 15
#define RST_SD0 16
#define RST_SD1 17
#define RST_SDMA 18
#define RST_I2S0 19
#define RST_I2S1 20
#define RST_I2S2 21
#define RST_I2S3 22
#define RST_UART0 23
#define RST_UART1 24
#define RST_UART2 25
#define RST_UART3 26
#define RST_I2C0 27
#define RST_I2C1 28
#define RST_I2C2 29
#define RST_I2C3 30
#define RST_I2C4 31
#define RST_PWM0 32
#define RST_PWM1 33
#define RST_PWM2 34
#define RST_PWM3 35
#define RST_PWM4 36
#define RST_PWM5 37
#define RST_PWM6 38
#define RST_PWM7 39
#define RST_SPI0 40
#define RST_SPI1 41
#define RST_SPI2 42
#define RST_SPI3 43
#define RST_GPIO0 44
#define RST_GPIO1 45
#define RST_GPIO2 46
#define RST_EFUSE 47
#define RST_WDT 48
#define RST_AHBRST_ROM 49
#define RST_SPIC 50
#define RST_TEMPSEN 51
#define RST_SARADC 52
#define RST_PCIERST_CDMA 53
#define RST_PCIERST_SMMU 54
#define RST_PCIERST_PCIE 55
#define RST_PCIERST_FABS 56
#define RST_PCIERST_IRQ 57
#define RST_COMBORST_PHY0 58
#define RST_COMBORST_PHY1 59
#define RST_USB1 60
#define RST_SPIRST_NAND 61
#define RST_SE 62
#define RST_RTCRST_SWRST_ONLY 63
#define RST_CPUCORE0 64
#define RST_CPUCORE1 65
#define RST_CPUCORE2 66
#define RST_CPUCORE3 67
#define RST_DSIPHY 68
#define RST_DSIPHYRST_APB 69
#define RST_CSIPHY0 70
#define RST_CSIPHY0RST_APB 71
#define RST_CSIPHY1 72
#define RST_CSIPHY1RST_APB 73
#define RST_UART4 74
#define RST_GPIO3 75
#define RST_SYSTEM 76
#define RST_TIMER 77
#define RST_TIMER0 78
#define RST_TIMER1 79
#define RST_TIMER2 80
#define RST_TIMER3 81
#define RST_TIMER4 82
#define RST_TIMER5 83
#define RST_TIMER6 84
#define RST_TIMER7 85
#define RST_WGN0 86
#define RST_WGN1 87
#define RST_WGN2 88
#define RST_KEYSCAN 89
#define RST_SPIC1 90
#define RST_AUDDAC 91
#define RST_AUDDACRST_APB 92
#define RST_AUDADC 93
#define RST_AUDADCRST_APB 94
#define RST_VCSYS 95
#define RST_ETHPHY 96
#define RST_ETHPHYRST_APB 97
#define RST_AUDSRC 98
#define RST_AUTO_CLEAR_CPUCORE0 99
#define RST_AUTO_CLEAR_CPUCORE1 100
#define RST_AUTO_CLEAR_CPUCORE2 101
#define RST_AUTO_CLEAR_CPUCORE3 102
#define RST_AUTO_CLEAR_MAINRST_AP 103
#define RST_AUTO_CLEAR_SECONDRST_AP 104
#define CLK_RST_A53 0
#define CLK_RST_50M_A53 1
#define CLK_RST_AHB_ROM 2
#define CLK_RST_AXI_SRAM 3
#define CLK_RST_DDR_AXI 4
#define CLK_RST_EFUSE 5
#define CLK_RST_APB_EFUSE 6
#define CLK_RST_AXI_EMMC 7
#define CLK_RST_EMMC 8
#define CLK_RST_100K_EMMC 9
#define CLK_RST_AXI_SD 10
#define CLK_RST_SD 11
#define CLK_RST_100K_SD 12
#define CLK_RST_500M_ETH0 13
#define CLK_RST_AXI_ETH0 14
#define CLK_RST_500M_ETH1 15
#define CLK_RST_AXI_ETH1 16
#define CLK_RST_AXI_GDMA 17
#define CLK_RST_APB_GPIO 18
#define CLK_RST_APB_GPIO_INTR 19
#define CLK_RST_GPIO_DB 20
#define CLK_RST_AXI_MINER 21
#define CLK_RST_AHB_SF 22
#define CLK_RST_SDMA_AXI 23
#define CLK_RST_SDMA_AUD 24
#define CLK_RST_APB_I2C 25
#define CLK_RST_APB_WDT 26
#define CLK_RST_APB_JPEG 27
#define CLK_RST_JPEG_AXI 28
#define CLK_RST_AXI_NF 29
#define CLK_RST_APB_NF 30
#define CLK_RST_NF 31
#define CLK_RST_APB_PWM 32
#define CLK_RST_RV 33
#define CLK_RST_APB_SPI 34
#define CLK_RST_TPU_AXI 35
#define CLK_RST_UART_500M 36
#define CLK_RST_APB_UART 37
#define CLK_RST_APB_I2S 38
#define CLK_RST_AXI_USB 39
#define CLK_RST_APB_USB 40
#define CLK_RST_125M_USB 41
#define CLK_RST_33K_USB 42
#define CLK_RST_12M_USB 43
#define CLK_RST_APB_VIDEO 44
#define CLK_RST_VIDEO_AXI 45
#define CLK_RST_VPP_AXI 46
#define CLK_RST_APB_VPP 47
#define CLK_RST_AXI1 48
#define CLK_RST_AXI2 49
#define CLK_RST_AXI3 50
#define CLK_RST_AXI4 51
#define CLK_RST_AXI5 52
#define CLK_RST_AXI6 53
#endif /* _DT_BINDINGS_RST_CV181X_H_ */