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[uboot] porting cvitek asic chips:

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1. add cvitek folders to u-boot-2021.10
	2. add cv183x/cv182x part
	3. add cv181x/cv180x part

Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
This commit is contained in:
sam.xiang
2023-02-22 13:43:23 +08:00
parent f8fc109960
commit 3a4bcfca2f
244 changed files with 41355 additions and 1273 deletions
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42
u-boot-2021.10/include/linux/mtd/cfi.h
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@ -11,22 +11,30 @@
#define CFI_ID_ANY 0xFFFF
#define CFI_MFR_CONTINUATION 0x007F
#define CFI_MFR_AMD 0x0001
#define CFI_MFR_AMIC 0x0037
#define CFI_MFR_ATMEL 0x001F
#define CFI_MFR_EON 0x001C
#define CFI_MFR_FUJITSU 0x0004
#define CFI_MFR_HYUNDAI 0x00AD
#define CFI_MFR_INTEL 0x0089
#define CFI_MFR_MACRONIX 0x00C2
#define CFI_MFR_NEC 0x0010
#define CFI_MFR_PMC 0x009D
#define CFI_MFR_SAMSUNG 0x00EC
#define CFI_MFR_SHARP 0x00B0
#define CFI_MFR_SST 0x00BF
#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
#define CFI_MFR_MICRON 0x002C /* Micron */
#define CFI_MFR_TOSHIBA 0x0098
#define CFI_MFR_WINBOND 0x00DA
#define CFI_MFR_AMD 0x0001
#define CFI_MFR_AMIC 0x0037
#define CFI_MFR_ATMEL 0x001F
#define CFI_MFR_EON 0x001C
#define CFI_MFR_FUJITSU 0x0004
#define CFI_MFR_HYUNDAI 0x00AD
#define CFI_MFR_INTEL 0x0089
#define CFI_MFR_MACRONIX 0x00C2
#define CFI_MFR_NEC 0x0010
#define CFI_MFR_PMC 0x009D
#define CFI_MFR_SAMSUNG 0x00EC
#define CFI_MFR_SHARP 0x00B0
#define CFI_MFR_SST 0x00BF
#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
#define CFI_MFR_MICRON 0x002C /* Micron */
#define CFI_MFR_TOSHIBA 0x0098
#define CFI_MFR_WINBOND 0x00DA
#define CFI_MFR_GIGADEVICE 0x00C8
#define CFI_MFR_XMC 0x0020
#define CFI_MFR_EON 0x001C
#define CFI_MFR_ZBIT 0x005E
#define CFI_MFR_XTX 0x000B
#define CFI_MFR_FM 0x00F8
#define CFI_MFR_JUYANG 0x004A
#define CFI_MFR_BOYA 0x0068
#endif /* __MTD_CFI_H__ */

9
u-boot-2021.10/include/linux/mtd/rawnand.h
View File

@ -184,6 +184,8 @@ enum nand_ecc_algo {
* Option constants for bizarre disfunctionality and real
* features.
*/
/* Chip can not auto increment pages */
#define NAND_NO_AUTOINCR 0x00000001
/* Buswidth is 16 bit */
#define NAND_BUSWIDTH_16 0x00000002
/* Device supports partial programming without padding */
@ -251,6 +253,11 @@ enum nand_ecc_algo {
*/
#define NAND_USE_BOUNCE_BUFFER 0x00100000
/*
* Some devices only support 1 bit transfer mode
*/
#define NAND_ONLY_ONE_BIT_MODE 0x10000000
/* Options set by nand scan */
/* bbt has already been read */
#define NAND_BBT_SCANNED 0x40000000
@ -945,7 +952,7 @@ struct nand_chip {
int jedec_version;
struct nand_onfi_params onfi_params;
struct nand_jedec_params jedec_params;
struct nand_data_interface *data_interface;
int read_retries;

14
u-boot-2021.10/include/linux/mtd/spi-nor.h
View File

@ -19,7 +19,7 @@
* Sometimes these are the same as CFI IDs, but sometimes they aren't.
*/
#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
#define SNOR_MFR_GIGADEVICE 0xc8
#define SNOR_MFR_GIGADEVICE CFI_MFR_GIGADEVICE
#define SNOR_MFR_INTEL CFI_MFR_INTEL
#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
#define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
@ -27,8 +27,16 @@
#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
#define SNOR_MFR_SPANSION CFI_MFR_AMD
#define SNOR_MFR_SST CFI_MFR_SST
#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
#define SNOR_MFR_WINBOND 0xEF /* Also used by some Spansion */
#define SNOR_MFR_CYPRESS 0x34
#define SNOR_MFR_XMC CFI_MFR_XMC
#define SNOR_MFR_EON CFI_MFR_EON
#define SNOR_MFR_ZBIT CFI_MFR_ZBIT
#define SNOR_MFR_XTX CFI_MFR_XTX
#define SNOR_MFR_FM CFI_MFR_FM
#define SNOR_MFR_JUYANG CFI_MFR_JUYANG
#define SNOR_MFR_BOYA CFI_MFR_BOYA
#define SNOR_MFR_PY 0x85
/*
* Note on opcode nomenclature: some opcodes have a format like
@ -43,7 +51,7 @@
#define SPINOR_OP_RDSR 0x05 /* Read status register */
#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
#define SPINOR_OP_WRSR2 0x31 /* Write status register 2 */
#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */