[uboot] porting cvitek asic chips:
1. add cvitek folders to u-boot-2021.10 2. add cv183x/cv182x part 3. add cv181x/cv180x part Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
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@ -19,7 +19,7 @@
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* Sometimes these are the same as CFI IDs, but sometimes they aren't.
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*/
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#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
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#define SNOR_MFR_GIGADEVICE 0xc8
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#define SNOR_MFR_GIGADEVICE CFI_MFR_GIGADEVICE
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#define SNOR_MFR_INTEL CFI_MFR_INTEL
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#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
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#define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
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@ -27,8 +27,16 @@
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#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
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#define SNOR_MFR_SPANSION CFI_MFR_AMD
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#define SNOR_MFR_SST CFI_MFR_SST
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#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
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#define SNOR_MFR_WINBOND 0xEF /* Also used by some Spansion */
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#define SNOR_MFR_CYPRESS 0x34
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#define SNOR_MFR_XMC CFI_MFR_XMC
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#define SNOR_MFR_EON CFI_MFR_EON
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#define SNOR_MFR_ZBIT CFI_MFR_ZBIT
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#define SNOR_MFR_XTX CFI_MFR_XTX
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#define SNOR_MFR_FM CFI_MFR_FM
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#define SNOR_MFR_JUYANG CFI_MFR_JUYANG
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#define SNOR_MFR_BOYA CFI_MFR_BOYA
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#define SNOR_MFR_PY 0x85
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/*
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* Note on opcode nomenclature: some opcodes have a format like
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@ -43,7 +51,7 @@
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#define SPINOR_OP_RDSR 0x05 /* Read status register */
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#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
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#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
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#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
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#define SPINOR_OP_WRSR2 0x31 /* Write status register 2 */
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#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
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#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
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