From 526f902b6abdeba9d3a795c2794166d3b939eca3 Mon Sep 17 00:00:00 2001 From: "sam.xiang" Date: Wed, 24 May 2023 00:03:55 +0800 Subject: [PATCH] middleware: weekly update 2023-05-22 1. update awb algo 2. support some sensor 3. add cv181x ko_shrink 4. update codec driver Change-Id: Ie0cf772066a25dcb12074ee562cdabd71d63cd06 --- middleware/v2/.gitignore | 45 +- middleware/v2/component/isp/sensor.mk | 7 + .../v2/component/isp/sensor/cv180x/Makefile | 20 + .../isp/sensor/cv180x/gcore_gc0312/Makefile | 36 + .../sensor/cv180x/gcore_gc0312/gc0312_cmos.c | 303 ++ .../cv180x/gcore_gc0312/gc0312_cmos_ex.h | 64 + .../cv180x/gcore_gc0312/gc0312_cmos_param.h | 71 + .../cv180x/gcore_gc0312/gc0312_sensor_ctl.c | 555 ++++ .../isp/sensor/cv180x/lontium_lt6911/Makefile | 36 + .../cv180x/lontium_lt6911/lt6911_cmos.c | 423 +++ .../cv180x/lontium_lt6911/lt6911_cmos_ex.h | 63 + .../cv180x/lontium_lt6911/lt6911_cmos_param.h | 75 + .../cv180x/lontium_lt6911/lt6911_sensor_ctl.c | 215 ++ .../isp/sensor/cv180x/sms_sc2331_1L/Makefile | 36 + .../cv180x/sms_sc2331_1L/sc2331_1L_cmos.c | 990 ++++++ .../cv180x/sms_sc2331_1L/sc2331_1L_cmos_ex.h | 80 + .../sms_sc2331_1L/sc2331_1L_cmos_param.h | 125 + .../sms_sc2331_1L/sc2331_1L_sensor_ctl.c | 388 +++ .../isp/sensor/cv180x/sms_sc2336p/Makefile | 36 + .../sensor/cv180x/sms_sc2336p/sc2336p_cmos.c | 905 ++++++ .../cv180x/sms_sc2336p/sc2336p_cmos_ex.h | 85 + .../cv180x/sms_sc2336p/sc2336p_cmos_param.h | 125 + .../cv180x/sms_sc2336p/sc2336p_sensor_ctl.c | 410 +++ .../isp/sensor/cv180x/sms_sc4336p/Makefile | 36 + .../sensor/cv180x/sms_sc4336p/sc4336p_cmos.c | 916 ++++++ .../cv180x/sms_sc4336p/sc4336p_cmos_ex.h | 78 + .../cv180x/sms_sc4336p/sc4336p_cmos_param.h | 121 + .../cv180x/sms_sc4336p/sc4336p_sensor_ctl.c | 384 +++ .../isp/sensor/cv180x/sms_sc5336_2L/Makefile | 36 + .../cv180x/sms_sc5336_2L/sc5336_2L_cmos.c | 1062 +++++++ .../cv180x/sms_sc5336_2L/sc5336_2L_cmos_ex.h | 85 + .../sms_sc5336_2L/sc5336_2L_cmos_param.h | 226 ++ .../sms_sc5336_2L/sc5336_2L_sensor_ctl.c | 463 +++ .../isp/sensor/cv180x/soi_q03p/Makefile | 36 + .../isp/sensor/cv180x/soi_q03p/q03p_cmos.c | 841 +++++ .../isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h | 83 + .../sensor/cv180x/soi_q03p/q03p_cmos_param.h | 123 + .../sensor/cv180x/soi_q03p/q03p_sensor_ctl.c | 361 +++ .../v2/component/isp/sensor/cv181x/Makefile | 20 + .../isp/sensor/cv181x/gcore_gc0312/Makefile | 36 + .../sensor/cv181x/gcore_gc0312/gc0312_cmos.c | 303 ++ .../cv181x/gcore_gc0312/gc0312_cmos_ex.h | 64 + .../cv181x/gcore_gc0312/gc0312_cmos_param.h | 71 + .../cv181x/gcore_gc0312/gc0312_sensor_ctl.c | 555 ++++ .../isp/sensor/cv181x/lontium_lt6911/Makefile | 36 + .../cv181x/lontium_lt6911/lt6911_cmos.c | 423 +++ .../cv181x/lontium_lt6911/lt6911_cmos_ex.h | 63 + .../cv181x/lontium_lt6911/lt6911_cmos_param.h | 75 + .../cv181x/lontium_lt6911/lt6911_sensor_ctl.c | 215 ++ .../isp/sensor/cv181x/sms_sc2331_1L/Makefile | 36 + .../cv181x/sms_sc2331_1L/sc2331_1L_cmos.c | 990 ++++++ .../cv181x/sms_sc2331_1L/sc2331_1L_cmos_ex.h | 80 + .../sms_sc2331_1L/sc2331_1L_cmos_param.h | 125 + .../sms_sc2331_1L/sc2331_1L_sensor_ctl.c | 388 +++ .../isp/sensor/cv181x/sms_sc2336p/Makefile | 36 + .../sensor/cv181x/sms_sc2336p/sc2336p_cmos.c | 905 ++++++ .../cv181x/sms_sc2336p/sc2336p_cmos_ex.h | 85 + .../cv181x/sms_sc2336p/sc2336p_cmos_param.h | 125 + .../cv181x/sms_sc2336p/sc2336p_sensor_ctl.c | 410 +++ .../isp/sensor/cv181x/sms_sc4336p/Makefile | 36 + .../sensor/cv181x/sms_sc4336p/sc4336p_cmos.c | 916 ++++++ .../cv181x/sms_sc4336p/sc4336p_cmos_ex.h | 78 + .../cv181x/sms_sc4336p/sc4336p_cmos_param.h | 121 + .../cv181x/sms_sc4336p/sc4336p_sensor_ctl.c | 384 +++ .../isp/sensor/cv181x/sms_sc5336_2L/Makefile | 36 + .../cv181x/sms_sc5336_2L/sc5336_2L_cmos.c | 1062 +++++++ .../cv181x/sms_sc5336_2L/sc5336_2L_cmos_ex.h | 85 + .../sms_sc5336_2L/sc5336_2L_cmos_param.h | 226 ++ .../sms_sc5336_2L/sc5336_2L_sensor_ctl.c | 463 +++ .../isp/sensor/cv181x/soi_q03p/Makefile | 36 + .../isp/sensor/cv181x/soi_q03p/q03p_cmos.c | 841 +++++ .../isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h | 83 + .../sensor/cv181x/soi_q03p/q03p_cmos_param.h | 123 + .../sensor/cv181x/soi_q03p/q03p_sensor_ctl.c | 361 +++ .../v2/component/panel/cv180x/dsi_gm8775c.h | 2 +- .../v2/component/panel/cv180x/dsi_lt9611.h | 140 + .../v2/component/panel/cv181x/dsi_gm8775c.h | 2 +- .../v2/component/panel/cv181x/dsi_lt9611.h | 140 + middleware/v2/cv180x/ko/cv180x_vcodec.ko | Bin 60328 -> 60328 bytes middleware/v2/cv180x/ko/cv180x_vi.ko | Bin 614512 -> 617856 bytes middleware/v2/cv180x/ko/cv180x_vpss.ko | Bin 506424 -> 508832 bytes middleware/v2/cv180x/ko/cvi_mipi_rx.ko | Bin 111904 -> 111904 bytes middleware/v2/cv180x/ko/cvi_vc_driver.ko | Bin 1625384 -> 1625248 bytes .../v2/cv180x/ko_shrink/cv180x_vcodec.ko | Bin 59376 -> 59376 bytes middleware/v2/cv180x/ko_shrink/cv180x_vi.ko | Bin 524328 -> 527632 bytes middleware/v2/cv180x/ko_shrink/cv180x_vpss.ko | Bin 485224 -> 485576 bytes middleware/v2/cv180x/ko_shrink/cvi_mipi_rx.ko | Bin 94904 -> 94904 bytes .../v2/cv180x/ko_shrink/cvi_vc_driver.ko | Bin 1568664 -> 1568504 bytes .../v2/cv180x/lib_glibc_riscv64/libawb.a | Bin 1581944 -> 1567296 bytes .../v2/cv180x/lib_glibc_riscv64/libawb.so | Bin 310536 -> 309184 bytes .../v2/cv180x/lib_musl_riscv64/libawb.a | Bin 1574640 -> 1560240 bytes .../v2/cv180x/lib_musl_riscv64/libawb.so | Bin 308248 -> 306976 bytes middleware/v2/cv181x/ko/cv181x_vcodec.ko | Bin 60328 -> 60328 bytes middleware/v2/cv181x/ko/cv181x_vi.ko | Bin 614848 -> 618208 bytes middleware/v2/cv181x/ko/cv181x_vpss.ko | Bin 508232 -> 510656 bytes middleware/v2/cv181x/ko/cvi_mipi_rx.ko | Bin 122776 -> 122840 bytes middleware/v2/cv181x/ko/cvi_vc_driver.ko | Bin 1625336 -> 1625136 bytes .../cv181x/ko_shrink/3rd/cvi_wiegand_gpio.ko | Bin 0 -> 23712 bytes middleware/v2/cv181x/ko_shrink/cv181x_base.ko | Bin 0 -> 146576 bytes .../cv181x/ko_shrink/cv181x_clock_cooling.ko | Bin 0 -> 11920 bytes middleware/v2/cv181x/ko_shrink/cv181x_dwa.ko | Bin 0 -> 75264 bytes .../v2/cv181x/ko_shrink/cv181x_fast_image.ko | Bin 0 -> 36912 bytes middleware/v2/cv181x/ko_shrink/cv181x_ive.ko | Bin 0 -> 369488 bytes middleware/v2/cv181x/ko_shrink/cv181x_jpeg.ko | Bin 0 -> 54520 bytes .../v2/cv181x/ko_shrink/cv181x_mipi_tx.ko | Bin 0 -> 41912 bytes middleware/v2/cv181x/ko_shrink/cv181x_mon.ko | Bin 0 -> 35960 bytes middleware/v2/cv181x/ko_shrink/cv181x_pwm.ko | Bin 0 -> 12016 bytes middleware/v2/cv181x/ko_shrink/cv181x_rgn.ko | Bin 0 -> 126128 bytes middleware/v2/cv181x/ko_shrink/cv181x_rtc.ko | Bin 0 -> 15128 bytes .../v2/cv181x/ko_shrink/cv181x_rtos_cmdqu.ko | Bin 0 -> 27656 bytes .../v2/cv181x/ko_shrink/cv181x_saradc.ko | Bin 0 -> 18008 bytes middleware/v2/cv181x/ko_shrink/cv181x_sys.ko | Bin 0 -> 49200 bytes middleware/v2/cv181x/ko_shrink/cv181x_tpu.ko | Bin 0 -> 51456 bytes .../v2/cv181x/ko_shrink/cv181x_vcodec.ko | Bin 0 -> 58200 bytes middleware/v2/cv181x/ko_shrink/cv181x_vi.ko | Bin 0 -> 523088 bytes middleware/v2/cv181x/ko_shrink/cv181x_vo.ko | Bin 0 -> 191240 bytes middleware/v2/cv181x/ko_shrink/cv181x_vpss.ko | Bin 0 -> 478760 bytes middleware/v2/cv181x/ko_shrink/cv181x_wdt.ko | Bin 0 -> 11040 bytes middleware/v2/cv181x/ko_shrink/cvi_mipi_rx.ko | Bin 0 -> 105840 bytes .../v2/cv181x/ko_shrink/cvi_vc_driver.ko | Bin 0 -> 1538376 bytes middleware/v2/cv181x/ko_shrink/cvi_wiegand.ko | Bin 0 -> 18920 bytes .../v2/cv181x/ko_shrink/cviaudio_core.ko | Bin 0 -> 133760 bytes middleware/v2/cv181x/ko_shrink/snsr_i2c.ko | Bin 0 -> 13664 bytes .../v2/cv181x/lib_glibc_riscv64/libawb.a | Bin 1577896 -> 1563504 bytes .../v2/cv181x/lib_glibc_riscv64/libawb.so | Bin 309792 -> 308520 bytes .../v2/cv181x/lib_musl_riscv64/libawb.a | Bin 1571088 -> 1556440 bytes .../v2/cv181x/lib_musl_riscv64/libawb.so | Bin 307656 -> 306312 bytes middleware/v2/include/cvi_sns_ctrl.h | 7 + middleware/v2/sample/common/Kbuild | 28 + middleware/v2/sample/common/sample_comm.h | 7 + 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100644 middleware/v2/cv181x/ko_shrink/cv181x_sys.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cv181x_tpu.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cv181x_vcodec.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cv181x_vi.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cv181x_vo.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cv181x_vpss.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cv181x_wdt.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cvi_mipi_rx.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cvi_vc_driver.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cvi_wiegand.ko create mode 100644 middleware/v2/cv181x/ko_shrink/cviaudio_core.ko create mode 100644 middleware/v2/cv181x/ko_shrink/snsr_i2c.ko delete mode 100644 middleware/v2/sample/mipi_tx/Kbuild create mode 100644 middleware/v2/sample/mipi_tx/lt9611/Makefile create mode 100644 middleware/v2/sample/mipi_tx/lt9611/lt9611.c create mode 100644 middleware/v2/sample/mipi_tx/lt9611/lt9611.h diff --git a/middleware/v2/.gitignore b/middleware/v2/.gitignore index c51bf680a..988a613e7 100644 --- a/middleware/v2/.gitignore +++ b/middleware/v2/.gitignore @@ -30,45 +30,11 @@ sample/vio/sample_vio sample/vdecvo/sample_vdecvo sample/multivenc/sample_multivenc sample/ir_auto/ir_auto -sample/ive/sample_16bitto8bit -sample/ive/sample_add -sample/ive/sample_and -sample/ive/sample_bernsen -sample/ive/sample_bgmodel -sample/ive/sample_cannyedge -sample/ive/sample_cannyhysedge -sample/ive/sample_csc -sample/ive/sample_dilate -sample/ive/sample_dma -sample/ive/sample_erode -sample/ive/sample_filter -sample/ive/sample_filterandcsc -sample/ive/sample_framediffmotion -sample/ive/sample_gmm -sample/ive/sample_gmm2 -sample/ive/sample_gradfg -sample/ive/sample_hist -sample/ive/sample_integ -sample/ive/sample_lbp -sample/ive/sample_magandang -sample/ive/sample_map -sample/ive/sample_ncc -sample/ive/sample_normgrad -sample/ive/sample_or -sample/ive/sample_ordstatfilter -sample/ive/sample_query -sample/ive/sample_resize -sample/ive/sample_sad -sample/ive/sample_sobel -sample/ive/sample_stcandicorner -sample/ive/sample_sub -sample/ive/sample_thresh -sample/ive/sample_thresh_S16 -sample/ive/sample_thresh_U16 -sample/ive/sample_xor +sample/mipi_tx/lt9611/lt9611 sample/osdc/sample_osdc sample/scene_auto/sample_scene_auto sample/sensor_test/sensor_test +sample/tp2863_tp2803/sample_test_tp2863_tp2803 self_test/cvi_test/cvi_test self_test/cvi_test/res @@ -82,6 +48,9 @@ self_test/rgn_ut/rgn_ut self_test/dwa_ut/dwa_ut self_test/vb_ut/vb_ut self_test/sys_ut/sys_ut +self_test/vc_test/cvi_h264_enc_test +self_test/vc_test/cvi_h265_enc_test +self_test/vc_test/cvi_jpg_codec self_test/fast_image_ut/fast_image_ut self_test/audio/aud_auto_test_sample/cvi_auto_play self_test/audio/aud_auto_test_sample/cvi_auto_record @@ -92,8 +61,6 @@ self_test/audio/audio_pcm/sample_audio_internal self_test/audio/audio_resample/sample_audio_resample self_test/audio/audio_transcode/sample_audio_transcode - - modules/venc/vc/jpeg/driver/bm_jpg_test modules/venc/vc/jpeg/driver/bmjpuapi/bmjpegdec modules/venc/vc/jpeg/driver/bmjpuapi/bmjpegenc @@ -108,4 +75,4 @@ modules/venc/vc/jpeg/driver/include/version.h .vscode/settings.json modules/isp -ko + diff --git a/middleware/v2/component/isp/sensor.mk b/middleware/v2/component/isp/sensor.mk index bb49c9149..214edace4 100644 --- a/middleware/v2/component/isp/sensor.mk +++ b/middleware/v2/component/isp/sensor.mk @@ -54,6 +54,7 @@ sensor-$(CONFIG_SENSOR_TECHPOINT_TP2825) += techpoint_tp2825 else ifeq ($(CHIP_ARCH), $(filter $(CHIP_ARCH), CV180X CV181X CV182X)) sensor-$(CONFIG_SENSOR_BRIGATES_BG0808) += brigates_bg0808 sensor-$(CONFIG_SENSOR_GCORE_GC02M1) += gcore_gc02m1 +sensor-$(CONFIG_SENSOR_GCORE_GC0312) += gcore_gc0312 sensor-$(CONFIG_SENSOR_GCORE_GC0329) += gcore_gc0329 sensor-$(CONFIG_SENSOR_GCORE_GC1054) += gcore_gc1054 sensor-$(CONFIG_SENSOR_GCORE_GC2053) += gcore_gc2053 @@ -89,14 +90,19 @@ sensor-$(CONFIG_SENSOR_SMS_SC531AI_2L) += sms_sc531ai_2L sensor-$(CONFIG_SENSOR_SMS_SC3332) += sms_sc3332 sensor-$(CONFIG_SENSOR_SMS_SC3335) += sms_sc3335 sensor-$(CONFIG_SENSOR_SMS_SC3336) += sms_sc3336 +sensor-$(CONFIG_SENSOR_SMS_SC2331_1L) += sms_sc2331_1L sensor-$(CONFIG_SENSOR_SMS_SC2335) += sms_sc2335 sensor-$(CONFIG_SENSOR_SMS_SC2336) += sms_sc2336 +sensor-$(CONFIG_SENSOR_SMS_SC2336P) += sms_sc2336p sensor-$(CONFIG_SENSOR_SMS_SC4336) += sms_sc4336 +sensor-$(CONFIG_SENSOR_SMS_SC4336P) += sms_sc4336p +sensor-$(CONFIG_SENSOR_SMS_SC5336_2L) += sms_sc5336_2L sensor-$(CONFIG_SENSOR_SOI_F23) += soi_f23 sensor-$(CONFIG_SENSOR_SOI_F35) += soi_f35 sensor-$(CONFIG_SENSOR_SOI_F37P) += soi_f37p sensor-$(CONFIG_SENSOR_SOI_K06) += soi_k06 sensor-$(CONFIG_SENSOR_SOI_Q03) += soi_q03 +sensor-$(CONFIG_SENSOR_SOI_Q03P) += soi_q03p sensor-$(CONFIG_SENSOR_SONY_IMX307) += sony_imx307 sensor-$(CONFIG_SENSOR_SONY_IMX307_SLAVE) += sony_imx307_slave sensor-$(CONFIG_SENSOR_SONY_IMX307_2L) += sony_imx307_2L @@ -108,6 +114,7 @@ sensor-$(CONFIG_SENSOR_SONY_IMX327_SUBLVDS) += sony_imx327_sublvds sensor-$(CONFIG_SENSOR_SONY_IMX335) += sony_imx335 sensor-$(CONFIG_SENSOR_TECHPOINT_TP2825) += techpoint_tp2825 sensor-$(CONFIG_SENSOR_TECHPOINT_TP2863) += techpoint_tp2863 +sensor-$(CONFIG_SENSOR_LONTIUM_LT6911) += lontium_lt6911 else $(error not supported chip arch cv180x/cv181x/cv182x/cv183x) endif diff --git a/middleware/v2/component/isp/sensor/cv180x/Makefile b/middleware/v2/component/isp/sensor/cv180x/Makefile index 815ace8d6..6706e8cfc 100644 --- a/middleware/v2/component/isp/sensor/cv180x/Makefile +++ b/middleware/v2/component/isp/sensor/cv180x/Makefile @@ -28,6 +28,8 @@ brigates_bg0808: gcore_gc02m1: $(call MAKE_SENSOR, ${@}) +gcore_gc0312: + $(call MAKE_SENSOR, ${@}) gcore_gc0329: $(call MAKE_SENSOR, ${@}) @@ -134,15 +136,27 @@ sms_sc3335: sms_sc3336: $(call MAKE_SENSOR, ${@}) +sms_sc2331_1L: + $(call MAKE_SENSOR, ${@}) + sms_sc2335: $(call MAKE_SENSOR, ${@}) sms_sc2336: $(call MAKE_SENSOR, ${@}) +sms_sc2336p: + $(call MAKE_SENSOR, ${@}) + sms_sc4336: $(call MAKE_SENSOR, ${@}) +sms_sc4336p: + $(call MAKE_SENSOR, ${@}) + +sms_sc5336_2L: + $(call MAKE_SENSOR, ${@}) + soi_f23: $(call MAKE_SENSOR, ${@}) @@ -155,6 +169,9 @@ soi_f37p: soi_q03: $(call MAKE_SENSOR, ${@}) +soi_q03p: + $(call MAKE_SENSOR, ${@}) + soi_k06: $(call MAKE_SENSOR, ${@}) @@ -191,6 +208,9 @@ techpoint_tp2825: techpoint_tp2863: $(call MAKE_SENSOR, ${@}) +lontium_lt6911: + $(call MAKE_SENSOR, ${@}) + all_sensor: @$(MAKE) -f Makefile_full || exit 1; diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/Makefile b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/Makefile new file mode 100644 index 000000000..4a0e22f55 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_gc0312.a +TARGET_SO = $(MW_LIB)/libsns_gc0312.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos.c b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos.c new file mode 100644 index 000000000..0f5e654f8 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos.c @@ -0,0 +1,303 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "gc0312_cmos_ex.h" +#include "gc0312_cmos_param.h" + +#define GC0312_ID 0xb310 +#define GC0312_I2C_ADDR_1 0x21 +#define GC0312_I2C_ADDR_IS_VALID(addr) ((addr) == GC0312_I2C_ADDR_1) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastGc0312[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define GC0312_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc0312[dev]) +#define GC0312_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc0312[dev] = pstCtx) +#define GC0312_SENSOR_RESET_CTX(dev) (g_pastGc0312[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunGc0312_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +#define GC0312_RES_IS_480P(w, h) ((w) == 640 && (h) == 480) + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const GC0312_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astGc0312_mode; + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstCfg0 = &pstSnsState->astSyncInfo[0]; + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 20) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (GC0312_RES_IS_480P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) + u8SensorImageMode = GC0312_MODE_640X480P20; + else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps); + return CVI_FAILURE; + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = GC0312_MODE_640X480P20; + pstSnsState->enWDRMode = WDR_MODE_NONE; +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &gc0312_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astGc0312_mode.stImg.stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astGc0312_mode.stImg.stSnsSize.u32Height; + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc0312_rx_attr; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = gc0312_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = gc0312_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (GC0312_I2C_ADDR_IS_VALID(s32I2cAddr)) + gc0312_i2c_addr = s32I2cAddr; +} + +static CVI_S32 gc0312_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunGc0312_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + GC0312_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + GC0312_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + (void) pstAeLib; + (void) pstAwbLib; + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = GC0312_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + (void) pstAeLib; + (void) pstAwbLib; + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC0312_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return gc0312_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsGc0312_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = CVI_NULL, + .pfnRestart = CVI_NULL, + .pfnWriteReg = gc0312_write_register, + .pfnReadReg = gc0312_read_register, + .pfnSetBusInfo = gc0312_set_bus_info, + .pfnSetInit = CVI_NULL, + .pfnMirrorFlip = CVI_NULL, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = CVI_NULL, + .pfnSnsProbe = sensor_probe, +}; diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos_ex.h new file mode 100644 index 000000000..d06a6598f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos_ex.h @@ -0,0 +1,64 @@ +#ifndef __GC0312_CMOS_EX_H_ +#define __GC0312_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +typedef enum _GC0312_MODE_E { + GC0312_MODE_640X480P20 = 0, + GC0312_MODE_NUM +} GC0312_SLAVE_MODE_E; + +typedef struct _GC0312_MODE_S { + ISP_WDR_SIZE_S stImg; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp; + SNS_ATTR_LARGE_S stAgain; + SNS_ATTR_LARGE_S stDgain; + char name[64]; +} GC0312_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastGc0312[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunGc0312_BusInfo[]; +extern CVI_U8 gc0312_i2c_addr; +extern const CVI_U32 gc0312_addr_byte; +extern const CVI_U32 gc0312_data_byte; +extern void gc0312_init(VI_PIPE ViPipe); +extern void gc0312_exit(VI_PIPE ViPipe); +extern void gc0312_standby(VI_PIPE ViPipe); +extern void gc0312_restart(VI_PIPE ViPipe); +extern int gc0312_write_register(VI_PIPE ViPipe, int addr, int data); +extern int gc0312_read_register(VI_PIPE ViPipe, int addr); +extern void gc0312_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int gc0312_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC0312_CMOS_EX_H_ */ + diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos_param.h new file mode 100644 index 000000000..cfc16cc3b --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_cmos_param.h @@ -0,0 +1,71 @@ +#ifndef __GC0312_CMOS_PARAM_H_ +#define __GC0312_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc0312_cmos_ex.h" + +static const GC0312_MODE_S g_astGc0312_mode = { + .name = "640X480P20", + .stImg = { + .stSnsSize = { + .u32Width = 640, + .u32Height = 480, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 640, + .u32Height = 480, + }, + .stMaxSize = { + .u32Width = 640, + .u32Height = 480, + }, + }, +}; + +struct combo_dev_attr_s gc0312_rx_attr = { + .input_mode = INPUT_MODE_BT601, + .mac_clk = RX_MAC_CLK_200M, + .ttl_attr = { + .vi = TTL_VI_SRC_VI0, + .ttl_fmt = TTL_VSDE_11B, + .raw_data_type = RAW_DATA_8BIT, + .func = { + 11, -1, -1, 12, + 1, 3, 4, 2, + 0, 5, 6, 7, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, + .mclk = { + .cam = 1, + .freq = CAMPLL_FREQ_24M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC0312_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_sensor_ctl.c new file mode 100644 index 000000000..72405a1e9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0312/gc0312_sensor_ctl.c @@ -0,0 +1,555 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc0312_cmos_ex.h" + +static void gc0312_linear_480p20_init(VI_PIPE ViPipe); + +CVI_U8 gc0312_i2c_addr = 0x21; +const CVI_U32 gc0312_addr_byte = 1; +const CVI_U32 gc0312_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int gc0312_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunGc0312_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc0312_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int gc0312_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int gc0312_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (gc0312_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, gc0312_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, gc0312_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (gc0312_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + + +int gc0312_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (gc0312_addr_byte == 1) { + buf[idx] = addr & 0xff; + idx++; + } + if (gc0312_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, gc0312_addr_byte + gc0312_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } +// syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +#define GC0312_CHIP_ID 0xb310 +#define GC0312_CHIP_ID_ADDR_H 0xf0 +#define GC0312_CHIP_ID_ADDR_L 0xf1 + +int gc0312_probe(VI_PIPE ViPipe) +{ + int nVal; + int nVal2; + + usleep(50); + if (gc0312_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = gc0312_read_register(ViPipe, GC0312_CHIP_ID_ADDR_H); + nVal2 = gc0312_read_register(ViPipe, GC0312_CHIP_ID_ADDR_L); + if (nVal < 0 || nVal2 < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + + if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC0312_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + printf("%d\n", ViPipe); + return CVI_SUCCESS; +} + +void gc0312_init(VI_PIPE ViPipe) +{ + gc0312_i2c_init(ViPipe); + + gc0312_linear_480p20_init(ViPipe); + + g_pastGc0312[ViPipe]->bInit = CVI_TRUE; +} + +void gc0312_exit(VI_PIPE ViPipe) +{ + gc0312_i2c_exit(ViPipe); +} + +static void gc0312_linear_480p20_init(VI_PIPE ViPipe) +{ + gc0312_write_register(ViPipe, 0xfe, 0xf0); + gc0312_write_register(ViPipe, 0xfe, 0xf0); + gc0312_write_register(ViPipe, 0xfe, 0x00); + gc0312_write_register(ViPipe, 0xfc, 0x0e); + gc0312_write_register(ViPipe, 0xfc, 0x0e); + gc0312_write_register(ViPipe, 0xf2, 0x07); + gc0312_write_register(ViPipe, 0xf3, 0x00);// output_disable + gc0312_write_register(ViPipe, 0xf7, 0x1b); + gc0312_write_register(ViPipe, 0xf8, 0x04); + gc0312_write_register(ViPipe, 0xf9, 0x0e); + gc0312_write_register(ViPipe, 0xfa, 0x11); + + ///////////////////////////////////////////////// + ///////////////// CISCTL reg ///////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x00, 0x2f); + gc0312_write_register(ViPipe, 0x01, 0x0f); + gc0312_write_register(ViPipe, 0x02, 0x04); + gc0312_write_register(ViPipe, 0x03, 0x03); + gc0312_write_register(ViPipe, 0x04, 0x50); + gc0312_write_register(ViPipe, 0x09, 0x00); + gc0312_write_register(ViPipe, 0x0a, 0x00); + gc0312_write_register(ViPipe, 0x0b, 0x00); + gc0312_write_register(ViPipe, 0x0c, 0x04); + gc0312_write_register(ViPipe, 0x0d, 0x01); + gc0312_write_register(ViPipe, 0x0e, 0xe8); + gc0312_write_register(ViPipe, 0x0f, 0x02); + gc0312_write_register(ViPipe, 0x10, 0x88); + gc0312_write_register(ViPipe, 0x16, 0x00); + gc0312_write_register(ViPipe, 0x17, 0x14); + gc0312_write_register(ViPipe, 0x18, 0x1a); + gc0312_write_register(ViPipe, 0x19, 0x14); + gc0312_write_register(ViPipe, 0x1b, 0x48); + gc0312_write_register(ViPipe, 0x1c, 0x6c);//1c travis 20140929 + gc0312_write_register(ViPipe, 0x1e, 0x6b); + gc0312_write_register(ViPipe, 0x1f, 0x28); + gc0312_write_register(ViPipe, 0x20, 0x8b);//89 travis 20140801 + gc0312_write_register(ViPipe, 0x21, 0x49); + gc0312_write_register(ViPipe, 0x22, 0xd0);//b0 travis 20140929 + gc0312_write_register(ViPipe, 0x23, 0x04); + gc0312_write_register(ViPipe, 0x24, 0x16); + gc0312_write_register(ViPipe, 0x34, 0x20); + + ///////////////////////////////////////////////// + //////////////////// BLK //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x26, 0x23); + gc0312_write_register(ViPipe, 0x28, 0xff); + gc0312_write_register(ViPipe, 0x29, 0x00); + gc0312_write_register(ViPipe, 0x32, 0x04);//00 travis 20140929 + gc0312_write_register(ViPipe, 0x33, 0x10); + gc0312_write_register(ViPipe, 0x37, 0x20); + gc0312_write_register(ViPipe, 0x38, 0x10); + gc0312_write_register(ViPipe, 0x47, 0x80); + gc0312_write_register(ViPipe, 0x4e, 0x66); + gc0312_write_register(ViPipe, 0xa8, 0x02); + gc0312_write_register(ViPipe, 0xa9, 0x80); + + ///////////////////////////////////////////////// + ////////////////// ISP reg /////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x40, 0xff); + gc0312_write_register(ViPipe, 0x41, 0x21); + gc0312_write_register(ViPipe, 0x42, 0xcf); + gc0312_write_register(ViPipe, 0x44, 0x02); + gc0312_write_register(ViPipe, 0x45, 0xa8); + gc0312_write_register(ViPipe, 0x46, 0x02); + gc0312_write_register(ViPipe, 0x4a, 0x11); + gc0312_write_register(ViPipe, 0x4b, 0x01); + gc0312_write_register(ViPipe, 0x4c, 0x20); + gc0312_write_register(ViPipe, 0x4d, 0x05); + gc0312_write_register(ViPipe, 0x4f, 0x01); + gc0312_write_register(ViPipe, 0x50, 0x01); + gc0312_write_register(ViPipe, 0x55, 0x01); + gc0312_write_register(ViPipe, 0x56, 0xe0); + gc0312_write_register(ViPipe, 0x57, 0x02); + gc0312_write_register(ViPipe, 0x58, 0x80); + + ///////////////////////////////////////////////// + /////////////////// GAIN //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x70, 0x70); + gc0312_write_register(ViPipe, 0x5a, 0x84); + gc0312_write_register(ViPipe, 0x5b, 0xc9); + gc0312_write_register(ViPipe, 0x5c, 0xed); + gc0312_write_register(ViPipe, 0x77, 0x74); + gc0312_write_register(ViPipe, 0x78, 0x40); + gc0312_write_register(ViPipe, 0x79, 0x5f); + + ///////////////////////////////////////////////// + /////////////////// DNDD ///////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x82, 0x14); + gc0312_write_register(ViPipe, 0x83, 0x0b); + gc0312_write_register(ViPipe, 0x89, 0xf0); + + ///////////////////////////////////////////////// + ////////////////// EEINTP //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x8f, 0xaa); + gc0312_write_register(ViPipe, 0x90, 0x8c); + gc0312_write_register(ViPipe, 0x91, 0x90); + gc0312_write_register(ViPipe, 0x92, 0x03); + gc0312_write_register(ViPipe, 0x93, 0x03); + gc0312_write_register(ViPipe, 0x94, 0x05); + gc0312_write_register(ViPipe, 0x95, 0x65); + gc0312_write_register(ViPipe, 0x96, 0xf0); + + ///////////////////////////////////////////////// + ///////////////////// ASDE //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x00); + + gc0312_write_register(ViPipe, 0x9a, 0x20); + gc0312_write_register(ViPipe, 0x9b, 0x80); + gc0312_write_register(ViPipe, 0x9c, 0x40); + gc0312_write_register(ViPipe, 0x9d, 0x80); + + gc0312_write_register(ViPipe, 0xa1, 0x30); + gc0312_write_register(ViPipe, 0xa2, 0x32); + gc0312_write_register(ViPipe, 0xa4, 0x80);//30 travis 20140929 + gc0312_write_register(ViPipe, 0xa5, 0x28);//30 travis 20140929 + gc0312_write_register(ViPipe, 0xaa, 0x30);//10 travis 20140929 + gc0312_write_register(ViPipe, 0xac, 0x22); + + ///////////////////////////////////////////////// + /////////////////// GAMMA /////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x00);//default + gc0312_write_register(ViPipe, 0xbf, 0x08); + gc0312_write_register(ViPipe, 0xc0, 0x16); + gc0312_write_register(ViPipe, 0xc1, 0x28); + gc0312_write_register(ViPipe, 0xc2, 0x41); + gc0312_write_register(ViPipe, 0xc3, 0x5a); + gc0312_write_register(ViPipe, 0xc4, 0x6c); + gc0312_write_register(ViPipe, 0xc5, 0x7a); + gc0312_write_register(ViPipe, 0xc6, 0x96); + gc0312_write_register(ViPipe, 0xc7, 0xac); + gc0312_write_register(ViPipe, 0xc8, 0xbc); + gc0312_write_register(ViPipe, 0xc9, 0xc9); + gc0312_write_register(ViPipe, 0xca, 0xd3); + gc0312_write_register(ViPipe, 0xcb, 0xdd); + gc0312_write_register(ViPipe, 0xcc, 0xe5); + gc0312_write_register(ViPipe, 0xcd, 0xf1); + gc0312_write_register(ViPipe, 0xce, 0xfa); + gc0312_write_register(ViPipe, 0xcf, 0xff); + ///////////////////////////////////////////////// + /////////////////// YCP ////////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xd0, 0x40); + gc0312_write_register(ViPipe, 0xd1, 0x34); + gc0312_write_register(ViPipe, 0xd2, 0x34); + gc0312_write_register(ViPipe, 0xd3, 0x40); + gc0312_write_register(ViPipe, 0xd6, 0xf2); + gc0312_write_register(ViPipe, 0xd7, 0x1b); + gc0312_write_register(ViPipe, 0xd8, 0x18); + gc0312_write_register(ViPipe, 0xdd, 0x03); + + ///////////////////////////////////////////////// + //////////////////// AEC //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x01); + gc0312_write_register(ViPipe, 0x05, 0x30); + gc0312_write_register(ViPipe, 0x06, 0x75); + gc0312_write_register(ViPipe, 0x07, 0x40); + gc0312_write_register(ViPipe, 0x08, 0xb0); + gc0312_write_register(ViPipe, 0x0a, 0xc5); + gc0312_write_register(ViPipe, 0x0b, 0x11); + gc0312_write_register(ViPipe, 0x0c, 0x00); + gc0312_write_register(ViPipe, 0x12, 0x52); + gc0312_write_register(ViPipe, 0x13, 0x38); + gc0312_write_register(ViPipe, 0x18, 0x95); + gc0312_write_register(ViPipe, 0x19, 0x96); + gc0312_write_register(ViPipe, 0x1f, 0x20); + gc0312_write_register(ViPipe, 0x20, 0xc0); + gc0312_write_register(ViPipe, 0x3e, 0x40); + gc0312_write_register(ViPipe, 0x3f, 0x57); + gc0312_write_register(ViPipe, 0x40, 0x7d); + gc0312_write_register(ViPipe, 0x03, 0x60); + gc0312_write_register(ViPipe, 0x44, 0x02); + + ///////////////////////////////////////////////// + //////////////////// AWB //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x01); + gc0312_write_register(ViPipe, 0x1c, 0x91); + gc0312_write_register(ViPipe, 0x21, 0x15); + gc0312_write_register(ViPipe, 0x50, 0x80); + gc0312_write_register(ViPipe, 0x56, 0x04); + gc0312_write_register(ViPipe, 0x59, 0x08); + gc0312_write_register(ViPipe, 0x5b, 0x02); + gc0312_write_register(ViPipe, 0x61, 0x8d); + gc0312_write_register(ViPipe, 0x62, 0xa7); + gc0312_write_register(ViPipe, 0x63, 0xd0); + gc0312_write_register(ViPipe, 0x65, 0x06); + gc0312_write_register(ViPipe, 0x66, 0x06); + gc0312_write_register(ViPipe, 0x67, 0x84); + gc0312_write_register(ViPipe, 0x69, 0x08); + gc0312_write_register(ViPipe, 0x6a, 0x25); + gc0312_write_register(ViPipe, 0x6b, 0x01); + gc0312_write_register(ViPipe, 0x6c, 0x00); + gc0312_write_register(ViPipe, 0x6d, 0x02); + gc0312_write_register(ViPipe, 0x6e, 0xf0); + gc0312_write_register(ViPipe, 0x6f, 0x80); + gc0312_write_register(ViPipe, 0x76, 0x80); + gc0312_write_register(ViPipe, 0x78, 0xaf); + gc0312_write_register(ViPipe, 0x79, 0x75); + gc0312_write_register(ViPipe, 0x7a, 0x40); + gc0312_write_register(ViPipe, 0x7b, 0x50); + gc0312_write_register(ViPipe, 0x7c, 0x0c); + + + gc0312_write_register(ViPipe, 0x90, 0xc9);//stable AWB + gc0312_write_register(ViPipe, 0x91, 0xbe); + gc0312_write_register(ViPipe, 0x92, 0xe2); + gc0312_write_register(ViPipe, 0x93, 0xc9); + gc0312_write_register(ViPipe, 0x95, 0x1b); + gc0312_write_register(ViPipe, 0x96, 0xe2); + gc0312_write_register(ViPipe, 0x97, 0x49); + gc0312_write_register(ViPipe, 0x98, 0x1b); + gc0312_write_register(ViPipe, 0x9a, 0x49); + gc0312_write_register(ViPipe, 0x9b, 0x1b); + gc0312_write_register(ViPipe, 0x9c, 0xc3); + gc0312_write_register(ViPipe, 0x9d, 0x49); + gc0312_write_register(ViPipe, 0x9f, 0xc7); + gc0312_write_register(ViPipe, 0xa0, 0xc8); + gc0312_write_register(ViPipe, 0xa1, 0x00); + gc0312_write_register(ViPipe, 0xa2, 0x00); + gc0312_write_register(ViPipe, 0x86, 0x00); + gc0312_write_register(ViPipe, 0x87, 0x00); + gc0312_write_register(ViPipe, 0x88, 0x00); + gc0312_write_register(ViPipe, 0x89, 0x00); + gc0312_write_register(ViPipe, 0xa4, 0xb9); + gc0312_write_register(ViPipe, 0xa5, 0xa0); + gc0312_write_register(ViPipe, 0xa6, 0xba); + gc0312_write_register(ViPipe, 0xa7, 0x92); + gc0312_write_register(ViPipe, 0xa9, 0xba); + gc0312_write_register(ViPipe, 0xaa, 0x80); + gc0312_write_register(ViPipe, 0xab, 0x9d); + gc0312_write_register(ViPipe, 0xac, 0x7f); + gc0312_write_register(ViPipe, 0xae, 0xbb); + gc0312_write_register(ViPipe, 0xaf, 0x9d); + gc0312_write_register(ViPipe, 0xb0, 0xc8); + gc0312_write_register(ViPipe, 0xb1, 0x97); + gc0312_write_register(ViPipe, 0xb3, 0xb7); + gc0312_write_register(ViPipe, 0xb4, 0x7f); + gc0312_write_register(ViPipe, 0xb5, 0x00); + gc0312_write_register(ViPipe, 0xb6, 0x00); + gc0312_write_register(ViPipe, 0x8b, 0x00); + gc0312_write_register(ViPipe, 0x8c, 0x00); + gc0312_write_register(ViPipe, 0x8d, 0x00); + gc0312_write_register(ViPipe, 0x8e, 0x00); + gc0312_write_register(ViPipe, 0x94, 0x55); + gc0312_write_register(ViPipe, 0x99, 0xa6); + gc0312_write_register(ViPipe, 0x9e, 0xaa); + gc0312_write_register(ViPipe, 0xa3, 0x0a); + gc0312_write_register(ViPipe, 0x8a, 0x00); + gc0312_write_register(ViPipe, 0xa8, 0x55); + gc0312_write_register(ViPipe, 0xad, 0x55); + gc0312_write_register(ViPipe, 0xb2, 0x55); + gc0312_write_register(ViPipe, 0xb7, 0x05); + gc0312_write_register(ViPipe, 0x8f, 0x00); + gc0312_write_register(ViPipe, 0xb8, 0xcb); + gc0312_write_register(ViPipe, 0xb9, 0x9b); + ///////////////////////////////////////////////// + //////////////////// CC //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x01); + + gc0312_write_register(ViPipe, 0xd0, 0x38);//skin red + gc0312_write_register(ViPipe, 0xd1, 0x00); + gc0312_write_register(ViPipe, 0xd2, 0x02); + gc0312_write_register(ViPipe, 0xd3, 0x04); + gc0312_write_register(ViPipe, 0xd4, 0x38); + gc0312_write_register(ViPipe, 0xd5, 0x12); + gc0312_write_register(ViPipe, 0xd6, 0x30); + gc0312_write_register(ViPipe, 0xd7, 0x00); + gc0312_write_register(ViPipe, 0xd8, 0x0a); + gc0312_write_register(ViPipe, 0xd9, 0x16); + gc0312_write_register(ViPipe, 0xda, 0x39); + gc0312_write_register(ViPipe, 0xdb, 0xf8); + + ///////////////////////////////////////////////// + //////////////////// LSC //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x01); + gc0312_write_register(ViPipe, 0xc1, 0x3c); + gc0312_write_register(ViPipe, 0xc2, 0x50); + gc0312_write_register(ViPipe, 0xc3, 0x00); + gc0312_write_register(ViPipe, 0xc4, 0x40); + gc0312_write_register(ViPipe, 0xc5, 0x30); + gc0312_write_register(ViPipe, 0xc6, 0x30); + gc0312_write_register(ViPipe, 0xc7, 0x10); + gc0312_write_register(ViPipe, 0xc8, 0x00); + gc0312_write_register(ViPipe, 0xc9, 0x00); + gc0312_write_register(ViPipe, 0xdc, 0x20); + gc0312_write_register(ViPipe, 0xdd, 0x10); + gc0312_write_register(ViPipe, 0xdf, 0x00); + gc0312_write_register(ViPipe, 0xde, 0x00); + + ///////////////////////////////////////////////// + /////////////////// Histogram ///////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x01, 0x10); + gc0312_write_register(ViPipe, 0x0b, 0x31); + gc0312_write_register(ViPipe, 0x0e, 0x50); + gc0312_write_register(ViPipe, 0x0f, 0x0f); + gc0312_write_register(ViPipe, 0x10, 0x6e); + gc0312_write_register(ViPipe, 0x12, 0xa0); + gc0312_write_register(ViPipe, 0x15, 0x60); + gc0312_write_register(ViPipe, 0x16, 0x60); + gc0312_write_register(ViPipe, 0x17, 0xe0); + + ///////////////////////////////////////////////// + ////////////// Measure Window /////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xcc, 0x0c); + gc0312_write_register(ViPipe, 0xcd, 0x10); + gc0312_write_register(ViPipe, 0xce, 0xa0); + gc0312_write_register(ViPipe, 0xcf, 0xe6); + + ///////////////////////////////////////////////// + ///////////////// dark sun ////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x45, 0xf7); + gc0312_write_register(ViPipe, 0x46, 0xff); + gc0312_write_register(ViPipe, 0x47, 0x15); + gc0312_write_register(ViPipe, 0x48, 0x03); + gc0312_write_register(ViPipe, 0x4f, 0x60); + + //////////////////banding////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x00); + gc0312_write_register(ViPipe, 0x05, 0x02); + gc0312_write_register(ViPipe, 0x06, 0xd1); //HB + gc0312_write_register(ViPipe, 0x07, 0x00); + gc0312_write_register(ViPipe, 0x08, 0x22); //VB + + gc0312_write_register(ViPipe, 0xfe, 0x01); + gc0312_write_register(ViPipe, 0x25, 0x00); //anti-flicker step [11:8] + gc0312_write_register(ViPipe, 0x26, 0x6a); //anti-flicker step [7:0] + + gc0312_write_register(ViPipe, 0x27, 0x02); //exp level 0 20fps + gc0312_write_register(ViPipe, 0x28, 0x12); + gc0312_write_register(ViPipe, 0x29, 0x03); //exp level 1 12.50fps + gc0312_write_register(ViPipe, 0x2a, 0x50); + gc0312_write_register(ViPipe, 0x2b, 0x05); //7.14fps + gc0312_write_register(ViPipe, 0x2c, 0xcc); + gc0312_write_register(ViPipe, 0x2d, 0x07); //exp level 3 5.55fps + gc0312_write_register(ViPipe, 0x2e, 0x74); + gc0312_write_register(ViPipe, 0x3c, 0x20); + gc0312_write_register(ViPipe, 0xfe, 0x00); + + ///////////////////////////////////////////////// + ///////////////////// DVP //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x03); + gc0312_write_register(ViPipe, 0x01, 0x00); + gc0312_write_register(ViPipe, 0x02, 0x00); + gc0312_write_register(ViPipe, 0x10, 0x00); + gc0312_write_register(ViPipe, 0x15, 0x00); + gc0312_write_register(ViPipe, 0xfe, 0x00); + ///////////////////OUTPUT////////////////////// + gc0312_write_register(ViPipe, 0xf3, 0xff);// output_enable + + + delay_ms(50); + + printf("ViPipe:%d,===GC0312 480P 20fps YUV Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/Makefile b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/Makefile new file mode 100644 index 000000000..8590b964e --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_lt6911.a +TARGET_SO = $(MW_LIB)/libsns_lt6911.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos.c b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos.c new file mode 100644 index 000000000..cceeeb08f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos.c @@ -0,0 +1,423 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "lt6911_cmos_ex.h" +#include "lt6911_cmos_param.h" + +#define LT6911_ID 6911 + +#define INPUT_WIDTH (1920) +#define INPUT_HEIGHT (1080) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastLt6911[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define LT6911_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastLt6911[dev]) +#define LT6911_SENSOR_SET_CTX(dev, pstCtx) (g_pastLt6911[dev] = pstCtx) +#define LT6911_SENSOR_RESET_CTX(dev) (g_pastLt6911[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunLt6911_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****lt6911 Lines Range*****/ + + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + (void) ViPipe; + (void) pstAeSnsDft; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + (void) ViPipe; + (void) pu32AgainLin; + (void) pu32AgainDb; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + (void) ViPipe; + (void) pu32DgainLin; + (void) pu32DgainDb; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + (void) ViPipe; + (void) pu32Again; + (void) pu32Dgain; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + + return CVI_SUCCESS; +} + + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const LT6911_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astLt6911_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "not support wdr mode\n"); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + + //pstSnsState->bSyncInit, pstSnsRegsInfo->bConfig); + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunLt6911_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + pstSnsState->bSyncInit = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = LT6911_MODE_NORMAL; + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + (void) ViPipe; + + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->u8ImgMode = LT6911_MODE_NORMAL; +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, <6911_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astLt6911_mode[0].astImg[pstSnsState->u8ImgMode].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astLt6911_mode[0].astImg[pstSnsState->u8ImgMode].stSnsSize.u32Height; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + (void) ViPipe; + (void) u8Mode; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = <6911_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = lt6911_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = lt6911_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 lt6911_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunLt6911_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_param_fix(CVI_VOID) +{ + LT6911_MODE_S *pstMode = &g_astLt6911_mode[LT6911_MODE_NORMAL]; + + pstMode->astImg[0].stSnsSize.u32Width = INPUT_WIDTH; + pstMode->astImg[0].stSnsSize.u32Height = INPUT_HEIGHT; + pstMode->astImg[0].stWndRect.u32Width = INPUT_WIDTH; + pstMode->astImg[0].stWndRect.u32Height = INPUT_HEIGHT; + pstMode->astImg[0].stMaxSize.u32Width = INPUT_WIDTH; + pstMode->astImg[0].stMaxSize.u32Height = INPUT_HEIGHT; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + LT6911_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + LT6911_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + sensor_param_fix(); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = LT6911_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, LT6911_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, LT6911_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, LT6911_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + (void) ViPipe; + (void) pstInitAttr; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return lt6911_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsLT6911_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = CVI_NULL, + .pfnRestart = CVI_NULL, + .pfnMirrorFlip = CVI_NULL, + .pfnWriteReg = lt6911_write, + .pfnReadReg = lt6911_read, + .pfnSetBusInfo = lt6911_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sensor_probe, +}; \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos_ex.h new file mode 100644 index 000000000..b3863cadc --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos_ex.h @@ -0,0 +1,63 @@ +#ifndef __LT6911_CMOS_EX_H_ +#define __LT6911_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +#ifndef UNUSED +#define UNUSED(x) ((void)(x)) +#endif + + +enum lt6911_linear_regs_e { + LINEAR_REGS_NUM +}; + + +typedef enum _LT6911_MODE_E { + LT6911_MODE_NONE, + LT6911_MODE_NORMAL, + LT6911_MODE_NUM +} LT6911_MODE_E; + + +typedef struct _LT6911_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + char name[64]; +} LT6911_MODE_S; + + +extern CVI_U8 lt6911_i2c_addr; +extern const CVI_U32 lt6911_addr_byte; +extern const CVI_U32 lt6911_data_byte; +extern void lt6911_init(VI_PIPE ViPipe); +extern void lt6911_exit(VI_PIPE ViPipe); +extern void lt6911_standby(VI_PIPE ViPipe); +extern void lt6911_restart(VI_PIPE ViPipe); +extern int lt6911_write(VI_PIPE ViPipe, int addr, int data); +extern int lt6911_read(VI_PIPE ViPipe, int addr); +extern void lt6911_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int lt6911_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __LT6911_CMOS_EX_H_ */ \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos_param.h new file mode 100644 index 000000000..46ccbdd7d --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_cmos_param.h @@ -0,0 +1,75 @@ +#ifndef __LT6911_CMOS_PARAM_H_ +#define __LT6911_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "lt6911_cmos_ex.h" + +// not real time resolution +#define WIDTH 3840//3840 1920 +#define HEIGHT 2160//2160 1080 + +static LT6911_MODE_S g_astLt6911_mode[LT6911_MODE_NUM] = { + [LT6911_MODE_NORMAL] = { + .name = "lt6911", + .astImg[0] = { + .stSnsSize = { + .u32Width = WIDTH, + .u32Height = HEIGHT, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = WIDTH, + .u32Height = HEIGHT, + }, + .stMaxSize = { + .u32Width = WIDTH, + .u32Height = HEIGHT, + }, + }, + }, +}; + +struct combo_dev_attr_s lt6911_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_600M, + .mipi_attr = { + .raw_data_type = YUV422_8BIT, + .lane_id = {2, 0, 1, 3, 4}, //3, 0, 1, 2, 4 ; 1, 4, 3, 2, 0 2, 0, 1, 3, 4 3, 1, 2, 4, 0 + .pn_swap = {1, 1, 1, 1, 1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_NONE, + }, + .devno = 1, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __LT6911_CMOS_PARAM_H_ */ \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_sensor_ctl.c new file mode 100644 index 000000000..3df0b4eb6 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/lontium_lt6911/lt6911_sensor_ctl.c @@ -0,0 +1,215 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "lt6911_cmos_ex.h" + +#define LT6911_I2C_DEV 3 +#define LT6911_I2C_BANK_ADDR 0xff + +CVI_U8 lt6911_i2c_addr = 0x2b; +const CVI_U32 lt6911_addr_byte = 1; +const CVI_U32 lt6911_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int lt6911_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", LT6911_I2C_DEV); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", LT6911_I2C_DEV); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, lt6911_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int lt6911_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + + +int lt6911_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + char buf[8]; + int idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (lt6911_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, lt6911_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, lt6911_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (lt6911_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "vipipe:%d i2c r 0x%x = 0x%x\n", ViPipe, addr, data); + return data; +} + +int lt6911_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (lt6911_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + } + buf[idx] = addr & 0xff; + idx++; + + + if (lt6911_data_byte == 2) { + buf[idx] = (data >> 8) & 0xff; + idx++; + } + buf[idx] = data & 0xff; + idx++; + + ret = write(g_fd[ViPipe], buf, lt6911_addr_byte + lt6911_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + // ret = read(g_fd[ViPipe], buf, lt6911_addr_byte + lt6911_data_byte); + syslog(LOG_DEBUG, "ViPipe:%d i2c w 0x%x 0x%x\n", ViPipe, addr, data); + return CVI_SUCCESS; +} + +static int lt6911_i2c_read(VI_PIPE ViPipe, int RegAddr) +{ + uint8_t bank = RegAddr >> 8; + uint8_t addr = RegAddr & 0xff; + + lt6911_write_register(ViPipe, LT6911_I2C_BANK_ADDR, bank); + return lt6911_read_register(ViPipe, addr); +} + +static int lt6911_i2c_write(VI_PIPE ViPipe, int RegAddr, int data) +{ + uint8_t bank = RegAddr >> 8; + uint8_t addr = RegAddr & 0xff; + + lt6911_write_register(ViPipe, LT6911_I2C_BANK_ADDR, bank); + return lt6911_write_register(ViPipe, addr, data); +} + +int lt6911_read(VI_PIPE ViPipe, int addr) +{ + int data = 0; + + lt6911_i2c_write(ViPipe, 0x80ee, 0x01); + data = lt6911_i2c_read(ViPipe, addr); + lt6911_i2c_write(ViPipe, 0x80ee, 0x00); + return data; +} + +int lt6911_write(VI_PIPE ViPipe, int addr, int data) +{ + lt6911_i2c_write(ViPipe, 0x80ee, 0x01); + lt6911_i2c_write(ViPipe, addr, data); + lt6911_i2c_write(ViPipe, 0x80ee, 0x00); + return CVI_SUCCESS; +} + +#define LT6911_CHIP_ID_ADDR_H 0xa000 +#define LT6911_CHIP_ID_ADDR_L 0xa001 +#define LT6911_CHIP_ID 0x1605 + +int lt6911_probe(VI_PIPE ViPipe) +{ + int nVal; + int nVal2; + + usleep(50); + if (lt6911_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = lt6911_read(ViPipe, LT6911_CHIP_ID_ADDR_H); + nVal2 = lt6911_read(ViPipe, LT6911_CHIP_ID_ADDR_L); + if (nVal < 0 || nVal2 < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + printf("data:%02x %02x\n", nVal, nVal2); + if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != LT6911_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void lt6911_init(VI_PIPE ViPipe) +{ + lt6911_i2c_init(ViPipe); +} + +void lt6911_exit(VI_PIPE ViPipe) +{ + lt6911_i2c_exit(ViPipe); +} \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/Makefile b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/Makefile new file mode 100644 index 000000000..a91b7c4b1 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_sc2331_1L.a +TARGET_SO = $(MW_LIB)/libsns_sc2331_1L.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos.c b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos.c new file mode 100644 index 000000000..a15f1b242 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos.c @@ -0,0 +1,990 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" + +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "sc2331_1L_cmos_ex.h" +#include "sc2331_1L_cmos_param.h" + + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define SC2331_1L_ID 0xCB5C +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastSC2331_1L[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define SC2331_1L_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastSC2331_1L[dev]) +#define SC2331_1L_SENSOR_SET_CTX(dev, pstCtx) (g_pastSC2331_1L[dev] = pstCtx) +#define SC2331_1L_SENSOR_RESET_CTX(dev) (g_pastSC2331_1L[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunSC2331_1L_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 2}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16SC2331_1L_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16SC2331_1L_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +ISP_SNS_MIRRORFLIP_TYPE_E g_aeSc2331_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****SC2331_1L Lines Range*****/ +#define SC2331_1L_FULL_LINES_MAX (0x7FFF) + +/*****SC2331_1L Register Address*****/ +#define SC2331_1L_EXP_H_ADDR (0x3e00) +#define SC2331_1L_EXP_M_ADDR (0x3e01) +#define SC2331_1L_EXP_L_ADDR (0x3e02) + +#define SC2331_1L_AGAIN_H_ADDR (0x3e08) + +#define SC2331_1L_DGAIN_H_ADDR (0x3e06) +#define SC2331_1L_DGAIN_L_ADDR (0x3e07) + +#define SC2331_1L_VMAX_H_ADDR (0x320e) +#define SC2331_1L_VMAX_L_ADDR (0x320f) + +#define SC2331_1L_GAIN_DPC_ADDR (0x5799) +#define SC2331_1L_HOLD_ADDR (0x3812) + +#define SC2331_1L_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080) + +#define SC2331_1L_EXPACCURACY (0.5) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const SC2331_1L_MODE_S *pstMode; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astSC2331_1L_mode[pstSnsState->u8ImgMode]; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = SC2331_1L_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = SC2331_1L_EXPACCURACY; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u16Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u16Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u16Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u16Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max; + pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min; + pstAeSnsDft->u32MaxIntTimeTarget = pstAeSnsDft->u32MaxIntTime; + pstAeSnsDft->u32MinIntTimeTarget = pstAeSnsDft->u32MinIntTime; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case SC2331_1L_MODE_1920X1080P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > SC2331_1L_FULL_LINES_MAX) ? SC2331_1L_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_H_ADDR].u32Data = ((u32VMAX & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_L_ADDR].u32Data = (u32VMAX & 0xFF); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = 2 * pstSnsState->u32FLStd - 13; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32TmpIntTime, u32MinTime, u32MaxTime; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear exposure reg range: + * min : 3 + * max : 2 * vts - 10 + * step : 1 + */ + u32MinTime = 2; + u32MaxTime = 2 * pstSnsState->au32FL[0] - 13; + u32TmpIntTime = (u32IntTime[0] > u32MaxTime) ? u32MaxTime : u32IntTime[0]; + u32TmpIntTime = (u32TmpIntTime < u32MinTime) ? u32MinTime : u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_EXP_H_ADDR].u32Data = ((u32TmpIntTime & 0xF000) >> 12); + pstSnsRegsInfo->astI2cData[LINEAR_EXP_M_ADDR].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4); + pstSnsRegsInfo->astI2cData[LINEAR_EXP_L_ADDR].u32Data = ((u32TmpIntTime & 0x000F) << 4); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; + +} + +typedef struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +} gain_tbl_info_s; + +static struct gain_tbl_info_s AgainInfo[6] = { + { + .gainMax = 2031, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 4064, + .idxBase = 64, + .regGain = 0x08, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 8128, + .idxBase = 128, + .regGain = 0x09, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 16256, + .idxBase = 192, + .regGain = 0x0b, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 32512, + .idxBase = 256, + .regGain = 0x0f, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 32768, + .idxBase = 320, + .regGain = 0x1f, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, +}; +static CVI_U32 Again_table[321] = { + 1024, 1040, 1055, 1072, 1088, 1103, 1120, 1135, 1152, 1168, 1183, 1200, 1216, 1231, 1248, 1263, 1280, + 1296, 1311, 1328, 1344, 1359, 1376, 1391, 1408, 1424, 1439, 1456, 1472, 1487, 1504, 1519, 1536, 1552, + 1567, 1584, 1600, 1615, 1632, 1647, 1664, 1680, 1695, 1712, 1728, 1743, 1760, 1775, 1792, 1808, 1823, + 1840, 1856, 1871, 1888, 1903, 1920, 1936, 1951, 1968, 1984, 1999, 2016, 2031, 2048, 2079, 2112, 2144, + 2176, 2207, 2240, 2272, 2304, 2335, 2368, 2400, 2432, 2463, 2496, 2528, 2560, 2591, 2624, 2656, 2688, + 2719, 2752, 2784, 2816, 2847, 2880, 2912, 2944, 2975, 3008, 3040, 3072, 3103, 3136, 3168, 3200, 3231, + 3264, 3296, 3328, 3359, 3392, 3424, 3456, 3487, 3520, 3552, 3584, 3615, 3648, 3680, 3712, 3743, 3776, + 3808, 3840, 3871, 3904, 3936, 3968, 3999, 4032, 4064, 4096, 4160, 4224, 4288, 4352, 4416, 4480, 4544, + 4608, 4672, 4736, 4800, 4864, 4928, 4992, 5056, 5120, 5184, 5248, 5312, 5376, 5440, 5504, 5568, 5632, + 5696, 5760, 5824, 5888, 5952, 6016, 6080, 6144, 6208, 6272, 6336, 6400, 6464, 6528, 6592, 6656, 6720, + 6784, 6848, 6912, 6976, 7040, 7104, 7168, 7232, 7296, 7360, 7424, 7488, 7552, 7616, 7680, 7744, 7808, + 7872, 7936, 8000, 8064, 8128, 8192, 8320, 8448, 8576, 8704, 8832, 8960, 9088, 9216, 9344, 9472, 9600, + 9728, 9856, 9984, 10112, 10240, 10368, 10496, 10624, 10752, 10880, 11008, 11136, 11264, 11392, 11520, + 11648, 11776, 11904, 12032, 12160, 12288, 12416, 12544, 12672, 12800, 12928, 13056, 13184, 13312, 13440, + 13568, 13696, 13824, 13952, 14080, 14208, 14336, 14464, 14592, 14720, 14848, 14976, 15104, 15232, 15360, + 15488, 15616, 15744, 15872, 16000, 16128, 16256, 16384, 16640, 16896, 17152, 17408, 17664, 17920, 18176, + 18432, 18688, 18944, 19200, 19456, 19712, 19968, 20224, 20480, 20736, 20992, 21248, 21504, 21760, 22016, + 22272, 22528, 22784, 23040, 23296, 23552, 23808, 24064, 24320, 24576, 24832, 25088, 25344, 25600, 25856, + 26112, 26368, 26624, 26880, 27136, 27392, 27648, 27904, 28160, 28416, 28672, 28928, 29184, 29440, 29696, + 29952, 30208, 30464, 30720, 30976, 31232, 31488, 31744, 32000, 32256, 32512, 32768 +}; + +static struct gain_tbl_info_s DgainInfo[3] = { + { + .gainMax = 2031, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 4064, + .idxBase = 64, + .regGain = 0x01, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 4096, + .idxBase = 128, + .regGain = 0x03, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, +}; + +static CVI_U32 Dgain_table[129] = { + 1024, 1040, 1055, 1072, 1088, 1103, 1120, 1135, 1152, 1168, 1183, 1200, 1216, 1231, 1248, + 1263, 1280, 1296, 1311, 1328, 1344, 1359, 1376, 1391, 1408, 1424, 1439, 1456, 1472, 1487, + 1504, 1519, 1536, 1552, 1567, 1584, 1600, 1615, 1632, 1647, 1664, 1680, 1695, 1712, 1728, + 1743, 1760, 1775, 1792, 1808, 1823, 1840, 1856, 1871, 1888, 1903, 1920, 1936, 1951, 1968, + 1984, 1999, 2016, 2031, 2048, 2079, 2112, 2144, 2176, 2207, 2240, 2272, 2304, 2335, 2368, + 2400, 2432, 2463, 2496, 2528, 2560, 2591, 2624, 2656, 2688, 2719, 2752, 2784, 2816, 2847, + 2880, 2912, 2944, 2975, 3008, 3040, 3072, 3103, 3136, 3168, 3200, 3231, 3264, 3296, 3328, + 3359, 3392, 3424, 3456, 3487, 3520, 3552, 3584, 3615, 3648, 3680, 3712, 3743, 3776, 3808, + 3840, 3871, 3904, 3936, 3968, 3999, 4032, 4064, 4096 +}; + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + int i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + if (*pu32AgainLin >= Again_table[320]) { + *pu32AgainLin = Again_table[320]; + *pu32AgainDb = 320; + return CVI_SUCCESS; + } + + for (i = 1; i < 321; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + int i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[128]) { + *pu32DgainLin = Dgain_table[128]; + *pu32DgainDb = 128; + return CVI_SUCCESS; + } + + for (i = 1; i < 129; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + + /* find Again register setting. */ + tbl_num = sizeof(AgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &AgainInfo[i]; + + if (u32Again >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_H_ADDR].u32Data = (info->regGain & 0xFF); + u32Again = info->regGainFineBase + (u32Again - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_L_ADDR].u32Data = (u32Again & 0xFF); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H_ADDR].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L_ADDR].u32Data = (u32Dgain & 0xFF); + + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + //pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + //pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const SC2331_1L_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astSC2331_1L_mode[pstSnsState->u8ImgMode]; + + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = SC2331_1L_MODE_1920X1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunSC2331_1L_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = sc2331_1L_i2c_addr; + pstI2c_data[i].u32AddrByteNum = sc2331_1L_addr_byte; + pstI2c_data[i].u32DataByteNum = sc2331_1L_data_byte; + } + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + //Linear Mode Regs + pstI2c_data[LINEAR_EXP_H_ADDR].u32RegAddr = SC2331_1L_EXP_H_ADDR; + pstI2c_data[LINEAR_EXP_M_ADDR].u32RegAddr = SC2331_1L_EXP_M_ADDR; + pstI2c_data[LINEAR_EXP_L_ADDR].u32RegAddr = SC2331_1L_EXP_L_ADDR; + pstI2c_data[LINEAR_AGAIN_H_ADDR].u32RegAddr = SC2331_1L_AGAIN_H_ADDR; + pstI2c_data[LINEAR_AGAIN_L_ADDR].u32RegAddr = SC2331_1L_DGAIN_L_ADDR; + pstI2c_data[LINEAR_DGAIN_H_ADDR].u32RegAddr = SC2331_1L_DGAIN_H_ADDR; + pstI2c_data[LINEAR_DGAIN_L_ADDR].u32RegAddr = SC2331_1L_DGAIN_L_ADDR; + pstI2c_data[LINEAR_VMAX_H_ADDR].u32RegAddr = SC2331_1L_VMAX_H_ADDR; + pstI2c_data[LINEAR_VMAX_L_ADDR].u32RegAddr = SC2331_1L_VMAX_L_ADDR; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (SC2331_1L_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = SC2331_1L_MODE_1920X1080P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + if (pstSnsState->bInit == CVI_TRUE && g_aeSc2331_MirrorFip[ViPipe] != eSnsMirrorFlip) { + sc2331_1L_mirror_flip(ViPipe, eSnsMirrorFlip); + g_aeSc2331_MirrorFip[ViPipe] = eSnsMirrorFlip; + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const SC2331_1L_MODE_S *pstMode = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = SC2331_1L_MODE_1920X1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astSC2331_1L_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &sc2331_1L_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &sc2331_1L_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = sc2331_1L_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = sc2331_1L_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 sc2331_1L_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunSC2331_1L_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + SC2331_1L_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + SC2331_1L_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = SC2331_1L_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, SC2331_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, SC2331_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, SC2331_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16SC2331_1L_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16SC2331_1L_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsSC2331_1L_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = sc2331_1L_standby, + .pfnRestart = sc2331_1L_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = sc2331_1L_write_register, + .pfnReadReg = sc2331_1L_read_register, + .pfnSetBusInfo = sc2331_1L_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sc2331_1L_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos_ex.h new file mode 100644 index 000000000..9678e34ad --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos_ex.h @@ -0,0 +1,80 @@ +#ifndef __SC2331_1L_CMOS_EX_H_ +#define __SC2331_1L_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum sc2331_1L_linear_regs_e { + LINEAR_EXP_H_ADDR, + LINEAR_EXP_M_ADDR, + LINEAR_EXP_L_ADDR, + LINEAR_AGAIN_H_ADDR, + LINEAR_AGAIN_L_ADDR, + LINEAR_DGAIN_H_ADDR, + LINEAR_DGAIN_L_ADDR, + LINEAR_VMAX_H_ADDR, + LINEAR_VMAX_L_ADDR, + LINEAR_REGS_NUM +}; + +typedef enum _SC2331_1L_MODE_E { + SC2331_1L_MODE_1920X1080P30 = 0, + SC2331_1L_MODE_LINEAR_NUM, + SC2331_1L_MODE_NUM +} SC2331_1L_MODE_E; + +typedef struct _SC2331_1L_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + char name[64]; +} SC2331_1L_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastSC2331_1L[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunSC2331_1L_BusInfo[]; +extern CVI_U16 g_au16SC2331_1L_GainMode[]; +extern CVI_U16 g_au16SC2331_1L_L2SMode[]; +extern const CVI_U8 sc2331_1L_i2c_addr; +extern const CVI_U32 sc2331_1L_addr_byte; +extern const CVI_U32 sc2331_1L_data_byte; +extern void sc2331_1L_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern void sc2331_1L_init(VI_PIPE ViPipe); +extern void sc2331_1L_exit(VI_PIPE ViPipe); +extern void sc2331_1L_standby(VI_PIPE ViPipe); +extern void sc2331_1L_restart(VI_PIPE ViPipe); +extern int sc2331_1L_write_register(VI_PIPE ViPipe, int addr, int data); +extern int sc2331_1L_read_register(VI_PIPE ViPipe, int addr); +extern int sc2331_1L_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC2331_1L_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos_param.h new file mode 100644 index 000000000..4ad8b58cd --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_cmos_param.h @@ -0,0 +1,125 @@ +#ifndef __SC2331_1L_CMOS_PARAM_H_ +#define __SC2331_1L_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc2331_1L_cmos_ex.h" + +static const SC2331_1L_MODE_S g_astSC2331_1L_mode[SC2331_1L_MODE_NUM] = { + [SC2331_1L_MODE_1920X1080P30] = { + .name = "1080p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 0.51, /* 1125 * 30 / 0x7FFF */ + .u32HtsDef = 2560, + .u32VtsDef = 1530, + .stExp[0] = { + .u16Min = 2,//3 + .u16Max = 1530*2 - 13, + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u16Min = 1024, + .u16Max = 32768, + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[0] = { + .u16Min = 1024, + .u16Max = 4096, + .u16Def = 1024, + .u16Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {256, 256, 256, 256, 0, 0, 0, 0 + #ifdef ARCH_CV182X + , 1092, 1092, 1092, 1092 + #endif + }, + .stAuto = { + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + #ifdef ARCH_CV182X + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + #endif + }, + }, +}; + +struct combo_dev_attr_s sc2331_1L_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {3, 2, -1, -1, -1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC2331_1L_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_sensor_ctl.c new file mode 100644 index 000000000..fc098a946 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2331_1L/sc2331_1L_sensor_ctl.c @@ -0,0 +1,388 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "cvi_sns_ctrl.h" +#include "sc2331_1L_cmos_ex.h" + +#define SC2331_1L_CHIP_ID_HI_ADDR 0x3107 +#define SC2331_1L_CHIP_ID_LO_ADDR 0x3108 +#define SC2331_1L_CHIP_ID 0xcb5c + +static void sc2331_1L_linear_1080p30_init(VI_PIPE ViPipe); + +const CVI_U8 sc2331_1L_i2c_addr = 0x30; /* I2C Address of SC2331_1L */ +const CVI_U32 sc2331_1L_addr_byte = 2; +const CVI_U32 sc2331_1L_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int sc2331_1L_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunSC2331_1L_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, sc2331_1L_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int sc2331_1L_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int sc2331_1L_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (sc2331_1L_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, sc2331_1L_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, sc2331_1L_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (sc2331_1L_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int sc2331_1L_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (sc2331_1L_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (sc2331_1L_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, sc2331_1L_addr_byte + sc2331_1L_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void sc2331_1L_prog(VI_PIPE ViPipe, int *rom) +{ + int i = 0; + + while (1) { + int lookup = rom[i++]; + int addr = (lookup >> 16) & 0xFFFF; + int data = lookup & 0xFFFF; + + if (addr == 0xFFFE) + delay_ms(data); + else if (addr != 0xFFFF) + sc2331_1L_write_register(ViPipe, addr, data); + } +} + +void sc2331_1L_standby(VI_PIPE ViPipe) +{ + sc2331_1L_write_register(ViPipe, 0x0100, 0x00); +} + +void sc2331_1L_restart(VI_PIPE ViPipe) +{ + sc2331_1L_write_register(ViPipe, 0x0100, 0x00); + delay_ms(20); + sc2331_1L_write_register(ViPipe, 0x0100, 0x01); +} + +void sc2331_1L_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastSC2331_1L[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + if (g_pastSC2331_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].bUpdate == CVI_TRUE) { + sc2331_1L_write_register(ViPipe, + g_pastSC2331_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastSC2331_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } + } +} + +void sc2331_1L_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = 0; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x6; + break; + case ISP_SNS_FLIP: + val |= 0x60; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x66; + break; + default: + return; + } + + sc2331_1L_write_register(ViPipe, 0x3221, val); +} + + +int sc2331_1L_probe(VI_PIPE ViPipe) +{ +int nVal; + CVI_U16 chip_id; + + usleep(4*1000); + if (sc2331_1L_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = sc2331_1L_read_register(ViPipe, SC2331_1L_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = sc2331_1L_read_register(ViPipe, SC2331_1L_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != SC2331_1L_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + +// printf("======%d\n",ViPipe); + return CVI_SUCCESS; +} + + + +/* 1080P30 and 1080P25 */ +static void sc2331_1L_linear_1080p30_init(VI_PIPE ViPipe) +{ + sc2331_1L_write_register(ViPipe, 0x0103, 0x01); + sc2331_1L_write_register(ViPipe, 0x0100, 0x00); + sc2331_1L_write_register(ViPipe, 0x36e9, 0x80); + sc2331_1L_write_register(ViPipe, 0x37f9, 0x80); + sc2331_1L_write_register(ViPipe, 0x3018, 0x1a); + sc2331_1L_write_register(ViPipe, 0x3019, 0x0e); + sc2331_1L_write_register(ViPipe, 0x301f, 0x20); + sc2331_1L_write_register(ViPipe, 0x3258, 0x0e); + sc2331_1L_write_register(ViPipe, 0x3301, 0x06); + sc2331_1L_write_register(ViPipe, 0x3302, 0x10); + sc2331_1L_write_register(ViPipe, 0x3304, 0x68); + sc2331_1L_write_register(ViPipe, 0x3306, 0x90); + sc2331_1L_write_register(ViPipe, 0x3308, 0x18); + sc2331_1L_write_register(ViPipe, 0x3309, 0x80); + sc2331_1L_write_register(ViPipe, 0x330a, 0x01); + sc2331_1L_write_register(ViPipe, 0x330b, 0x48); + sc2331_1L_write_register(ViPipe, 0x330d, 0x18); + sc2331_1L_write_register(ViPipe, 0x331c, 0x02); + sc2331_1L_write_register(ViPipe, 0x331e, 0x59); + sc2331_1L_write_register(ViPipe, 0x331f, 0x71); + sc2331_1L_write_register(ViPipe, 0x3333, 0x10); + sc2331_1L_write_register(ViPipe, 0x3334, 0x40); + sc2331_1L_write_register(ViPipe, 0x3364, 0x56); + sc2331_1L_write_register(ViPipe, 0x3390, 0x08); + sc2331_1L_write_register(ViPipe, 0x3391, 0x09); + sc2331_1L_write_register(ViPipe, 0x3392, 0x0b); + sc2331_1L_write_register(ViPipe, 0x3393, 0x0a); + sc2331_1L_write_register(ViPipe, 0x3394, 0x2a); + sc2331_1L_write_register(ViPipe, 0x3395, 0x2a); + sc2331_1L_write_register(ViPipe, 0x3396, 0x48); + sc2331_1L_write_register(ViPipe, 0x3397, 0x49); + sc2331_1L_write_register(ViPipe, 0x3398, 0x4b); + sc2331_1L_write_register(ViPipe, 0x3399, 0x06); + sc2331_1L_write_register(ViPipe, 0x339a, 0x0a); + sc2331_1L_write_register(ViPipe, 0x339b, 0x30); + sc2331_1L_write_register(ViPipe, 0x339c, 0x48); + sc2331_1L_write_register(ViPipe, 0x33ad, 0x2c); + sc2331_1L_write_register(ViPipe, 0x33ae, 0x38); + sc2331_1L_write_register(ViPipe, 0x33b3, 0x40); + sc2331_1L_write_register(ViPipe, 0x349f, 0x02); + sc2331_1L_write_register(ViPipe, 0x34a6, 0x09); + sc2331_1L_write_register(ViPipe, 0x34a7, 0x0f); + sc2331_1L_write_register(ViPipe, 0x34a8, 0x30); + sc2331_1L_write_register(ViPipe, 0x34a9, 0x28); + sc2331_1L_write_register(ViPipe, 0x34f8, 0x5f); + sc2331_1L_write_register(ViPipe, 0x34f9, 0x28); + sc2331_1L_write_register(ViPipe, 0x3630, 0xc6); + sc2331_1L_write_register(ViPipe, 0x3633, 0x33); + sc2331_1L_write_register(ViPipe, 0x3637, 0x6b); + sc2331_1L_write_register(ViPipe, 0x363c, 0xc1); + sc2331_1L_write_register(ViPipe, 0x363e, 0xc2); + sc2331_1L_write_register(ViPipe, 0x3670, 0x2e); + sc2331_1L_write_register(ViPipe, 0x3674, 0xc5); + sc2331_1L_write_register(ViPipe, 0x3675, 0xc7); + sc2331_1L_write_register(ViPipe, 0x3676, 0xcb); + sc2331_1L_write_register(ViPipe, 0x3677, 0x44); + sc2331_1L_write_register(ViPipe, 0x3678, 0x48); + sc2331_1L_write_register(ViPipe, 0x3679, 0x48); + sc2331_1L_write_register(ViPipe, 0x367c, 0x08); + sc2331_1L_write_register(ViPipe, 0x367d, 0x0b); + sc2331_1L_write_register(ViPipe, 0x367e, 0x0b); + sc2331_1L_write_register(ViPipe, 0x367f, 0x0f); + sc2331_1L_write_register(ViPipe, 0x3690, 0x33); + sc2331_1L_write_register(ViPipe, 0x3691, 0x33); + sc2331_1L_write_register(ViPipe, 0x3692, 0x33); + sc2331_1L_write_register(ViPipe, 0x3693, 0x84); + sc2331_1L_write_register(ViPipe, 0x3694, 0x85); + sc2331_1L_write_register(ViPipe, 0x3695, 0x8d); + sc2331_1L_write_register(ViPipe, 0x3696, 0x9c); + sc2331_1L_write_register(ViPipe, 0x369c, 0x0b); + sc2331_1L_write_register(ViPipe, 0x369d, 0x0f); + sc2331_1L_write_register(ViPipe, 0x369e, 0x09); + sc2331_1L_write_register(ViPipe, 0x369f, 0x0b); + sc2331_1L_write_register(ViPipe, 0x36a0, 0x0f); + sc2331_1L_write_register(ViPipe, 0x36ec, 0x0c); + sc2331_1L_write_register(ViPipe, 0x370f, 0x01); + sc2331_1L_write_register(ViPipe, 0x3722, 0x05); + sc2331_1L_write_register(ViPipe, 0x3724, 0x20); + sc2331_1L_write_register(ViPipe, 0x3725, 0x91); + sc2331_1L_write_register(ViPipe, 0x3771, 0x05); + sc2331_1L_write_register(ViPipe, 0x3772, 0x05); + sc2331_1L_write_register(ViPipe, 0x3773, 0x05); + sc2331_1L_write_register(ViPipe, 0x377a, 0x0b); + sc2331_1L_write_register(ViPipe, 0x377b, 0x0f); + sc2331_1L_write_register(ViPipe, 0x3900, 0x19); + sc2331_1L_write_register(ViPipe, 0x3905, 0xb8); + sc2331_1L_write_register(ViPipe, 0x391b, 0x80); + sc2331_1L_write_register(ViPipe, 0x391c, 0x04); + sc2331_1L_write_register(ViPipe, 0x391d, 0x81); + sc2331_1L_write_register(ViPipe, 0x3933, 0xc0); + sc2331_1L_write_register(ViPipe, 0x3934, 0x08); + sc2331_1L_write_register(ViPipe, 0x3940, 0x72); + sc2331_1L_write_register(ViPipe, 0x3941, 0x00); + sc2331_1L_write_register(ViPipe, 0x3942, 0x00); + sc2331_1L_write_register(ViPipe, 0x3943, 0x09); + sc2331_1L_write_register(ViPipe, 0x3946, 0x10); + sc2331_1L_write_register(ViPipe, 0x3957, 0x86); + sc2331_1L_write_register(ViPipe, 0x3e01, 0x8b); + sc2331_1L_write_register(ViPipe, 0x3e02, 0xd0); + sc2331_1L_write_register(ViPipe, 0x3e08, 0x00); + sc2331_1L_write_register(ViPipe, 0x440e, 0x02); + sc2331_1L_write_register(ViPipe, 0x4509, 0x28); + sc2331_1L_write_register(ViPipe, 0x450d, 0x10); + sc2331_1L_write_register(ViPipe, 0x4819, 0x09); + sc2331_1L_write_register(ViPipe, 0x481b, 0x05); + sc2331_1L_write_register(ViPipe, 0x481d, 0x14); + sc2331_1L_write_register(ViPipe, 0x481f, 0x04); + sc2331_1L_write_register(ViPipe, 0x4821, 0x0a); + sc2331_1L_write_register(ViPipe, 0x4823, 0x05); + sc2331_1L_write_register(ViPipe, 0x4825, 0x04); + sc2331_1L_write_register(ViPipe, 0x4827, 0x05); + sc2331_1L_write_register(ViPipe, 0x4829, 0x08); + sc2331_1L_write_register(ViPipe, 0x5780, 0x66); + sc2331_1L_write_register(ViPipe, 0x578d, 0x40); + sc2331_1L_write_register(ViPipe, 0x5799, 0x06); + sc2331_1L_write_register(ViPipe, 0x36e9, 0x20); + sc2331_1L_write_register(ViPipe, 0x37f9, 0x27); + + sc2331_1L_default_reg_init(ViPipe); + + sc2331_1L_write_register(ViPipe, 0x0100, 0x01); + + // printf("ViPipe:%d,===SC2331_1L 1080P 30fps 10bit LINE Init OK!===\n", ViPipe); +} + +void sc2331_1L_init(VI_PIPE ViPipe) +{ + sc2331_1L_i2c_init(ViPipe); + + //linear mode only + sc2331_1L_linear_1080p30_init(ViPipe); + + g_pastSC2331_1L[ViPipe]->bInit = CVI_TRUE; +} + +void sc2331_1L_exit(VI_PIPE ViPipe) +{ + sc2331_1L_i2c_exit(ViPipe); +} \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/Makefile b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/Makefile new file mode 100644 index 000000000..5cdee09c9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_sc2336p.a +TARGET_SO = $(MW_LIB)/libsns_sc2336p.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJ) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos.c b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos.c new file mode 100644 index 000000000..27c5fb7bf --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos.c @@ -0,0 +1,905 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "sc2336p_cmos_ex.h" +#include "sc2336p_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define SC2336P_ID 35 +#define SENSOR_SC2336P_WIDTH 1920 +#define SENSOR_SC2336P_HEIGHT 1080 +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastSC2336P[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define SC2336P_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastSC2336P[dev]) +#define SC2336P_SENSOR_SET_CTX(dev, pstCtx) (g_pastSC2336P[dev] = pstCtx) +#define SC2336P_SENSOR_RESET_CTX(dev) (g_pastSC2336P[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunSC2336P_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16SC2336P_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16SC2336P_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +SC2336P_STATE_S g_astSC2336P_State[VI_MAX_PIPE_NUM] = {{0} }; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ + +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****SC2336P Lines Range*****/ +#define SC2336P_FULL_LINES_MAX (0xFFFF) + +/*****SC2336P Register Address*****/ +#define SC2336P_SHS1_0_ADDR 0x3E00 +#define SC2336P_SHS1_1_ADDR 0x3E01 +#define SC2336P_SHS1_2_ADDR 0x3E02 +#define SC2336P_AGAIN0_ADDR 0x3E09 +#define SC2336P_DGAIN0_ADDR 0x3E06 +#define SC2336P_VMAX_ADDR 0x320E +#define SC2336P_TABLE_END 0xFFFF + +#define SC2336P_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const SC2336P_MODE_S *pstMode; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astSC2336P_mode[pstSnsState->u8ImgMode]; +#if 0 + memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S)); +#endif + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = SC2336P_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_DB; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + default: + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u16Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u16Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u16Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u16Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max; + pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astSC2336P_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astSC2336P_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astSC2336P_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case SC2336P_MODE_1080P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > SC2336P_FULL_LINES_MAX) ? SC2336P_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_ADDR].u32Data = ((u32VMAX & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_ADDR].u32Data = (u32VMAX & 0xFF); + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 6; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (WDR_MODE_2To1_LINE != pstSnsState->enWDRMode) { + CVI_U32 u32TmpIntTime = u32IntTime[0]; + /* linear exposure reg range: + * min : 1 + * max : (vts - 6) + * step : 1 + */ + u32TmpIntTime = (u32TmpIntTime > (pstSnsState->au32FL[0] - 6)) ? + (pstSnsState->au32FL[0] - 6) : u32TmpIntTime; + if (!u32TmpIntTime) + u32TmpIntTime = 1; + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_ADDR].u32Data = ((u32TmpIntTime & 0xF000) >> 12); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_ADDR].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_2_ADDR].u32Data = (u32TmpIntTime & 0xF) << 4; + } + + return CVI_SUCCESS; + +} + +struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +}; + +static CVI_U32 Again_table[] = { + 1024, 2048, 4096, 8192, 16384, 32768 +}; + +static CVI_U32 AgainReg[] = { + 0x00, 0x08, 0x09, 0x0b, 0x0f, 0x1f +}; + +static struct gain_tbl_info_s DgainInfo[] = { + { + .gainMax = 2016, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x01, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4096, + .idxBase = 64, + .regGain = 0x03, + .regGainFineBase = 0x80, + .regGainFineStep = 0, + }, +}; + +static CVI_U32 Dgain_table[] = { + 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, + 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, + 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, + 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, + 4096, +}; + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 tableSize = sizeof(Again_table) / sizeof(CVI_U32); + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= Again_table[tableSize - 1]) { + *pu32AgainLin = Again_table[tableSize - 1]; + *pu32AgainDb = AgainReg[tableSize - 1]; + return CVI_SUCCESS; + } + + for (CVI_U32 i = 1; i < tableSize; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = AgainReg[i - 1]; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 tableSize = sizeof(Dgain_table) / sizeof(CVI_U32); + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[tableSize - 1]) { + *pu32DgainLin = Dgain_table[tableSize - 1]; + *pu32DgainDb = tableSize - 1; + return CVI_SUCCESS; + } + + for (CVI_U32 i = 1; i < tableSize; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + CVI_S32 i = 0, tbl_num = 0; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + + /* Again. */ + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_0_ADDR].u32Data = (u32Again & 0xFF); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_0_ADDR].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_1_ADDR].u32Data = (u32Dgain & 0xFF); + } + return CVI_SUCCESS; +} + + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + // pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + // pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const SC2336P_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astSC2336P_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = SC2336P_MODE_1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astSC2336P_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunSC2336P_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = sc2336p_i2c_addr; + pstI2c_data[i].u32AddrByteNum = sc2336p_addr_byte; + pstI2c_data[i].u32DataByteNum = sc2336p_data_byte; + } + + //DOL 2t1 Mode Regs + switch (pstSnsState->enWDRMode) { + case WDR_MODE_2To1_LINE: + break; + default: + //Linear Mode Regs + pstI2c_data[LINEAR_SHS1_0_ADDR].u32RegAddr = SC2336P_SHS1_0_ADDR; + pstI2c_data[LINEAR_SHS1_1_ADDR].u32RegAddr = SC2336P_SHS1_1_ADDR; + pstI2c_data[LINEAR_SHS1_2_ADDR].u32RegAddr = SC2336P_SHS1_2_ADDR; + pstI2c_data[LINEAR_AGAIN_0_ADDR].u32RegAddr = SC2336P_AGAIN0_ADDR; + pstI2c_data[LINEAR_DGAIN_0_ADDR].u32RegAddr = SC2336P_DGAIN0_ADDR; + pstI2c_data[LINEAR_DGAIN_1_ADDR].u32RegAddr = SC2336P_DGAIN0_ADDR + 1; + pstI2c_data[LINEAR_VMAX_0_ADDR].u32RegAddr = SC2336P_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1_ADDR].u32RegAddr = SC2336P_VMAX_ADDR + 1; + + break; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (SC2336P_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = SC2336P_MODE_1080P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const SC2336P_MODE_S *pstMode = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = SC2336P_MODE_1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astSC2336P_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &sc2336p_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astSC2336P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astSC2336P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &sc2336p_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = sc2336p_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = sc2336p_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 sc2336p_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunSC2336P_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + SC2336P_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + SC2336P_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = SC2336P_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, SC2336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, SC2336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, SC2336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16SC2336P_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16SC2336P_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsSC2336P_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = sc2336p_standby, + .pfnRestart = sc2336p_restart, + .pfnMirrorFlip = sc2336p_mirror_flip, + .pfnWriteReg = sc2336p_write_register, + .pfnReadReg = sc2336p_read_register, + .pfnSetBusInfo = sc2336p_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sc2336p_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos_ex.h new file mode 100644 index 000000000..45c005be5 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos_ex.h @@ -0,0 +1,85 @@ +#ifndef __SC2336P_CMOS_EX_H_ +#define __SC2336P_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum sc2336p_linear_regs_e { + LINEAR_SHS1_0_ADDR, + LINEAR_SHS1_1_ADDR, + LINEAR_SHS1_2_ADDR, + LINEAR_AGAIN_0_ADDR, + LINEAR_DGAIN_0_ADDR, + LINEAR_DGAIN_1_ADDR, + LINEAR_VMAX_0_ADDR, + LINEAR_VMAX_1_ADDR, + LINEAR_REGS_NUM +}; + + +typedef enum _SC2336P_MODE_E { + SC2336P_MODE_1080P30 = 0, + SC2336P_MODE_LINEAR_NUM, + SC2336P_MODE_NUM +} SC2336P_MODE_E; + +typedef struct _SC2336P_STATE_S { + CVI_U32 u32Sexp_MAX; /* (2*{16’h3e23,16’h3e24} – 'd10)/2 */ +} SC2336P_STATE_S; + +typedef struct _SC2336P_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + CVI_U16 u16SexpMaxReg; /* {16’h3e23,16’h3e24} */ + char name[64]; +} SC2336P_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastSC2336P[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunSC2336P_BusInfo[]; +extern CVI_U16 g_au16SC2336P_GainMode[]; +extern CVI_U16 g_au16SC2336P_L2SMode[]; +extern const CVI_U8 sc2336p_i2c_addr; +extern const CVI_U32 sc2336p_addr_byte; +extern const CVI_U32 sc2336p_data_byte; +extern void sc2336p_init(VI_PIPE ViPipe); +extern void sc2336p_exit(VI_PIPE ViPipe); +extern void sc2336p_standby(VI_PIPE ViPipe); +extern void sc2336p_restart(VI_PIPE ViPipe); +extern int sc2336p_write_register(VI_PIPE ViPipe, int addr, int data); +extern int sc2336p_read_register(VI_PIPE ViPipe, int addr); +extern void sc2336p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int sc2336p_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC2336P_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos_param.h new file mode 100644 index 000000000..feebdae9a --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_cmos_param.h @@ -0,0 +1,125 @@ +#ifndef __SC2336P_CMOS_PARAM_H_ +#define __SC2336P_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc2336p_cmos_ex.h" + +static const SC2336P_MODE_S g_astSC2336P_mode[SC2336P_MODE_NUM] = { + [SC2336P_MODE_1080P30] = { + .name = "1080p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 0.51, /* 1125 * 30 / 0xFFFF*/ + .u32HtsDef = 2560, + .u32VtsDef = 1125, + .stExp[0] = { + .u16Min = 1, + .u16Max = 12184 - 6, + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u16Min = 1024, + .u16Max = 32768, + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[0] = { + .u16Min = 1024, + .u16Max = 4096, + .u16Def = 1024, + .u16Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {260, 260, 260, 260, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1093, 1093, 1093, 1093 +#endif + }, + .stAuto = { + {260, 260, 260, 260, 260, 252, 252, 252, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 252, 252, 252, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 252, 252, 252, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 252, 252, 252, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1093, 1093, 1093, 1093, 1093, 1091, 1091, 1091, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1091, 1091, 1091, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1091, 1091, 1091, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1091, 1091, 1091, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, +#endif + }, + }, +}; + +struct combo_dev_attr_s sc2336p_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {2, 1, 3, -1, -1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + } + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC2336P_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_sensor_ctl.c new file mode 100644 index 000000000..28af2ec0f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc2336p/sc2336p_sensor_ctl.c @@ -0,0 +1,410 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc2336p_cmos_ex.h" + +static void sc2336p_linear_1080p30_init(VI_PIPE ViPipe); + +const CVI_U8 sc2336p_i2c_addr = 0x30; /* I2C Address of SC2336P */ +const CVI_U32 sc2336p_addr_byte = 2; +const CVI_U32 sc2336p_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int sc2336p_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunSC2336P_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, sc2336p_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int sc2336p_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int sc2336p_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + char buf[8]; + int idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (sc2336p_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, sc2336p_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, sc2336p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (sc2336p_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int sc2336p_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (sc2336p_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (sc2336p_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, sc2336p_addr_byte + sc2336p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void sc2336p_prog(VI_PIPE ViPipe, int *rom) +{ + int i = 0; + + while (1) { + int lookup = rom[i++]; + int addr = (lookup >> 16) & 0xFFFF; + int data = lookup & 0xFFFF; + + if (addr == 0xFFFE) + delay_ms(data); + else if (addr != 0xFFFF) + sc2336p_write_register(ViPipe, addr, data); + } +} + +void sc2336p_standby(VI_PIPE ViPipe) +{ + sc2336p_write_register(ViPipe, 0x0100, 0x00); +} + +void sc2336p_restart(VI_PIPE ViPipe) +{ + sc2336p_write_register(ViPipe, 0x0100, 0x00); + delay_ms(20); + sc2336p_write_register(ViPipe, 0x0100, 0x01); +} + +void sc2336p_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastSC2336P[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + sc2336p_write_register(ViPipe, + g_pastSC2336P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastSC2336P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +#define SC2336P_CHIP_ID_HI_ADDR 0x3107 +#define SC2336P_CHIP_ID_LO_ADDR 0x3108 +#define SC2336P_CHIP_ID 0x9b3a + +void sc2336p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = 0; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x6; + break; + case ISP_SNS_FLIP: + val |= 0x60; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x66; + break; + default: + return; + } + + sc2336p_write_register(ViPipe, 0x3221, val); +} + +int sc2336p_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + usleep(4*1000); + if (sc2336p_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = sc2336p_read_register(ViPipe, SC2336P_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = sc2336p_read_register(ViPipe, SC2336P_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != SC2336P_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + return CVI_SUCCESS; +} + + +void sc2336p_init(VI_PIPE ViPipe) +{ + WDR_MODE_E enWDRMode; + CVI_BOOL bInit; + + bInit = g_pastSC2336P[ViPipe]->bInit; + enWDRMode = g_pastSC2336P[ViPipe]->enWDRMode; + + sc2336p_i2c_init(ViPipe); + + /* When sensor first init, config all registers */ + if (bInit == CVI_FALSE) { + if (enWDRMode == WDR_MODE_NONE) { + sc2336p_linear_1080p30_init(ViPipe); + } + } + /* When sensor switch mode(linear<->WDR or resolution), config different registers(if possible) */ + else { + if (enWDRMode == WDR_MODE_NONE) { + sc2336p_linear_1080p30_init(ViPipe); + } + } + g_pastSC2336P[ViPipe]->bInit = CVI_TRUE; +} + +void sc2336p_exit(VI_PIPE ViPipe) +{ + sc2336p_i2c_exit(ViPipe); +} + +/* 1080P30 and 1080P25 */ +static void sc2336p_linear_1080p30_init(VI_PIPE ViPipe) +{ + sc2336p_write_register(ViPipe, 0x0103, 0x01); + sc2336p_write_register(ViPipe, 0x0100, 0x00); + sc2336p_write_register(ViPipe, 0x36e9, 0x80); + sc2336p_write_register(ViPipe, 0x37f9, 0x80); + sc2336p_write_register(ViPipe, 0x301f, 0x02); + sc2336p_write_register(ViPipe, 0x3106, 0x05); + sc2336p_write_register(ViPipe, 0x3248, 0x04); + sc2336p_write_register(ViPipe, 0x3249, 0x0b); + sc2336p_write_register(ViPipe, 0x3253, 0x08); + sc2336p_write_register(ViPipe, 0x3301, 0x09); + sc2336p_write_register(ViPipe, 0x3302, 0xff); + sc2336p_write_register(ViPipe, 0x3303, 0x10); + sc2336p_write_register(ViPipe, 0x3306, 0x80); + sc2336p_write_register(ViPipe, 0x3307, 0x02); + sc2336p_write_register(ViPipe, 0x3309, 0xc8); + sc2336p_write_register(ViPipe, 0x330a, 0x01); + sc2336p_write_register(ViPipe, 0x330b, 0x30); + sc2336p_write_register(ViPipe, 0x330c, 0x16); + sc2336p_write_register(ViPipe, 0x330d, 0xff); + sc2336p_write_register(ViPipe, 0x3318, 0x02); + sc2336p_write_register(ViPipe, 0x331f, 0xb9); + sc2336p_write_register(ViPipe, 0x3321, 0x0a); + sc2336p_write_register(ViPipe, 0x3327, 0x0e); + sc2336p_write_register(ViPipe, 0x332b, 0x12); + sc2336p_write_register(ViPipe, 0x3333, 0x10); + sc2336p_write_register(ViPipe, 0x3334, 0x40); + sc2336p_write_register(ViPipe, 0x335e, 0x06); + sc2336p_write_register(ViPipe, 0x335f, 0x0a); + sc2336p_write_register(ViPipe, 0x3364, 0x1f); + sc2336p_write_register(ViPipe, 0x337c, 0x02); + sc2336p_write_register(ViPipe, 0x337d, 0x0e); + sc2336p_write_register(ViPipe, 0x3390, 0x09); + sc2336p_write_register(ViPipe, 0x3391, 0x0f); + sc2336p_write_register(ViPipe, 0x3392, 0x1f); + sc2336p_write_register(ViPipe, 0x3393, 0x20); + sc2336p_write_register(ViPipe, 0x3394, 0x20); + sc2336p_write_register(ViPipe, 0x3395, 0xe0); + sc2336p_write_register(ViPipe, 0x33a2, 0x04); + sc2336p_write_register(ViPipe, 0x33b1, 0x80); + sc2336p_write_register(ViPipe, 0x33b2, 0x68); + sc2336p_write_register(ViPipe, 0x33b3, 0x42); + sc2336p_write_register(ViPipe, 0x33f9, 0x90); + sc2336p_write_register(ViPipe, 0x33fb, 0xd0); + sc2336p_write_register(ViPipe, 0x33fc, 0x0f); + sc2336p_write_register(ViPipe, 0x33fd, 0x1f); + sc2336p_write_register(ViPipe, 0x349f, 0x03); + sc2336p_write_register(ViPipe, 0x34a6, 0x0f); + sc2336p_write_register(ViPipe, 0x34a7, 0x1f); + sc2336p_write_register(ViPipe, 0x34a8, 0x42); + sc2336p_write_register(ViPipe, 0x34a9, 0x18); + sc2336p_write_register(ViPipe, 0x34aa, 0x01); + sc2336p_write_register(ViPipe, 0x34ab, 0x43); + sc2336p_write_register(ViPipe, 0x34ac, 0x01); + sc2336p_write_register(ViPipe, 0x34ad, 0x80); + sc2336p_write_register(ViPipe, 0x3630, 0xf4); + sc2336p_write_register(ViPipe, 0x3632, 0x44); + sc2336p_write_register(ViPipe, 0x3633, 0x22); + sc2336p_write_register(ViPipe, 0x3639, 0xf4); + sc2336p_write_register(ViPipe, 0x363c, 0x47); + sc2336p_write_register(ViPipe, 0x3670, 0x09); + sc2336p_write_register(ViPipe, 0x3674, 0xf4); + sc2336p_write_register(ViPipe, 0x3675, 0xfb); + sc2336p_write_register(ViPipe, 0x3676, 0xed); + sc2336p_write_register(ViPipe, 0x367c, 0x09); + sc2336p_write_register(ViPipe, 0x367d, 0x0f); + sc2336p_write_register(ViPipe, 0x3690, 0x22); + sc2336p_write_register(ViPipe, 0x3691, 0x22); + sc2336p_write_register(ViPipe, 0x3692, 0x22); + sc2336p_write_register(ViPipe, 0x3698, 0x89); + sc2336p_write_register(ViPipe, 0x3699, 0x96); + sc2336p_write_register(ViPipe, 0x369a, 0xd0); + sc2336p_write_register(ViPipe, 0x369b, 0xd0); + sc2336p_write_register(ViPipe, 0x369c, 0x09); + sc2336p_write_register(ViPipe, 0x369d, 0x0f); + sc2336p_write_register(ViPipe, 0x36a2, 0x09); + sc2336p_write_register(ViPipe, 0x36a3, 0x0f); + sc2336p_write_register(ViPipe, 0x36a4, 0x1f); + sc2336p_write_register(ViPipe, 0x36d0, 0x01); + sc2336p_write_register(ViPipe, 0x3722, 0x81); + sc2336p_write_register(ViPipe, 0x3724, 0x41); + sc2336p_write_register(ViPipe, 0x3725, 0xc1); + sc2336p_write_register(ViPipe, 0x3728, 0x20); + sc2336p_write_register(ViPipe, 0x3900, 0x0d); + sc2336p_write_register(ViPipe, 0x3905, 0x98); + sc2336p_write_register(ViPipe, 0x391b, 0x81); + sc2336p_write_register(ViPipe, 0x391c, 0x10); + sc2336p_write_register(ViPipe, 0x3933, 0x81); + sc2336p_write_register(ViPipe, 0x3934, 0xd0); + sc2336p_write_register(ViPipe, 0x3940, 0x75); + sc2336p_write_register(ViPipe, 0x3941, 0x00); + sc2336p_write_register(ViPipe, 0x3942, 0x01); + sc2336p_write_register(ViPipe, 0x3943, 0xd1); + sc2336p_write_register(ViPipe, 0x3952, 0x02); + sc2336p_write_register(ViPipe, 0x3953, 0x0f); + sc2336p_write_register(ViPipe, 0x3e01, 0x45); + sc2336p_write_register(ViPipe, 0x3e02, 0xf0); + sc2336p_write_register(ViPipe, 0x3e08, 0x1f); + sc2336p_write_register(ViPipe, 0x3e1b, 0x14); + sc2336p_write_register(ViPipe, 0x440e, 0x02); + sc2336p_write_register(ViPipe, 0x4509, 0x38); + sc2336p_write_register(ViPipe, 0x5799, 0x06); + sc2336p_write_register(ViPipe, 0x5ae0, 0xfe); + sc2336p_write_register(ViPipe, 0x5ae1, 0x40); + sc2336p_write_register(ViPipe, 0x5ae2, 0x30); + sc2336p_write_register(ViPipe, 0x5ae3, 0x28); + sc2336p_write_register(ViPipe, 0x5ae4, 0x20); + sc2336p_write_register(ViPipe, 0x5ae5, 0x30); + sc2336p_write_register(ViPipe, 0x5ae6, 0x28); + sc2336p_write_register(ViPipe, 0x5ae7, 0x20); + sc2336p_write_register(ViPipe, 0x5ae8, 0x3c); + sc2336p_write_register(ViPipe, 0x5ae9, 0x30); + sc2336p_write_register(ViPipe, 0x5aea, 0x28); + sc2336p_write_register(ViPipe, 0x5aeb, 0x3c); + sc2336p_write_register(ViPipe, 0x5aec, 0x30); + sc2336p_write_register(ViPipe, 0x5aed, 0x28); + sc2336p_write_register(ViPipe, 0x5aee, 0xfe); + sc2336p_write_register(ViPipe, 0x5aef, 0x40); + sc2336p_write_register(ViPipe, 0x5af4, 0x30); + sc2336p_write_register(ViPipe, 0x5af5, 0x28); + sc2336p_write_register(ViPipe, 0x5af6, 0x20); + sc2336p_write_register(ViPipe, 0x5af7, 0x30); + sc2336p_write_register(ViPipe, 0x5af8, 0x28); + sc2336p_write_register(ViPipe, 0x5af9, 0x20); + sc2336p_write_register(ViPipe, 0x5afa, 0x3c); + sc2336p_write_register(ViPipe, 0x5afb, 0x30); + sc2336p_write_register(ViPipe, 0x5afc, 0x28); + sc2336p_write_register(ViPipe, 0x5afd, 0x3c); + sc2336p_write_register(ViPipe, 0x5afe, 0x30); + sc2336p_write_register(ViPipe, 0x5aff, 0x28); + sc2336p_write_register(ViPipe, 0x36e9, 0x20); + sc2336p_write_register(ViPipe, 0x37f9, 0x27); + + sc2336p_default_reg_init(ViPipe); + + sc2336p_write_register(ViPipe, 0x0100, 0x01); + + printf("ViPipe:%d,===SC2336P 1080P 30fps 10bit LINE Init OK!===\n", ViPipe); +} diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/Makefile b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/Makefile new file mode 100644 index 000000000..f2679b71f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_sc4336p.a +TARGET_SO = $(MW_LIB)/libsns_sc4336p.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos.c b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos.c new file mode 100644 index 000000000..1901daec9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos.c @@ -0,0 +1,916 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "sc4336p_cmos_ex.h" +#include "sc4336p_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define SC4336P_ID 4336 +#define SENSOR_SC4336P_WIDTH 2560 +#define SENSOR_SC4336P_HEIGHT 1440 +#define SC4336P_I2C_ADDR_1 0x30 +#define SC4336P_I2C_ADDR_2 0x32 +#define SC4336P_I2C_ADDR_IS_VALID(addr) ((addr) == SC4336P_I2C_ADDR_1 || (addr) == SC4336P_I2C_ADDR_2) + +#define SC4336P_EXPACCURACY (1) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastSC4336P[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define SC4336P_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastSC4336P[dev]) +#define SC4336P_SENSOR_SET_CTX(dev, pstCtx) (g_pastSC4336P[dev] = pstCtx) +#define SC4336P_SENSOR_RESET_CTX(dev) (g_pastSC4336P[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunSC4336P_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16SC4336P_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16SC4336P_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +ISP_SNS_MIRRORFLIP_TYPE_E g_aeSc4336p_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****SC4336P Lines Range*****/ +#define SC4336P_FULL_LINES_MAX (0x7FFF) + +/*****SC4336P Register Address*****/ +#define SC4336P_EXP_ADDR 0x3E00 +#define SC4336P_AGAIN_ADDR 0x3E09 +#define SC4336P_DGAIN_ADDR 0x3E06 +#define SC4336P_VMAX_ADDR 0x320E + +#define SC4336P_RES_IS_1440P(w, h) ((w) == 2560 && (h) == 1440) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = SC4336P_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = SC4336P_EXPACCURACY; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_DB; + pstAeSnsDft->stAgainAccu.f32Accuracy = 6; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = g_astSC4336P_mode[pstSnsState->u8ImgMode].f32MaxFps; + pstAeSnsDft->f32MinFps = g_astSC4336P_mode[pstSnsState->u8ImgMode].f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = g_astSC4336P_mode[pstSnsState->u8ImgMode].stAgain[0].u32Max; + pstAeSnsDft->u32MinAgain = g_astSC4336P_mode[pstSnsState->u8ImgMode].stAgain[0].u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = g_astSC4336P_mode[pstSnsState->u8ImgMode].stDgain[0].u32Max; + pstAeSnsDft->u32MinDgain = g_astSC4336P_mode[pstSnsState->u8ImgMode].stDgain[0].u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = g_astSC4336P_mode[pstSnsState->u8ImgMode].stExp[0].u32Max; + pstAeSnsDft->u32MinIntTime = g_astSC4336P_mode[pstSnsState->u8ImgMode].stExp[0].u32Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astSC4336P_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astSC4336P_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astSC4336P_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case SC4336P_MODE_1440P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > SC4336P_FULL_LINES_MAX) ? SC4336P_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_ADDR].u32Data = ((u32VMAX & 0x7F00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_ADDR].u32Data = (u32VMAX & 0xFF); + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = (pstSnsState->u32FLStd << 1) - 8; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32TmpIntTime, u32MinTime, u32MaxTime; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + /* linear exposure reg range: + * min : 0 + * max : vts - 8 + * step : 1 + */ + u32MinTime = 0; + u32MaxTime = pstSnsState->au32FL[0] - 8; + u32TmpIntTime = (u32IntTime[0] > u32MaxTime) ? u32MaxTime : u32IntTime[0]; + u32TmpIntTime = (u32TmpIntTime < u32MinTime) ? u32MinTime : u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_ADDR].u32Data = ((u32TmpIntTime & 0xF000) >> 12); //bit[15:12] + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_ADDR].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4); //bit[11:4] + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_2_ADDR].u32Data = ((u32TmpIntTime & 0x000F) << 4); //bit[3:0] + + return CVI_SUCCESS; +} + +struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +}; + +static struct gain_tbl_info_s DgainInfo[] = { + { + .gainMax = 2016, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x01, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 8064, + .idxBase = 64, + .regGain = 0x03, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 16128, + .idxBase = 96, + .regGain = 0x07, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, +}; + +static CVI_U32 Dgain_table[] = { + 1024, 1055, 1088, 1120, 1152, 1183, 1216, 1248, 1280, 1311, 1344, 1376, 1408, 1439, 1472, + 1504, 1536, 1567, 1600, 1632, 1664, 1695, 1728, 1760, 1792, 1823, 1856, 1888, 1920, 1951, + 1984, 2016, 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, + 2816, 2880, 2944, 3008, 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, + 3840, 3904, 3968, 4032, 4096, 4224, 4352, 4480, 4608, 4736, 4864, 4992, 5120, 5248, 5376, + 5504, 5632, 5760, 5888, 6016, 6144, 6272, 6400, 6528, 6656, 6784, 6912, 7040, 7168, 7296, + 7424, 7552, 7680, 7808, 7936, 8064, 8192, 8448, 8704, 8960, 9216, 9472, 9728, 9984, 10240, + 10496, 10752, 11008, 11264, 11520, 11776, 12032, 12288, 12544, 12800, 13056, 13312, + 13568, 13824, 14080, 14336, 14592, 14848, 15104, 15360, 15616, 15872, 16128 +}; + +static const CVI_U32 dgain_table_size = ARRAY_SIZE(Dgain_table); + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 again = *pu32AgainLin; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (again < 2048) { + *pu32AgainDb = 0x00; + *pu32AgainLin = 1024; + } else if (again < 4096) { + *pu32AgainDb = 0x08; + *pu32AgainLin = 2048; + } else if (again < 8192) { + *pu32AgainDb = 0x09; + *pu32AgainLin = 4096; + } else if (again < 16384) { + *pu32AgainDb = 0x0B; + *pu32AgainLin = 8192; + } else if (again < 32768) { + *pu32AgainDb = 0x0F; + *pu32AgainLin = 16384; + } else { + *pu32AgainDb = 0x1F; + *pu32AgainLin = 32768; + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 i; + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[dgain_table_size - 1]) { + *pu32DgainLin = Dgain_table[dgain_table_size - 1]; + *pu32DgainDb = dgain_table_size - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < dgain_table_size; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + /* find Again register setting. */ + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_ADDR].u32Data = (u32Again & 0xFF); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_ADDR].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_D_FINEGAIN_ADDR].u32Data = (u32Dgain & 0xFF); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + //pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + //pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const SC4336P_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astSC4336P_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = SC4336P_MODE_1440P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astSC4336P_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunSC4336P_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = sc4336p_i2c_addr; + pstI2c_data[i].u32AddrByteNum = sc4336p_addr_byte; + pstI2c_data[i].u32DataByteNum = sc4336p_data_byte; + } + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + //Linear Mode Regs + pstI2c_data[LINEAR_SHS1_0_ADDR].u32RegAddr = SC4336P_EXP_ADDR; + pstI2c_data[LINEAR_SHS1_1_ADDR].u32RegAddr = SC4336P_EXP_ADDR + 1; + pstI2c_data[LINEAR_SHS1_2_ADDR].u32RegAddr = SC4336P_EXP_ADDR + 2; + + pstI2c_data[LINEAR_AGAIN_ADDR].u32RegAddr = SC4336P_AGAIN_ADDR; + pstI2c_data[LINEAR_DGAIN_ADDR].u32RegAddr = SC4336P_DGAIN_ADDR; + pstI2c_data[LINEAR_D_FINEGAIN_ADDR].u32RegAddr = SC4336P_DGAIN_ADDR + 1; + + pstI2c_data[LINEAR_VMAX_0_ADDR].u32RegAddr = SC4336P_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1_ADDR].u32RegAddr = SC4336P_VMAX_ADDR + 1; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (SC4336P_RES_IS_1440P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = SC4336P_MODE_1440P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + if (pstSnsState->bInit == CVI_TRUE && g_aeSc4336p_MirrorFip[ViPipe] != eSnsMirrorFlip) { + sc4336p_mirror_flip(ViPipe, eSnsMirrorFlip); + g_aeSc4336p_MirrorFip[ViPipe] = eSnsMirrorFlip; + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const SC4336P_MODE_S *pstMode = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = SC4336P_MODE_1440P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astSC4336P_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &sc4336p_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astSC4336P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astSC4336P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &sc4336p_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = sc4336p_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = sc4336p_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (SC4336P_I2C_ADDR_IS_VALID(s32I2cAddr)) + sc4336p_i2c_addr = s32I2cAddr; +} + +static CVI_S32 sc4336p_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunSC4336P_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + SC4336P_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + SC4336P_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = SC4336P_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, SC4336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, SC4336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, SC4336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16SC4336P_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16SC4336P_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsSC4336P_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = sc4336p_standby, + .pfnRestart = sc4336p_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = sc4336p_write_register, + .pfnReadReg = sc4336p_read_register, + .pfnSetBusInfo = sc4336p_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sc4336p_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos_ex.h new file mode 100644 index 000000000..d09e26b52 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos_ex.h @@ -0,0 +1,78 @@ +#ifndef __SC4336P_CMOS_EX_H_ +#define __SC4336P_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum sc4336p_linear_regs_e { + LINEAR_SHS1_0_ADDR, + LINEAR_SHS1_1_ADDR, + LINEAR_SHS1_2_ADDR, + LINEAR_AGAIN_ADDR, + LINEAR_DGAIN_ADDR, + LINEAR_D_FINEGAIN_ADDR, + LINEAR_VMAX_0_ADDR, + LINEAR_VMAX_1_ADDR, + LINEAR_REGS_NUM +}; + +typedef enum _SC4336P_MODE_E { + SC4336P_MODE_1440P30 = 0, + SC4336P_MODE_NUM +} SC4336P_MODE_E; + +typedef struct _SC4336P_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_LARGE_S stExp[2]; + SNS_ATTR_LARGE_S stAgain[2]; + SNS_ATTR_LARGE_S stDgain[2]; + char name[64]; +} SC4336P_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastSC4336P[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunSC4336P_BusInfo[]; +extern CVI_U16 g_au16SC4336P_GainMode[]; +extern CVI_U16 g_au16SC4336P_L2SMode[]; +extern CVI_U8 sc4336p_i2c_addr; +extern const CVI_U32 sc4336p_addr_byte; +extern const CVI_U32 sc4336p_data_byte; +extern void sc4336p_init(VI_PIPE ViPipe); +extern void sc4336p_exit(VI_PIPE ViPipe); +extern void sc4336p_standby(VI_PIPE ViPipe); +extern void sc4336p_restart(VI_PIPE ViPipe); +extern int sc4336p_write_register(VI_PIPE ViPipe, int addr, int data); +extern int sc4336p_read_register(VI_PIPE ViPipe, int addr); +extern void sc4336p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int sc4336p_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC4336P_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos_param.h new file mode 100644 index 000000000..d086f8ae9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_cmos_param.h @@ -0,0 +1,121 @@ +#ifndef __SC4336P_CMOS_PARAM_H_ +#define __SC4336P_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc4336p_cmos_ex.h" + +static const SC4336P_MODE_S g_astSC4336P_mode[SC4336P_MODE_NUM] = { + [SC4336P_MODE_1440P30] = { + .name = "1440p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 2560, + .u32Height = 1440, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2560, + .u32Height = 1440, + }, + .stMaxSize = { + .u32Width = 2560, + .u32Height = 1440, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 1.37, /* 1500 * 30 / 0x7FFF*/ + .u32HtsDef = 2800, + .u32VtsDef = 1500, + .stExp[0] = { + .u32Min = 0, + .u32Max = 1500 - 8, //vts - 8 + .u32Def = 400, + .u32Step = 1, + }, + .stAgain[0] = { + .u32Min = 1024, + .u32Max = 32768, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain[0] = { + .u32Min = 1024, + .u32Max = 16182, + .u32Def = 1024, + .u32Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {260, 260, 260, 260, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1093, 1093, 1093, 1093 +#endif + }, + .stAuto = { + {260, 260, 260, 260, 260, 260, 260, 260, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 260, 260, 260, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 260, 260, 260, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 260, 260, 260, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, +#endif + }, + }, +}; + +struct combo_dev_attr_s sc4336p_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {2, 1, 3, -1, -1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC4336P_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_sensor_ctl.c new file mode 100644 index 000000000..fccedf9d1 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc4336p/sc4336p_sensor_ctl.c @@ -0,0 +1,384 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc4336p_cmos_ex.h" + +static void sc4336p_linear_1440p30_init(VI_PIPE ViPipe); + +CVI_U8 sc4336p_i2c_addr = 0x30; /* I2C Address of SC4336P */ +const CVI_U32 sc4336p_addr_byte = 2; +const CVI_U32 sc4336p_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int sc4336p_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunSC4336P_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, sc4336p_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int sc4336p_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int sc4336p_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (sc4336p_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, sc4336p_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, sc4336p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (sc4336p_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int sc4336p_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (sc4336p_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (sc4336p_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, sc4336p_addr_byte + sc4336p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void sc4336p_standby(VI_PIPE ViPipe) +{ + sc4336p_write_register(ViPipe, 0x0100, 0x00); +} + +void sc4336p_restart(VI_PIPE ViPipe) +{ + sc4336p_write_register(ViPipe, 0x0100, 0x00); + delay_ms(20); + sc4336p_write_register(ViPipe, 0x0100, 0x01); +} + +void sc4336p_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastSC4336P[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + sc4336p_write_register(ViPipe, + g_pastSC4336P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastSC4336P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +void sc4336p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = 0; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x6; + break; + case ISP_SNS_FLIP: + val |= 0x60; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x66; + break; + default: + return; + } + + sc4336p_write_register(ViPipe, 0x3221, val); +} + +#define SC4336P_CHIP_ID_HI_ADDR 0x3107 +#define SC4336P_CHIP_ID_LO_ADDR 0x3108 +#define SC4336P_CHIP_ID 0x9c42 + +int sc4336p_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + if (sc4336p_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + delay_ms(5); + + nVal = sc4336p_read_register(ViPipe, SC4336P_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = sc4336p_read_register(ViPipe, SC4336P_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != SC4336P_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + printf("%d\n", ViPipe); + return CVI_SUCCESS; +} + + +void sc4336p_init(VI_PIPE ViPipe) +{ + sc4336p_i2c_init(ViPipe); + + sc4336p_linear_1440p30_init(ViPipe); + + g_pastSC4336P[ViPipe]->bInit = CVI_TRUE; +} + +void sc4336p_exit(VI_PIPE ViPipe) +{ + sc4336p_i2c_exit(ViPipe); +} + +/* 1440P30 and 1440P25 */ +static void sc4336p_linear_1440p30_init(VI_PIPE ViPipe) +{ + sc4336p_write_register(ViPipe, 0x0103, 0x01); + sc4336p_write_register(ViPipe, 0x36e9, 0x80); + sc4336p_write_register(ViPipe, 0x37f9, 0x80); + sc4336p_write_register(ViPipe, 0x301f, 0x01); + sc4336p_write_register(ViPipe, 0x30b8, 0x44); + sc4336p_write_register(ViPipe, 0x3253, 0x10); + sc4336p_write_register(ViPipe, 0x3301, 0x0a); + sc4336p_write_register(ViPipe, 0x3302, 0xff); + sc4336p_write_register(ViPipe, 0x3305, 0x00); + sc4336p_write_register(ViPipe, 0x3306, 0x90); + sc4336p_write_register(ViPipe, 0x3308, 0x08); + sc4336p_write_register(ViPipe, 0x330a, 0x01); + sc4336p_write_register(ViPipe, 0x330b, 0xb0); + sc4336p_write_register(ViPipe, 0x330d, 0xf0); + sc4336p_write_register(ViPipe, 0x3314, 0x14); + sc4336p_write_register(ViPipe, 0x3333, 0x10); + sc4336p_write_register(ViPipe, 0x3334, 0x40); + sc4336p_write_register(ViPipe, 0x335e, 0x06); + sc4336p_write_register(ViPipe, 0x335f, 0x0a); + sc4336p_write_register(ViPipe, 0x3364, 0x5e); + sc4336p_write_register(ViPipe, 0x337d, 0x0e); + sc4336p_write_register(ViPipe, 0x338f, 0x20); + sc4336p_write_register(ViPipe, 0x3390, 0x08); + sc4336p_write_register(ViPipe, 0x3391, 0x09); + sc4336p_write_register(ViPipe, 0x3392, 0x0f); + sc4336p_write_register(ViPipe, 0x3393, 0x18); + sc4336p_write_register(ViPipe, 0x3394, 0x60); + sc4336p_write_register(ViPipe, 0x3395, 0xff); + sc4336p_write_register(ViPipe, 0x3396, 0x08); + sc4336p_write_register(ViPipe, 0x3397, 0x09); + sc4336p_write_register(ViPipe, 0x3398, 0x0f); + sc4336p_write_register(ViPipe, 0x3399, 0x0a); + sc4336p_write_register(ViPipe, 0x339a, 0x18); + sc4336p_write_register(ViPipe, 0x339b, 0x60); + sc4336p_write_register(ViPipe, 0x339c, 0xff); + sc4336p_write_register(ViPipe, 0x33a2, 0x04); + sc4336p_write_register(ViPipe, 0x33ad, 0x0c); + sc4336p_write_register(ViPipe, 0x33b2, 0x40); + sc4336p_write_register(ViPipe, 0x33b3, 0x30); + sc4336p_write_register(ViPipe, 0x33f8, 0x00); + sc4336p_write_register(ViPipe, 0x33f9, 0xb0); + sc4336p_write_register(ViPipe, 0x33fa, 0x00); + sc4336p_write_register(ViPipe, 0x33fb, 0xf8); + sc4336p_write_register(ViPipe, 0x33fc, 0x09); + sc4336p_write_register(ViPipe, 0x33fd, 0x1f); + sc4336p_write_register(ViPipe, 0x349f, 0x03); + sc4336p_write_register(ViPipe, 0x34a6, 0x09); + sc4336p_write_register(ViPipe, 0x34a7, 0x1f); + sc4336p_write_register(ViPipe, 0x34a8, 0x28); + sc4336p_write_register(ViPipe, 0x34a9, 0x28); + sc4336p_write_register(ViPipe, 0x34aa, 0x01); + sc4336p_write_register(ViPipe, 0x34ab, 0xe0); + sc4336p_write_register(ViPipe, 0x34ac, 0x02); + sc4336p_write_register(ViPipe, 0x34ad, 0x28); + sc4336p_write_register(ViPipe, 0x34f8, 0x1f); + sc4336p_write_register(ViPipe, 0x34f9, 0x20); + sc4336p_write_register(ViPipe, 0x3630, 0xc0); + sc4336p_write_register(ViPipe, 0x3631, 0x84); + sc4336p_write_register(ViPipe, 0x3632, 0x54); + sc4336p_write_register(ViPipe, 0x3633, 0x44); + sc4336p_write_register(ViPipe, 0x3637, 0x49); + sc4336p_write_register(ViPipe, 0x363f, 0xc0); + sc4336p_write_register(ViPipe, 0x3641, 0x28); + sc4336p_write_register(ViPipe, 0x3670, 0x56); + sc4336p_write_register(ViPipe, 0x3674, 0xb0); + sc4336p_write_register(ViPipe, 0x3675, 0xa0); + sc4336p_write_register(ViPipe, 0x3676, 0xa0); + sc4336p_write_register(ViPipe, 0x3677, 0x84); + sc4336p_write_register(ViPipe, 0x3678, 0x88); + sc4336p_write_register(ViPipe, 0x3679, 0x8d); + sc4336p_write_register(ViPipe, 0x367c, 0x09); + sc4336p_write_register(ViPipe, 0x367d, 0x0b); + sc4336p_write_register(ViPipe, 0x367e, 0x08); + sc4336p_write_register(ViPipe, 0x367f, 0x0f); + sc4336p_write_register(ViPipe, 0x3696, 0x24); + sc4336p_write_register(ViPipe, 0x3697, 0x34); + sc4336p_write_register(ViPipe, 0x3698, 0x34); + sc4336p_write_register(ViPipe, 0x36a0, 0x0f); + sc4336p_write_register(ViPipe, 0x36a1, 0x1f); + sc4336p_write_register(ViPipe, 0x36b0, 0x81); + sc4336p_write_register(ViPipe, 0x36b1, 0x83); + sc4336p_write_register(ViPipe, 0x36b2, 0x85); + sc4336p_write_register(ViPipe, 0x36b3, 0x8b); + sc4336p_write_register(ViPipe, 0x36b4, 0x09); + sc4336p_write_register(ViPipe, 0x36b5, 0x0b); + sc4336p_write_register(ViPipe, 0x36b6, 0x0f); + sc4336p_write_register(ViPipe, 0x370f, 0x01); + sc4336p_write_register(ViPipe, 0x3722, 0x09); + sc4336p_write_register(ViPipe, 0x3724, 0x21); + sc4336p_write_register(ViPipe, 0x3771, 0x09); + sc4336p_write_register(ViPipe, 0x3772, 0x05); + sc4336p_write_register(ViPipe, 0x3773, 0x05); + sc4336p_write_register(ViPipe, 0x377a, 0x0f); + sc4336p_write_register(ViPipe, 0x377b, 0x1f); + sc4336p_write_register(ViPipe, 0x3905, 0x8c); + sc4336p_write_register(ViPipe, 0x391d, 0x02); + sc4336p_write_register(ViPipe, 0x391f, 0x49); + sc4336p_write_register(ViPipe, 0x3926, 0x21); + sc4336p_write_register(ViPipe, 0x3933, 0x80); + sc4336p_write_register(ViPipe, 0x3934, 0x03); + sc4336p_write_register(ViPipe, 0x3937, 0x7b); + sc4336p_write_register(ViPipe, 0x3939, 0x00); + sc4336p_write_register(ViPipe, 0x393a, 0x00); + sc4336p_write_register(ViPipe, 0x39dc, 0x02); + sc4336p_write_register(ViPipe, 0x3e00, 0x00); + sc4336p_write_register(ViPipe, 0x3e01, 0x5d); + sc4336p_write_register(ViPipe, 0x3e02, 0x40); + sc4336p_write_register(ViPipe, 0x440e, 0x02); + sc4336p_write_register(ViPipe, 0x4509, 0x28); + sc4336p_write_register(ViPipe, 0x450d, 0x32); + sc4336p_write_register(ViPipe, 0x5000, 0x06); + sc4336p_write_register(ViPipe, 0x578d, 0x40); + sc4336p_write_register(ViPipe, 0x5799, 0x46); + sc4336p_write_register(ViPipe, 0x579a, 0x77); + sc4336p_write_register(ViPipe, 0x57d9, 0x46); + sc4336p_write_register(ViPipe, 0x57da, 0x77); + sc4336p_write_register(ViPipe, 0x5ae0, 0xfe); + sc4336p_write_register(ViPipe, 0x5ae1, 0x40); + sc4336p_write_register(ViPipe, 0x5ae2, 0x38); + sc4336p_write_register(ViPipe, 0x5ae3, 0x30); + sc4336p_write_register(ViPipe, 0x5ae4, 0x28); + sc4336p_write_register(ViPipe, 0x5ae5, 0x38); + sc4336p_write_register(ViPipe, 0x5ae6, 0x30); + sc4336p_write_register(ViPipe, 0x5ae7, 0x28); + sc4336p_write_register(ViPipe, 0x5ae8, 0x3f); + sc4336p_write_register(ViPipe, 0x5ae9, 0x34); + sc4336p_write_register(ViPipe, 0x5aea, 0x2c); + sc4336p_write_register(ViPipe, 0x5aeb, 0x3f); + sc4336p_write_register(ViPipe, 0x5aec, 0x34); + sc4336p_write_register(ViPipe, 0x5aed, 0x2c); + sc4336p_write_register(ViPipe, 0x36e9, 0x44); + sc4336p_write_register(ViPipe, 0x37f9, 0x44); + + sc4336p_default_reg_init(ViPipe); + + sc4336p_write_register(ViPipe, 0x0100, 0x01); + + delay_ms(100); + + printf("ViPipe:%d,===SC4336P 1440P 30fps 10bit LINE Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/Makefile b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/Makefile new file mode 100644 index 000000000..a4b7ecc74 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_sc5336_2L.a +TARGET_SO = $(MW_LIB)/libsns_sc5336_2L.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos.c b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos.c new file mode 100644 index 000000000..9d1077905 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos.c @@ -0,0 +1,1062 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "sc5336_2L_cmos_ex.h" +#include "sc5336_2L_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define SC5336_2L_ID 500 +#define SENSOR_SC5336_2L_WIDTH 2880 +#define SENSOR_SC5336_2L_HEIGHT 1620 +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastSC5336_2L[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define SC5336_2L_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastSC5336_2L[dev]) +#define SC5336_2L_SENSOR_SET_CTX(dev, pstCtx) (g_pastSC5336_2L[dev] = pstCtx) +#define SC5336_2L_SENSOR_RESET_CTX(dev) (g_pastSC5336_2L[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunSC5336_2L_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16SC5336_2L_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16SC5336_2L_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +SC5336_2L_STATE_S g_astSC5336_2L_State[VI_MAX_PIPE_NUM] = {{0} }; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = { + [0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE +}; + +static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****SC5336_2L Lines Range*****/ +#define SC5336_2L_FULL_LINES_MAX (0x7FFF) + +/*****SC5336_2L Register Address*****/ +#define SC5336_2L_SHS1_0_ADDR 0x3E00 +#define SC5336_2L_SHS1_1_ADDR 0x3E01 +#define SC5336_2L_SHS1_2_ADDR 0x3E02 +#define SC5336_2L_AGAIN_0_ADDR 0x3E09 +#define SC5336_2L_DGAIN_0_ADDR 0x3E06 +#define SC5336_2L_VMAX_ADDR 0x320E +#define SC5336_2L_TABLE_END 0xFFFF + +#define SC5336_2L_RES_IS_1620P(w, h) ((w) <= 2880 && (h) <= 1620) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); +#if 0 + memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S)); +#endif + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = SC5336_2L_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + default: + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].f32MaxFps; + pstAeSnsDft->f32MinFps = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].stAgain[0].u32Max; + pstAeSnsDft->u32MinAgain = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].stAgain[0].u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].stDgain[0].u32Max; + pstAeSnsDft->u32MinDgain = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].stDgain[0].u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 4; + pstAeSnsDft->u32MinIntTime = 3; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + case WDR_MODE_2To1_LINE: + break; + } + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case SC5336_2L_MODE_1620P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > SC5336_2L_FULL_LINES_MAX) ? SC5336_2L_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_ADDR].u32Data = ((u32VMAX & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_ADDR].u32Data = (u32VMAX & 0xFF); + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 4; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + CVI_U32 u32TmpIntTime = u32IntTime[0]; + CVI_U32 maxExp = pstSnsState->au32FL[0] - 4; + + /* linear exposure reg range: + * min : 2 + * max : vts - 4 + * step : 1 + */ + u32TmpIntTime = (u32TmpIntTime > maxExp) ? maxExp : u32TmpIntTime; + if (u32TmpIntTime < 2) + u32TmpIntTime = 2; + u32IntTime[0] = u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_ADDR].u32Data = ((u32TmpIntTime & 0xF000) >> 12); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_ADDR].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_2_ADDR].u32Data = (u32TmpIntTime & 0xF) << 4; + + return CVI_SUCCESS; + +} + +struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +}; + +static struct gain_tbl_info_s AgainInfo[] = { + { + .gainMax = 2016, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x08, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 8064, + .idxBase = 64, + .regGain = 0x09, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 16128, + .idxBase = 96, + .regGain = 0x0b, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 32256, + .idxBase = 128, + .regGain = 0x0F, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 32768, + .idxBase = 160, + .regGain = 0x1F, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, +}; + +static CVI_U32 Again_table[] = { + 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, + 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, + 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, + 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, + + 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, + 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, + 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, + 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, + + 4096, 4224, 4352, 4480, 4608, 4736, 4864, 4992, + 5120, 5248, 5376, 5504, 5632, 5760, 5888, 6016, + 6144, 6272, 6400, 6528, 6656, 6784, 6912, 7040, + 7168, 7296, 7424, 7552, 7680, 7808, 7936, 8064, + + 8192, 8448, 8704, 8960, 9216, 9472, 9728, 9984, + 10240, 10496, 10752, 11008, 11264, 11520, 11776, 12032, + 12288, 12544, 12800, 13056, 13312, 13568, 13824, 14080, + 14336, 14592, 14848, 15104, 15360, 15616, 15872, 16128, + + 16384, 16896, 17408, 17920, 18432, 18944, 19456, 19968, + 20480, 20992, 21504, 22016, 22528, 23040, 23552, 24064, + 24576, 25088, 25600, 26112, 26624, 27136, 27648, 28160, + 28672, 29184, 29696, 30208, 30720, 31232, 31744, 32256, + + 32768, +}; + +static struct gain_tbl_info_s DgainInfo[] = { + { + .gainMax = 2016, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x01, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 8064, + .idxBase = 64, + .regGain = 0x03, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 16128, + .idxBase = 96, + .regGain = 0x07, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, +}; + +static CVI_U32 Dgain_table[] = { + 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, + 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, + 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, + 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, + + 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, + 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, + 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, + 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, + + 4096, 4224, 4352, 4480, 4608, 4736, 4864, 4992, + 5120, 5248, 5376, 5504, 5632, 5760, 5888, 6016, + 6144, 6272, 6400, 6528, 6656, 6784, 6912, 7040, + 7168, 7296, 7424, 7552, 7680, 7808, 7936, 8064, + + 8192, 8448, 8704, 8960, 9216, 9472, 9728, 9984, + 10240, 10496, 10752, 11008, 11264, 11520, 11776, 12032, + 12288, 12544, 12800, 13056, 13312, 13568, 13824, 14080, + 14336, 14592, 14848, 15104, 15360, 15616, 15872, 16128, +}; + +CVI_U32 AtableSize = sizeof(Again_table) / sizeof(CVI_U32); +CVI_U32 DtableSize = sizeof(Dgain_table) / sizeof(CVI_U32); + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 i; + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= Again_table[AtableSize - 1]) { + *pu32AgainLin = Again_table[AtableSize - 1]; + *pu32AgainDb = AtableSize - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < AtableSize; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 i; + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[DtableSize - 1]) { + *pu32DgainLin = Dgain_table[DtableSize - 1]; + *pu32DgainDb = DtableSize - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < DtableSize; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + + /* find Again register setting. */ + tbl_num = sizeof(AgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &AgainInfo[i]; + + if (u32Again >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_0_ADDR].u32Data = (info->regGain & 0xFF); + u32Again = info->regGainFineBase + (u32Again - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_1_ADDR].u32Data = (u32Again & 0xFF); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_0_ADDR].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_1_ADDR].u32Data = (u32Dgain & 0xFF); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio, + CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime) +{ + CVI_U32 u32IntTimeMaxTmp = 0; + CVI_U32 u32ShortTimeMinLimit = 5; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32MaxSexp = 2 * g_astSC5336_2L_State[ViPipe].u32Sexp_MAX - 14; + + (void) u16ManRatioEnable; + + CMOS_CHECK_POINTER(au32Ratio); + CMOS_CHECK_POINTER(au32IntTimeMax); + CMOS_CHECK_POINTER(au32IntTimeMin); + CMOS_CHECK_POINTER(pu32LFMaxIntTime); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + /* short exposure reg range: + * min : 5 + * max : 2 * (max sexp - 7) + * step : 4 + * long exposure reg range: + * min : 5 + * max : 2 * (vts - max sexp - 9) + * step : 4 + */ + u32IntTimeMaxTmp = ((2 * pstSnsState->au32FL[0] - 16) * 0x40) / (au32Ratio[0] + 0x40); + u32IntTimeMaxTmp = (u32IntTimeMaxTmp > u32MaxSexp) ? u32MaxSexp : u32IntTimeMaxTmp; + u32IntTimeMaxTmp = (u32IntTimeMaxTmp < u32ShortTimeMinLimit) ? u32ShortTimeMinLimit : u32IntTimeMaxTmp; + + if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) { + au32IntTimeMax[0] = u32IntTimeMaxTmp; + au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6; + au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6; + au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6; + au32IntTimeMin[0] = u32ShortTimeMinLimit; + au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6; + au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6; + au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6; + syslog(LOG_DEBUG, "ViPipe = %d ratio = %d, (%d, %d)\n", ViPipe, au32Ratio[0], + u32IntTimeMaxTmp, u32ShortTimeMinLimit); + } + + return CVI_SUCCESS; +} + +/* Only used in LINE_WDR mode */ +static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr) +{ + CMOS_CHECK_POINTER(pstAeFSWDRAttr); + + genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode; + gu32MaxTimeGetCnt[ViPipe] = 0; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + memcpy(pstDef->stNoiseCalibration.CalibrationCoef, + &g_stIspNoiseCalibratio, sizeof(ISP_CMOS_NOISE_CALIBRATION_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const SC5336_2L_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astSC5336_2L_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + + case WDR_MODE_2To1_LINE: + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunSC5336_2L_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = SC5336_2l_i2c_addr; + pstI2c_data[i].u32AddrByteNum = SC5336_2l_addr_byte; + pstI2c_data[i].u32DataByteNum = SC5336_2l_data_byte; + } + + //Linear Mode Regs + pstI2c_data[LINEAR_SHS1_0_ADDR].u32RegAddr = SC5336_2L_SHS1_0_ADDR; + pstI2c_data[LINEAR_SHS1_1_ADDR].u32RegAddr = SC5336_2L_SHS1_1_ADDR; + pstI2c_data[LINEAR_SHS1_2_ADDR].u32RegAddr = SC5336_2L_SHS1_2_ADDR; + pstI2c_data[LINEAR_AGAIN_0_ADDR].u32RegAddr = SC5336_2L_AGAIN_0_ADDR; + pstI2c_data[LINEAR_AGAIN_1_ADDR].u32RegAddr = SC5336_2L_DGAIN_0_ADDR + 1; + pstI2c_data[LINEAR_DGAIN_0_ADDR].u32RegAddr = SC5336_2L_DGAIN_0_ADDR; + pstI2c_data[LINEAR_DGAIN_1_ADDR].u32RegAddr = SC5336_2L_DGAIN_0_ADDR + 1; + pstI2c_data[LINEAR_VMAX_0_ADDR].u32RegAddr = SC5336_2L_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1_ADDR].u32RegAddr = SC5336_2L_VMAX_ADDR + 1; + + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (SC5336_2L_RES_IS_1620P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = SC5336_2L_MODE_1620P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const SC5336_2L_MODE_S *pstMode = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = SC5336_2L_MODE_1620P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astSC5336_2L_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &SC5336_2l_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &SC5336_2l_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = SC5336_2l_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = SC5336_2l_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 SC5336_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunSC5336_2L_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + SC5336_2L_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + SC5336_2L_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = SC5336_2L_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, SC5336_2L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, SC5336_2L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, SC5336_2L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16SC5336_2L_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16SC5336_2L_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsSC5336_2L_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = SC5336_2l_standby, + .pfnRestart = SC5336_2l_restart, + .pfnMirrorFlip = SC5336_2l_mirror_flip, + .pfnWriteReg = SC5336_2l_write_register, + .pfnReadReg = SC5336_2l_read_register, + .pfnSetBusInfo = SC5336_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = SC5336_2l_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos_ex.h new file mode 100644 index 000000000..2464599f3 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos_ex.h @@ -0,0 +1,85 @@ +#ifndef __SC5336_2L_CMOS_EX_H_ +#define __SC5336_2L_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum SC5336_2l_linear_regs_e { + LINEAR_SHS1_0_ADDR, + LINEAR_SHS1_1_ADDR, + LINEAR_SHS1_2_ADDR, + LINEAR_AGAIN_0_ADDR, + LINEAR_AGAIN_1_ADDR, + LINEAR_DGAIN_0_ADDR, + LINEAR_DGAIN_1_ADDR, + LINEAR_VMAX_0_ADDR, + LINEAR_VMAX_1_ADDR, + LINEAR_REGS_NUM +}; + +typedef enum _SC5336_2L_MODE_E { + SC5336_2L_MODE_1620P30 = 0, + SC5336_2L_MODE_LINEAR_NUM, + SC5336_2L_MODE_NUM +} SC5336_2L_MODE_E; + +typedef struct _SC5336_2L_STATE_S { + CVI_U32 u32Sexp_MAX; /* (2*{16’h3e23,16’h3e24} – 'd10)/2 */ +} SC5336_2L_STATE_S; + +typedef struct _SC5336_2L_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_LARGE_S stAgain[2]; + SNS_ATTR_LARGE_S stDgain[2]; + CVI_U16 u16SexpMaxReg; /* {16’h3e23,16’h3e24} */ + char name[64]; +} SC5336_2L_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastSC5336_2L[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunSC5336_2L_BusInfo[]; +extern CVI_U16 g_au16SC5336_2L_GainMode[]; +extern CVI_U16 g_au16SC5336_2L_L2SMode[]; +extern const CVI_U8 SC5336_2l_i2c_addr; +extern const CVI_U32 SC5336_2l_addr_byte; +extern const CVI_U32 SC5336_2l_data_byte; +extern void SC5336_2l_init(VI_PIPE ViPipe); +extern void SC5336_2l_exit(VI_PIPE ViPipe); +extern void SC5336_2l_standby(VI_PIPE ViPipe); +extern void SC5336_2l_restart(VI_PIPE ViPipe); +extern int SC5336_2l_write_register(VI_PIPE ViPipe, int addr, int data); +extern int SC5336_2l_read_register(VI_PIPE ViPipe, int addr); +extern void SC5336_2l_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int SC5336_2l_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC5336_2L_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos_param.h new file mode 100644 index 000000000..4bfdcb017 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_cmos_param.h @@ -0,0 +1,226 @@ +#ifndef __SC5336_2L_CMOS_PARAM_H_ +#define __SC5336_2L_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc5336_2L_cmos_ex.h" + +static const SC5336_2L_MODE_S g_astSC5336_2L_mode[SC5336_2L_MODE_NUM] = { + [SC5336_2L_MODE_1620P30] = { + .name = "1620p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 2880, + .u32Height = 1620, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2880, + .u32Height = 1620, + }, + .stMaxSize = { + .u32Width = 2880, + .u32Height = 1620, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 1.65, /* 1800 * 30 / 0x7FFF*/ + .u32HtsDef = 2560, /* NA */ + .u32VtsDef = 1800, + .stExp[0] = { + .u16Min = 2, + .u16Max = 1796,/* vts-4 */ + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u32Min = 1024, + .u32Max = 32768, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain[0] = { + .u32Min = 1024, + .u32Max = 16128, + .u32Def = 1024, + .u32Step = 1, + }, + }, +}; + +static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = { + { //iso 100 + {0.02792946062982082367, 3.36534714698791503906}, //B: slope, intercept + {0.02071751467883586884, 5.34583568572998046875}, //Gb: slope, intercept + {0.02110148966312408447, 5.02954530715942382813}, //Gr: slope, intercept + {0.02168512716889381409, 4.89776754379272460938}, //R: slope, intercept + }, + { //iso 200 + {0.03194080293178558350, 5.61192893981933593750}, //B: slope, intercept + {0.02428408525884151459, 7.94834280014038085938}, //Gb: slope, intercept + {0.02499442733824253082, 7.72430133819580078125}, //Gr: slope, intercept + {0.02584112435579299927, 7.20574426651000976563}, //R: slope, intercept + }, + { //iso 400 + {0.04612467437982559204, 6.88752269744873046875}, //B: slope, intercept + {0.03022909909486770630, 11.05101776123046875000}, //Gb: slope, intercept + {0.03175539523363113403, 10.60332489013671875000}, //Gr: slope, intercept + {0.03522306308150291443, 9.36425399780273437500}, //R: slope, intercept + }, + { //iso 800 + {0.06092500314116477966, 9.79670524597167968750}, //B: slope, intercept + {0.03984217345714569092, 15.30182266235351562500}, //Gb: slope, intercept + {0.04019560664892196655, 14.93132972717285156250}, //Gr: slope, intercept + {0.04470816254615783691, 13.26843166351318359375}, //R: slope, intercept + }, + { //iso 1600 + {0.08295634388923645020, 14.20334625244140625000}, //B: slope, intercept + {0.05075264349579811096, 20.99221038818359375000}, //Gb: slope, intercept + {0.05426201224327087402, 20.08068656921386718750}, //Gr: slope, intercept + {0.05945669487118721008, 19.02898788452148437500}, //R: slope, intercept + }, + { //iso 3200 + {0.09782519936561584473, 21.84967994689941406250}, //B: slope, intercept + {0.06690908223390579224, 26.53993988037109375000}, //Gb: slope, intercept + {0.06954573839902877808, 25.74129104614257812500}, //Gr: slope, intercept + {0.09061723947525024414, 22.98998260498046875000}, //R: slope, intercept + }, + { //iso 6400 + {0.14311420917510986328, 28.96467971801757812500}, //B: slope, intercept + {0.08148498833179473877, 37.93062591552734375000}, //Gb: slope, intercept + {0.08273542672395706177, 38.37096405029296875000}, //Gr: slope, intercept + {0.12093253433704376221, 33.31475067138671875000}, //R: slope, intercept + }, + { //iso 12800 + {0.17958122491836547852, 43.49506759643554687500}, //B: slope, intercept + {0.09839969873428344727, 55.43268966674804687500}, //Gb: slope, intercept + {0.10201884806156158447, 52.97607040405273437500}, //Gr: slope, intercept + {0.15302789211273193359, 47.54779434204101562500}, //R: slope, intercept + }, + { //iso 25600 + {0.25833165645599365234, 56.96470642089843750000}, //B: slope, intercept + {0.13260601460933685303, 74.69016265869140625000}, //Gb: slope, intercept + {0.14035490155220031738, 75.44366455078125000000}, //Gr: slope, intercept + {0.23465165495872497559, 60.52228164672851562500}, //R: slope, intercept + }, + { //iso 51200 + {0.37595292925834655762, 78.54853057861328125000}, //B: slope, intercept + {0.21475413441658020020, 102.12300872802734375000}, //Gb: slope, intercept + {0.20840260386466979980, 103.65763854980468750000}, //Gr: slope, intercept + {0.34428051114082336426, 87.83551025390625000000}, //R: slope, intercept + }, + { //iso 102400 + {0.51122575998306274414, 113.49224090576171875000}, //B: slope, intercept + {0.29245173931121826172, 154.26939392089843750000}, //Gb: slope, intercept + {0.31501635909080505371, 148.29017639160156250000}, //Gr: slope, intercept + {0.47034618258476257324, 124.06208038330078125000}, //R: slope, intercept + }, + { //iso 204800 + {0.67213481664657592773, 134.71751403808593750000}, //B: slope, intercept + {0.40368056297302246094, 189.80801391601562500000}, //Gb: slope, intercept + {0.43581819534301757813, 186.44682312011718750000}, //Gr: slope, intercept + {0.60127359628677368164, 160.66384887695312500000}, //R: slope, intercept + }, + { //iso 409600 + {0.81907004117965698242, 103.53753662109375000000}, //B: slope, intercept + {0.56758689880371093750, 134.64016723632812500000}, //Gb: slope, intercept + {0.60227775573730468750, 125.39395904541015625000}, //Gr: slope, intercept + {0.76318585872650146484, 111.18676757812500000000}, //R: slope, intercept + }, + { //iso 819200 + {0.81907004117965698242, 103.53753662109375000000}, //B: slope, intercept + {0.56758689880371093750, 134.64016723632812500000}, //Gb: slope, intercept + {0.60227775573730468750, 125.39395904541015625000}, //Gr: slope, intercept + {0.76318585872650146484, 111.18676757812500000000}, //R: slope, intercept + }, + { //iso 1638400 + {0.81907004117965698242, 103.53753662109375000000}, //B: slope, intercept + {0.56758689880371093750, 134.64016723632812500000}, //Gb: slope, intercept + {0.60227775573730468750, 125.39395904541015625000}, //Gr: slope, intercept + {0.76318585872650146484, 111.18676757812500000000}, //R: slope, intercept + }, + { //iso 3276800 + {0.81907004117965698242, 103.53753662109375000000}, //B: slope, intercept + {0.56758689880371093750, 134.64016723632812500000}, //Gb: slope, intercept + {0.60227775573730468750, 125.39395904541015625000}, //Gr: slope, intercept + {0.76318585872650146484, 111.18676757812500000000}, //R: slope, intercept + }, +} }; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {256, 256, 256, 256, 0, 0, 0, 0, +#ifdef ARCH_CV182X + 1092, 1092, 1092, 1092 +#endif + }, + + .stAuto = { + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, +#endif + }, + }, +}; + +struct combo_dev_attr_s SC5336_2l_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {0, 1, 2, -1, -1}, + .pn_swap = {0, 0, 0, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_VC, + .dphy = { + .enable = 1, + .hs_settle = 14, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC5336_2L_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_sensor_ctl.c new file mode 100644 index 000000000..3dcd1dc89 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/sms_sc5336_2L/sc5336_2L_sensor_ctl.c @@ -0,0 +1,463 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc5336_2L_cmos_ex.h" + +static void SC5336_2l_linear_1620p30_init(VI_PIPE ViPipe); + +const CVI_U8 SC5336_2l_i2c_addr = 0x30; /* I2C Address of SC5336_2L */ +const CVI_U32 SC5336_2l_addr_byte = 2; +const CVI_U32 SC5336_2l_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int SC5336_2l_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunSC5336_2L_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, SC5336_2l_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int SC5336_2l_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int SC5336_2l_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (SC5336_2l_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, SC5336_2l_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, SC5336_2l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (SC5336_2l_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int SC5336_2l_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (SC5336_2l_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (SC5336_2l_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, SC5336_2l_addr_byte + SC5336_2l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void SC5336_2l_prog(VI_PIPE ViPipe, int *rom) +{ + int i = 0; + + while (1) { + int lookup = rom[i++]; + int addr = (lookup >> 16) & 0xFFFF; + int data = lookup & 0xFFFF; + + if (addr == 0xFFFE) + delay_ms(data); + else if (addr != 0xFFFF) + SC5336_2l_write_register(ViPipe, addr, data); + } +} + +void SC5336_2l_standby(VI_PIPE ViPipe) +{ + SC5336_2l_write_register(ViPipe, 0x0100, 0x00); +} + +void SC5336_2l_restart(VI_PIPE ViPipe) +{ + SC5336_2l_write_register(ViPipe, 0x0100, 0x00); + delay_ms(20); + SC5336_2l_write_register(ViPipe, 0x0100, 0x01); +} + +void SC5336_2l_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastSC5336_2L[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + SC5336_2l_write_register(ViPipe, + g_pastSC5336_2L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastSC5336_2L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +#define SC5336_2L_CHIP_ID_HI_ADDR 0x3107 +#define SC5336_2L_CHIP_ID_LO_ADDR 0x3108 +#define SC5336_2L_CHIP_ID 0xce50 + +void SC5336_2l_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = 0; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x6; + break; + case ISP_SNS_FLIP: + val |= 0x60; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x66; + break; + default: + return; + } + + SC5336_2l_write_register(ViPipe, 0x3221, val); +} + +int SC5336_2l_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + usleep(4*1000); + if (SC5336_2l_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = SC5336_2l_read_register(ViPipe, SC5336_2L_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = SC5336_2l_read_register(ViPipe, SC5336_2L_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != SC5336_2L_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void SC5336_2l_init(VI_PIPE ViPipe) +{ + WDR_MODE_E enWDRMode; + CVI_BOOL bInit; + + bInit = g_pastSC5336_2L[ViPipe]->bInit; + enWDRMode = g_pastSC5336_2L[ViPipe]->enWDRMode; + + SC5336_2l_i2c_init(ViPipe); + + /* When sensor first init, config all registers */ + if (bInit == CVI_FALSE) { + if (enWDRMode == WDR_MODE_2To1_LINE) { + CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n"); + } else { + SC5336_2l_linear_1620p30_init(ViPipe); + } + } + /* When sensor switch mode(linear<->WDR or resolution), config different registers(if possible) */ + else { + if (enWDRMode == WDR_MODE_2To1_LINE) { + CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n"); + } else { + SC5336_2l_linear_1620p30_init(ViPipe); + } + } + g_pastSC5336_2L[ViPipe]->bInit = CVI_TRUE; +} + +void SC5336_2l_exit(VI_PIPE ViPipe) +{ + SC5336_2l_i2c_exit(ViPipe); +} + +/* 1620P30 and 1620P25 */ +static void SC5336_2l_linear_1620p30_init(VI_PIPE ViPipe) +{ + SC5336_2l_write_register(ViPipe, 0x0103, 0x01); + SC5336_2l_write_register(ViPipe, 0x36e9, 0x80); + SC5336_2l_write_register(ViPipe, 0x37f9, 0x80); + SC5336_2l_write_register(ViPipe, 0x301f, 0x01); + SC5336_2l_write_register(ViPipe, 0x320e, 0x07); + SC5336_2l_write_register(ViPipe, 0x320f, 0x08); + SC5336_2l_write_register(ViPipe, 0x3213, 0x04); + SC5336_2l_write_register(ViPipe, 0x3241, 0x00); + SC5336_2l_write_register(ViPipe, 0x3243, 0x01); + SC5336_2l_write_register(ViPipe, 0x3248, 0x02); + SC5336_2l_write_register(ViPipe, 0x3249, 0x0b); + SC5336_2l_write_register(ViPipe, 0x3253, 0x10); + SC5336_2l_write_register(ViPipe, 0x3258, 0x0c); + SC5336_2l_write_register(ViPipe, 0x3301, 0x0a); + SC5336_2l_write_register(ViPipe, 0x3305, 0x00); + SC5336_2l_write_register(ViPipe, 0x3306, 0x58); + SC5336_2l_write_register(ViPipe, 0x3308, 0x08); + SC5336_2l_write_register(ViPipe, 0x3309, 0xb0); + SC5336_2l_write_register(ViPipe, 0x330a, 0x00); + SC5336_2l_write_register(ViPipe, 0x330b, 0xc8); + SC5336_2l_write_register(ViPipe, 0x3314, 0x14); + SC5336_2l_write_register(ViPipe, 0x331f, 0xa1); + SC5336_2l_write_register(ViPipe, 0x3321, 0x10); + SC5336_2l_write_register(ViPipe, 0x3327, 0x14); + SC5336_2l_write_register(ViPipe, 0x3328, 0x0b); + SC5336_2l_write_register(ViPipe, 0x3329, 0x0e); + SC5336_2l_write_register(ViPipe, 0x3333, 0x10); + SC5336_2l_write_register(ViPipe, 0x3334, 0x40); + SC5336_2l_write_register(ViPipe, 0x3356, 0x10); + SC5336_2l_write_register(ViPipe, 0x3364, 0x5e); + SC5336_2l_write_register(ViPipe, 0x3390, 0x09); + SC5336_2l_write_register(ViPipe, 0x3391, 0x0b); + SC5336_2l_write_register(ViPipe, 0x3392, 0x0f); + SC5336_2l_write_register(ViPipe, 0x3393, 0x10); + SC5336_2l_write_register(ViPipe, 0x3394, 0x18); + SC5336_2l_write_register(ViPipe, 0x3395, 0x98); + SC5336_2l_write_register(ViPipe, 0x3396, 0x08); + SC5336_2l_write_register(ViPipe, 0x3397, 0x09); + SC5336_2l_write_register(ViPipe, 0x3398, 0x0f); + SC5336_2l_write_register(ViPipe, 0x3399, 0x0a); + SC5336_2l_write_register(ViPipe, 0x339a, 0x18); + SC5336_2l_write_register(ViPipe, 0x339b, 0x60); + SC5336_2l_write_register(ViPipe, 0x339c, 0xff); + SC5336_2l_write_register(ViPipe, 0x33ad, 0x0c); + SC5336_2l_write_register(ViPipe, 0x33ae, 0x68); + SC5336_2l_write_register(ViPipe, 0x33b2, 0x48); + SC5336_2l_write_register(ViPipe, 0x33b3, 0x28); + SC5336_2l_write_register(ViPipe, 0x33f8, 0x00); + SC5336_2l_write_register(ViPipe, 0x33f9, 0x70); + SC5336_2l_write_register(ViPipe, 0x33fa, 0x00); + SC5336_2l_write_register(ViPipe, 0x33fb, 0x90); + SC5336_2l_write_register(ViPipe, 0x33fc, 0x0b); + SC5336_2l_write_register(ViPipe, 0x33fd, 0x1f); + SC5336_2l_write_register(ViPipe, 0x349f, 0x03); + SC5336_2l_write_register(ViPipe, 0x34a6, 0x0b); + SC5336_2l_write_register(ViPipe, 0x34a7, 0x1f); + SC5336_2l_write_register(ViPipe, 0x34a8, 0x18); + SC5336_2l_write_register(ViPipe, 0x34a9, 0x08); + SC5336_2l_write_register(ViPipe, 0x34aa, 0x00); + SC5336_2l_write_register(ViPipe, 0x34ab, 0xe8); + SC5336_2l_write_register(ViPipe, 0x34ac, 0x01); + SC5336_2l_write_register(ViPipe, 0x34ad, 0x08); + SC5336_2l_write_register(ViPipe, 0x34f8, 0x1f); + SC5336_2l_write_register(ViPipe, 0x34f9, 0x08); + SC5336_2l_write_register(ViPipe, 0x3630, 0xc0); + SC5336_2l_write_register(ViPipe, 0x3631, 0x83); + SC5336_2l_write_register(ViPipe, 0x3632, 0x54); + SC5336_2l_write_register(ViPipe, 0x3633, 0x33); + SC5336_2l_write_register(ViPipe, 0x3641, 0x20); + SC5336_2l_write_register(ViPipe, 0x3670, 0x56); + SC5336_2l_write_register(ViPipe, 0x3674, 0xc0); + SC5336_2l_write_register(ViPipe, 0x3675, 0xa0); + SC5336_2l_write_register(ViPipe, 0x3676, 0xa0); + SC5336_2l_write_register(ViPipe, 0x3677, 0x83); + SC5336_2l_write_register(ViPipe, 0x3678, 0x86); + SC5336_2l_write_register(ViPipe, 0x3679, 0x8a); + SC5336_2l_write_register(ViPipe, 0x367c, 0x08); + SC5336_2l_write_register(ViPipe, 0x367d, 0x0f); + SC5336_2l_write_register(ViPipe, 0x367e, 0x08); + SC5336_2l_write_register(ViPipe, 0x367f, 0x0f); + SC5336_2l_write_register(ViPipe, 0x3696, 0x23); + SC5336_2l_write_register(ViPipe, 0x3697, 0x33); + SC5336_2l_write_register(ViPipe, 0x3698, 0x43); + SC5336_2l_write_register(ViPipe, 0x36a0, 0x09); + SC5336_2l_write_register(ViPipe, 0x36a1, 0x0f); + SC5336_2l_write_register(ViPipe, 0x36b0, 0x88); + SC5336_2l_write_register(ViPipe, 0x36b1, 0x92); + SC5336_2l_write_register(ViPipe, 0x36b2, 0xa4); + SC5336_2l_write_register(ViPipe, 0x36b3, 0xc7); + SC5336_2l_write_register(ViPipe, 0x36b4, 0x09); + SC5336_2l_write_register(ViPipe, 0x36b5, 0x0b); + SC5336_2l_write_register(ViPipe, 0x36b6, 0x0f); + SC5336_2l_write_register(ViPipe, 0x36ea, 0x0c); + SC5336_2l_write_register(ViPipe, 0x370f, 0x01); + SC5336_2l_write_register(ViPipe, 0x3721, 0x6c); + SC5336_2l_write_register(ViPipe, 0x3722, 0x89); + SC5336_2l_write_register(ViPipe, 0x3724, 0x21); + SC5336_2l_write_register(ViPipe, 0x3725, 0xb4); + SC5336_2l_write_register(ViPipe, 0x3727, 0x14); + SC5336_2l_write_register(ViPipe, 0x3771, 0x89); + SC5336_2l_write_register(ViPipe, 0x3772, 0x85); + SC5336_2l_write_register(ViPipe, 0x3773, 0x85); + SC5336_2l_write_register(ViPipe, 0x377a, 0x0b); + SC5336_2l_write_register(ViPipe, 0x377b, 0x1f); + SC5336_2l_write_register(ViPipe, 0x37fa, 0x0c); + SC5336_2l_write_register(ViPipe, 0x3901, 0x00); + SC5336_2l_write_register(ViPipe, 0x3904, 0x04); + SC5336_2l_write_register(ViPipe, 0x3905, 0x8c); + SC5336_2l_write_register(ViPipe, 0x391d, 0x04); + SC5336_2l_write_register(ViPipe, 0x391f, 0x49); + SC5336_2l_write_register(ViPipe, 0x3926, 0x21); + SC5336_2l_write_register(ViPipe, 0x3933, 0x80); + SC5336_2l_write_register(ViPipe, 0x3934, 0x0a); + SC5336_2l_write_register(ViPipe, 0x3935, 0x00); + SC5336_2l_write_register(ViPipe, 0x3936, 0xff); + SC5336_2l_write_register(ViPipe, 0x3937, 0x75); + SC5336_2l_write_register(ViPipe, 0x3938, 0x74); + SC5336_2l_write_register(ViPipe, 0x393c, 0x1e); + SC5336_2l_write_register(ViPipe, 0x39dc, 0x02); + SC5336_2l_write_register(ViPipe, 0x3e00, 0x00); + SC5336_2l_write_register(ViPipe, 0x3e01, 0x70); + SC5336_2l_write_register(ViPipe, 0x3e02, 0x00); + SC5336_2l_write_register(ViPipe, 0x3e09, 0x00); + SC5336_2l_write_register(ViPipe, 0x440d, 0x10); + SC5336_2l_write_register(ViPipe, 0x440e, 0x02); + SC5336_2l_write_register(ViPipe, 0x450d, 0x18); + SC5336_2l_write_register(ViPipe, 0x4819, 0x0b); + SC5336_2l_write_register(ViPipe, 0x481b, 0x06); + SC5336_2l_write_register(ViPipe, 0x481d, 0x17); + SC5336_2l_write_register(ViPipe, 0x481f, 0x05); + SC5336_2l_write_register(ViPipe, 0x4821, 0x0b); + SC5336_2l_write_register(ViPipe, 0x4823, 0x06); + SC5336_2l_write_register(ViPipe, 0x4825, 0x05); + SC5336_2l_write_register(ViPipe, 0x4827, 0x05); + SC5336_2l_write_register(ViPipe, 0x4829, 0x09); + SC5336_2l_write_register(ViPipe, 0x5780, 0x66); + SC5336_2l_write_register(ViPipe, 0x5787, 0x08); + SC5336_2l_write_register(ViPipe, 0x5788, 0x03); + SC5336_2l_write_register(ViPipe, 0x5789, 0x00); + SC5336_2l_write_register(ViPipe, 0x578a, 0x08); + SC5336_2l_write_register(ViPipe, 0x578b, 0x03); + SC5336_2l_write_register(ViPipe, 0x578c, 0x00); + SC5336_2l_write_register(ViPipe, 0x578d, 0x40); + SC5336_2l_write_register(ViPipe, 0x5790, 0x08); + SC5336_2l_write_register(ViPipe, 0x5791, 0x04); + SC5336_2l_write_register(ViPipe, 0x5792, 0x01); + SC5336_2l_write_register(ViPipe, 0x5793, 0x08); + SC5336_2l_write_register(ViPipe, 0x5794, 0x04); + SC5336_2l_write_register(ViPipe, 0x5795, 0x01); + SC5336_2l_write_register(ViPipe, 0x5799, 0x46); + SC5336_2l_write_register(ViPipe, 0x57aa, 0x2a); + SC5336_2l_write_register(ViPipe, 0x5ae0, 0xfe); + SC5336_2l_write_register(ViPipe, 0x5ae1, 0x40); + SC5336_2l_write_register(ViPipe, 0x5ae2, 0x38); + SC5336_2l_write_register(ViPipe, 0x5ae3, 0x30); + SC5336_2l_write_register(ViPipe, 0x5ae4, 0x0c); + SC5336_2l_write_register(ViPipe, 0x5ae5, 0x38); + SC5336_2l_write_register(ViPipe, 0x5ae6, 0x30); + SC5336_2l_write_register(ViPipe, 0x5ae7, 0x28); + SC5336_2l_write_register(ViPipe, 0x5ae8, 0x3f); + SC5336_2l_write_register(ViPipe, 0x5ae9, 0x34); + SC5336_2l_write_register(ViPipe, 0x5aea, 0x2c); + SC5336_2l_write_register(ViPipe, 0x5aeb, 0x3f); + SC5336_2l_write_register(ViPipe, 0x5aec, 0x34); + SC5336_2l_write_register(ViPipe, 0x5aed, 0x2c); + SC5336_2l_write_register(ViPipe, 0x36e9, 0x44); + SC5336_2l_write_register(ViPipe, 0x37f9, 0x44); + if (0x00 == SC5336_2l_read_register(ViPipe, 0x3040)) { + SC5336_2l_write_register(ViPipe, 0x3258, 0x0c); + SC5336_2l_write_register(ViPipe, 0x3249, 0x0b); + SC5336_2l_write_register(ViPipe, 0x3934, 0x0a); + SC5336_2l_write_register(ViPipe, 0x3935, 0x00); + SC5336_2l_write_register(ViPipe, 0x3937, 0x75); + } else if (0x03 == SC5336_2l_read_register(ViPipe, 0x3040)) { + SC5336_2l_write_register(ViPipe, 0x3258, 0x08); + SC5336_2l_write_register(ViPipe, 0x3249, 0x07); + SC5336_2l_write_register(ViPipe, 0x3934, 0x05); + SC5336_2l_write_register(ViPipe, 0x3935, 0x07); + SC5336_2l_write_register(ViPipe, 0x3937, 0x74); + } + SC5336_2l_write_register(ViPipe, 0x0100, 0x01); + SC5336_2l_default_reg_init(ViPipe); + + SC5336_2l_write_register(ViPipe, 0x0100, 0x01); + + printf("ViPipe:%d,===SC5336_2L 1620P 30fps 10bit LINE Init OK!===\n", ViPipe); +} diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/Makefile b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/Makefile new file mode 100644 index 000000000..c2c419ec9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_q03p.a +TARGET_SO = $(MW_LIB)/libsns_q03p.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJ) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos.c b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos.c new file mode 100644 index 000000000..cd81e2fd9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos.c @@ -0,0 +1,841 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "q03p_cmos_ex.h" +#include "q03p_cmos_param.h" +// #include + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define Q03P_ID 03 +#define Q03P_I2C_ADDR_1 0x40 +#define Q03P_I2C_ADDR_2 0x44 +#define Q03P_I2C_ADDR_IS_VALID(addr) ((addr) == Q03P_I2C_ADDR_1 || (addr) == Q03P_I2C_ADDR_2) +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastQ03P[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define Q03P_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastQ03P[dev]) +#define Q03P_SENSOR_SET_CTX(dev, pstCtx) (g_pastQ03P[dev] = pstCtx) +#define Q03P_SENSOR_RESET_CTX(dev) (g_pastQ03P[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunQ03P_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16Q03P_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16Q03P_L2SMode[VI_MAX_PIPE_NUM] = {0}; +ISP_SNS_MIRRORFLIP_TYPE_E g_aeQ03P_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****Q03P Lines Range*****/ +#define Q03P_FULL_LINES_MAX (0xFFFF) + +/*****Q03P Register Address*****/ +#define Q03P_SHS1_ADDR 0x01 +#define Q03P_GAIN_ADDR 0x00 +#define Q03P_VMAX_ADDR 0x22 +#define Q03P_TABLE_END 0xff + +#define Q03P_RES_IS_1296P(w, h) ((w) <= 2304 && (h) <= 1296) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const Q03P_MODE_S *pstMode; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astQ03P_mode[pstSnsState->u8ImgMode]; +#if 0 + memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S)); +#endif + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = Q03P_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 2; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_DB; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + pstAeSnsDft->enBlcType = AE_BLC_TYPE_LINEAR; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u16Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u16Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u16Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u16Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? + g_au32InitExposure[ViPipe] : g_astQ03P_mode[Q03P_MODE_1296p30].stExp[0].u16Def; + + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 5; + pstAeSnsDft->u32MinIntTime = 1; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astQ03P_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astQ03P_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astQ03P_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case Q03P_MODE_1296p30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > Q03P_FULL_LINES_MAX) ? Q03P_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_DATA].u32Data = (u32VMAX & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_DATA].u32Data = ((u32VMAX & 0xFF00) >> 8); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 5; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if ((u32IntTime[0] + 5) > pstSnsState->au32FL[0]) { + CVI_TRACE_SNS(CVI_DBG_ERR, "inttime over spec [%u, %u]\n", + u32IntTime[0], + pstSnsState->au32FL[0]); + return CVI_FAILURE; + } + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_DATA].u32Data = (u32IntTime[0] & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_DATA].u32Data = ((u32IntTime[0] & 0xFF00) >> 8); + + return CVI_SUCCESS; + +} + +// static CVI_U32 gain_table[64] = { +// 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792, +// 1856, 1920, 1984, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200, +// 3328, 3456, 3584, 3712, 3840, 3968, 4096, 4352, 4608, 4864, 5120, 5376, 5632, +// 5888, 6144, 6400, 6656, 6912, 7168, 7424, 7680, 7936, 8192, 8704, 9216, 9728, +// 10240, 10752, 11264, 11776, 12288, 12800, 13312, 13824, 14336, 14848, 15360, +// 15872 +// }; +static CVI_U32 gain_table[96] = { + 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792, + 1856, 1920, 1984, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200, + 3328, 3456, 3584, 3712, 3840, 3968, 4096, 4352, 4608, 4864, 5120, 5376, 5632, + 5888, 6144, 6400, 6656, 6912, 7168, 7424, 7680, 7936, 8192, 8704, 9216, 9728, + 10240, 10752, 11264, 11776, 12288, 12800, 13312, 13824, 14336, 14848, 15360, + 15872,16384,17408,18432,19456,20480,21504,22528,23552,24576,25600,26624,27648, + 28672,29696,30720,31744,32768,34816,36864,38912,40960,43008,45056,47104,49152, + 51200,53248,55296,57344,59392,61440,63488 +}; +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + int i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= gain_table[95]) { + *pu32AgainLin = gain_table[95]; + *pu32AgainDb = 95; + return CVI_SUCCESS; + } + + for (i = 1; i < 95; i++) { + if (*pu32AgainLin < gain_table[i]) { + *pu32AgainLin = gain_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + *pu32DgainLin = 1024; + *pu32DgainDb = 0; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_DATA].u32Data = (u32Again & 0xFF); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + //pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + //pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const Q03P_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astQ03P_mode[pstSnsState->u8ImgMode]; + + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = Q03P_MODE_1296p30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astQ03P_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunQ03P_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = q03p_i2c_addr; + pstI2c_data[i].u32AddrByteNum = q03p_addr_byte; + pstI2c_data[i].u32DataByteNum = q03p_data_byte; + } + + //DOL 2t1 Mode Regs + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + pstI2c_data[LINEAR_SHS1_0_DATA].u32RegAddr = Q03P_SHS1_ADDR; + + pstI2c_data[LINEAR_SHS1_1_DATA].u32RegAddr = Q03P_SHS1_ADDR + 1; + + pstI2c_data[LINEAR_AGAIN_DATA].u32RegAddr = Q03P_GAIN_ADDR; + + pstI2c_data[LINEAR_VMAX_0_DATA].u32RegAddr = Q03P_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_0_DATA].u8DelayFrmNum = 2; + + pstI2c_data[LINEAR_VMAX_1_DATA].u32RegAddr = Q03P_VMAX_ADDR + 1; + pstI2c_data[LINEAR_VMAX_1_DATA].u8DelayFrmNum = 2; + + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (Q03P_RES_IS_1296P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = Q03P_MODE_1296p30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + if (pstSnsState->bInit == CVI_TRUE && g_aeQ03P_MirrorFip[ViPipe] != eSnsMirrorFlip) { + q03p_mirror_flip(ViPipe, eSnsMirrorFlip); + g_aeQ03P_MirrorFip[ViPipe] = eSnsMirrorFlip; + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const Q03P_MODE_S *pstMode = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = Q03P_MODE_1296p30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astQ03P_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &q03p_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astQ03P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astQ03P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &q03p_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = q03p_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = q03p_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (Q03P_I2C_ADDR_IS_VALID(s32I2cAddr)) + q03p_i2c_addr = s32I2cAddr; +} + +static CVI_S32 q03p_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunQ03P_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + Q03P_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + Q03P_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = Q03P_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, Q03P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, Q03P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, Q03P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16Q03P_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16Q03P_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsQ03P_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = q03p_standby, + .pfnRestart = q03p_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = q03p_write_register, + .pfnReadReg = q03p_read_register, + .pfnSetBusInfo = q03p_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = q03p_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h new file mode 100644 index 000000000..0e41820f2 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h @@ -0,0 +1,83 @@ +#ifndef __Q03P_CMOS_EX_H_ +#define __Q03P_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +#ifndef UNUSED +#define UNUSED(x) ((void)(x)) +#endif + +enum q03p_linear_regs_e { + LINEAR_SHS1_0_DATA, + LINEAR_SHS1_1_DATA, + LINEAR_AGAIN_DATA, + LINEAR_VMAX_0_DATA, + LINEAR_VMAX_1_DATA, + LINEAR_REGS_NUM +}; + + +typedef enum _Q03P_MODE_E { + Q03P_MODE_1296p30 = 0, + Q03P_MODE_LINEAR_NUM, + Q03P_MODE_1296p30_WDR = Q03P_MODE_LINEAR_NUM, + Q03P_MODE_NUM +} Q03P_MODE_E; + +typedef struct _Q03P_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + CVI_U8 u8DgainReg; + CVI_U32 u32L2S_MAX; + char name[64]; +} Q03P_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastQ03P[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunQ03P_BusInfo[]; +extern CVI_U16 g_au16Q03P_GainMode[]; +extern CVI_U16 g_au16Q03P_L2SMode[]; +extern CVI_U8 q03p_i2c_addr; +extern const CVI_U32 q03p_addr_byte; +extern const CVI_U32 q03p_data_byte; +extern void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern void q03p_init(VI_PIPE ViPipe); +extern void q03p_exit(VI_PIPE ViPipe); +extern void q03p_standby(VI_PIPE ViPipe); +extern void q03p_restart(VI_PIPE ViPipe); +extern int q03p_write_register(VI_PIPE ViPipe, int addr, int data); +extern int q03p_read_register(VI_PIPE ViPipe, int addr); +extern int q03p_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __Q03P_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_param.h new file mode 100644 index 000000000..91d4d43f1 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_param.h @@ -0,0 +1,123 @@ +#ifndef __Q03P_CMOS_PARAM_H_ +#define __Q03P_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "q03p_cmos_ex.h" + +static const Q03P_MODE_S g_astQ03P_mode[Q03P_MODE_NUM] = { + [Q03P_MODE_1296p30] = { + .name = "1296p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 2304, + .u32Height = 1296, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2304, + .u32Height = 1296, + }, + .stMaxSize = { + .u32Width = 2304, + .u32Height = 1296, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 0.64, /* 1400 * 30 / 0xFFFF */ + .u32HtsDef = 3600, + .u32VtsDef = 1400, + .stExp[0] = { + .u16Min = 1, + .u16Max = 1400, + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u16Min = 1024, + .u16Max = 15872,/* 1024 * 15.5 */ + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[0] = { + .u16Min = 1024, + .u16Max = 1024, + .u16Def = 1024, + .u16Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {64, 64, 64, 64, 0, 0, 0, 0. +#ifdef ARCH_CV182X + , 1040, 1040, 1040, 1040 +#endif + }, + + .stAuto = { + {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, +#endif + }, + }, +}; + +struct combo_dev_attr_s q03p_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {2, 3, 4, -1, -1}, + .pn_swap = {0, 0, 0, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_24M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __Q03P_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_sensor_ctl.c new file mode 100644 index 000000000..207faafae --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_sensor_ctl.c @@ -0,0 +1,361 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "q03p_cmos_ex.h" + +#define Q03P_CHIP_ID_HI_ADDR 0x0A +#define Q03P_CHIP_ID_LO_ADDR 0x0B +#define Q03P_CHIP_ID 0x0843 + +//static void q03p_linear_1296p30_init(VI_PIPE ViPipe); +static void q03p_linear_1296p30_init(VI_PIPE ViPipe); +CVI_U8 q03p_i2c_addr = 0x40; /* I2C Address of Q03P */ +const CVI_U32 q03p_addr_byte = 1; +const CVI_U32 q03p_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int q03p_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunQ03P_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, q03p_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + printf("q03p_i2c_init success\n"); + return CVI_SUCCESS; +} + +int q03p_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int q03p_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + // add address byte 0 + buf[idx++] = addr & 0xff; + // printf("buff[%d]:%x\n",idx,buf[idx]); + ret = write(g_fd[ViPipe], buf, q03p_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + ret = read(g_fd[ViPipe], buf, q03p_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (q03p_data_byte == 1) { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int q03p_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (q03p_addr_byte == 1) { + buf[idx] = addr & 0xff; + idx++; + } + if (q03p_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, q03p_addr_byte + q03p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + // printf("q03p_write_register success\n"); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void q03p_prog(VI_PIPE ViPipe, int *rom) +{ + int i = 0; + + while (1) { + int lookup = rom[i++]; + int addr = (lookup >> 16) & 0xFFFF; + int data = lookup & 0xFFFF; + + if (addr == 0xFFFE) + delay_ms(data); + else if (addr != 0xFFFF) + q03p_write_register(ViPipe, addr, data); + } +} + +void q03p_standby(VI_PIPE ViPipe) +{ + q03p_write_register(ViPipe, 0x12, 0x40); +} + +void q03p_restart(VI_PIPE ViPipe) +{ + q03p_write_register(ViPipe, 0x12, 0x40); + delay_ms(20); + q03p_write_register(ViPipe, 0x12, 0x00); +} + +void q03p_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastQ03P[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + q03p_write_register(ViPipe, + g_pastQ03P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastQ03P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = q03p_read_register(ViPipe, 0x12) & ~0x30; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x20; + break; + case ISP_SNS_FLIP: + val |= 0x10; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x30; + break; + default: + return; + } + + q03p_write_register(ViPipe, 0x12, val); +} + +int q03p_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + usleep(4*1000); + if (q03p_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + printf("q03p_read_register,Q03P_CHIP_ID_HI_ADDR:%x\n ",Q03P_CHIP_ID_HI_ADDR); + nVal = q03p_read_register(ViPipe, Q03P_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + printf("q03p_read_register,Q03P_CHIP_ID_LO_ADDR:%x\n ",Q03P_CHIP_ID_LO_ADDR); + nVal = q03p_read_register(ViPipe, Q03P_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != Q03P_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void q03p_init(VI_PIPE ViPipe) +{ + q03p_i2c_init(ViPipe); + + q03p_linear_1296p30_init(ViPipe); + g_pastQ03P[ViPipe]->bInit = CVI_TRUE; +} + +void q03p_exit(VI_PIPE ViPipe) +{ + q03p_i2c_exit(ViPipe); +} + +static void q03p_linear_1296p30_init(VI_PIPE ViPipe) +{ + q03p_write_register(ViPipe, 0x12,0x40); + q03p_write_register(ViPipe, 0x48,0x96); + q03p_write_register(ViPipe, 0x48,0x16); + q03p_write_register(ViPipe, 0x0E,0x11); + q03p_write_register(ViPipe, 0x0F,0x04); + q03p_write_register(ViPipe, 0x10,0x3F); + q03p_write_register(ViPipe, 0x11,0x80); + q03p_write_register(ViPipe, 0x46,0x00); + q03p_write_register(ViPipe, 0x0D,0xA0); + q03p_write_register(ViPipe, 0x57,0x67); + q03p_write_register(ViPipe, 0x58,0x1F); + q03p_write_register(ViPipe, 0x5F,0x41); + q03p_write_register(ViPipe, 0x60,0x28); + q03p_write_register(ViPipe, 0x64,0xD2); + q03p_write_register(ViPipe, 0xA5,0x4F); + q03p_write_register(ViPipe, 0x20,0x84); + q03p_write_register(ViPipe, 0x21,0x03); + q03p_write_register(ViPipe, 0x22,0x78); + q03p_write_register(ViPipe, 0x23,0x05); + q03p_write_register(ViPipe, 0x24,0x40); + q03p_write_register(ViPipe, 0x25,0x10); + q03p_write_register(ViPipe, 0x26,0x52); + q03p_write_register(ViPipe, 0x27,0x74); + q03p_write_register(ViPipe, 0x28,0x15); + q03p_write_register(ViPipe, 0x29,0x03); + q03p_write_register(ViPipe, 0x2A,0x6E); + q03p_write_register(ViPipe, 0x2B,0x13); + q03p_write_register(ViPipe, 0x2C,0x00); + q03p_write_register(ViPipe, 0x2D,0x00); + q03p_write_register(ViPipe, 0x2E,0x4A); + q03p_write_register(ViPipe, 0x2F,0x64); + q03p_write_register(ViPipe, 0x41,0x84); + q03p_write_register(ViPipe, 0x42,0x24); + q03p_write_register(ViPipe, 0x47,0x42); + q03p_write_register(ViPipe, 0x76,0x40); + q03p_write_register(ViPipe, 0x77,0x0B); + q03p_write_register(ViPipe, 0x80,0x03); + q03p_write_register(ViPipe, 0xAF,0x22); + q03p_write_register(ViPipe, 0xAB,0x00); + q03p_write_register(ViPipe, 0x1D,0x00); + q03p_write_register(ViPipe, 0x1E,0x04); + q03p_write_register(ViPipe, 0x6C,0x40); + q03p_write_register(ViPipe, 0x6E,0x2C); + q03p_write_register(ViPipe, 0x70,0xD9); + q03p_write_register(ViPipe, 0x71,0xD5); + q03p_write_register(ViPipe, 0x72,0xD2); + q03p_write_register(ViPipe, 0x73,0x59); + q03p_write_register(ViPipe, 0x74,0x02); + q03p_write_register(ViPipe, 0x78,0x98); + q03p_write_register(ViPipe, 0x89,0x01); + q03p_write_register(ViPipe, 0x6B,0x20); + q03p_write_register(ViPipe, 0x86,0x40); + q03p_write_register(ViPipe, 0x0C,0x10); + q03p_write_register(ViPipe, 0x31,0x10); + q03p_write_register(ViPipe, 0x32,0x31); + q03p_write_register(ViPipe, 0x33,0x5C); + q03p_write_register(ViPipe, 0x34,0x24); + q03p_write_register(ViPipe, 0x35,0x20); + q03p_write_register(ViPipe, 0x3A,0xA0); + q03p_write_register(ViPipe, 0x3B,0x00); + q03p_write_register(ViPipe, 0x3C,0xDC); + q03p_write_register(ViPipe, 0x3D,0xF0); + q03p_write_register(ViPipe, 0x3E,0xBC); + q03p_write_register(ViPipe, 0x56,0x10); + q03p_write_register(ViPipe, 0x59,0x54); + q03p_write_register(ViPipe, 0x5A,0x00); + q03p_write_register(ViPipe, 0x61,0x00); + q03p_write_register(ViPipe, 0x85,0x4A); + q03p_write_register(ViPipe, 0x8A,0x00); + q03p_write_register(ViPipe, 0x8D,0x67); + q03p_write_register(ViPipe, 0x91,0x08); + q03p_write_register(ViPipe, 0x94,0xA0); + q03p_write_register(ViPipe, 0x9C,0x61); + q03p_write_register(ViPipe, 0xA7,0x00); + q03p_write_register(ViPipe, 0xA9,0x4C); + q03p_write_register(ViPipe, 0x5B,0xA0); + q03p_write_register(ViPipe, 0x5C,0x84); + q03p_write_register(ViPipe, 0x5D,0x86); + q03p_write_register(ViPipe, 0x5E,0x03); + q03p_write_register(ViPipe, 0x65,0x02); + q03p_write_register(ViPipe, 0x66,0xC4); + q03p_write_register(ViPipe, 0x67,0x48); + q03p_write_register(ViPipe, 0x68,0x00); + q03p_write_register(ViPipe, 0x69,0x74); + q03p_write_register(ViPipe, 0x6A,0x22); + q03p_write_register(ViPipe, 0x7A,0x77); + q03p_write_register(ViPipe, 0x8F,0x90); + q03p_write_register(ViPipe, 0x45,0x01); + q03p_write_register(ViPipe, 0xA4,0xC7); + q03p_write_register(ViPipe, 0x97,0x20); + q03p_write_register(ViPipe, 0x13,0x81); + q03p_write_register(ViPipe, 0x96,0x84); + q03p_write_register(ViPipe, 0x4A,0x01); + q03p_write_register(ViPipe, 0xB1,0x00); + q03p_write_register(ViPipe, 0xA1,0x0F); + q03p_write_register(ViPipe, 0xB5,0x0C); + q03p_write_register(ViPipe, 0x7E,0x48); + q03p_write_register(ViPipe, 0x9E,0xF0); + q03p_write_register(ViPipe, 0x50,0x02); + q03p_write_register(ViPipe, 0x49,0x10); + q03p_write_register(ViPipe, 0x7F,0x56); + q03p_write_register(ViPipe, 0x8C,0xFF); + q03p_write_register(ViPipe, 0x8E,0x00); + q03p_write_register(ViPipe, 0x8B,0x01); + q03p_write_register(ViPipe, 0xBC,0x11); + q03p_write_register(ViPipe, 0x82,0x00); + q03p_write_register(ViPipe, 0x19,0x20); + q03p_write_register(ViPipe, 0x1B,0x4F); + q03p_write_register(ViPipe, 0x12,0x00); + q03p_write_register(ViPipe, 0x48,0x96); + q03p_write_register(ViPipe, 0x48,0x16); + q03p_default_reg_init(ViPipe); + printf("ViPipe:%d,===Q03P 1296P 30fps 10bit LINE Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv181x/Makefile b/middleware/v2/component/isp/sensor/cv181x/Makefile index 815ace8d6..6706e8cfc 100644 --- a/middleware/v2/component/isp/sensor/cv181x/Makefile +++ b/middleware/v2/component/isp/sensor/cv181x/Makefile @@ -28,6 +28,8 @@ brigates_bg0808: gcore_gc02m1: $(call MAKE_SENSOR, ${@}) +gcore_gc0312: + $(call MAKE_SENSOR, ${@}) gcore_gc0329: $(call MAKE_SENSOR, ${@}) @@ -134,15 +136,27 @@ sms_sc3335: sms_sc3336: $(call MAKE_SENSOR, ${@}) +sms_sc2331_1L: + $(call MAKE_SENSOR, ${@}) + sms_sc2335: $(call MAKE_SENSOR, ${@}) sms_sc2336: $(call MAKE_SENSOR, ${@}) +sms_sc2336p: + $(call MAKE_SENSOR, ${@}) + sms_sc4336: $(call MAKE_SENSOR, ${@}) +sms_sc4336p: + $(call MAKE_SENSOR, ${@}) + +sms_sc5336_2L: + $(call MAKE_SENSOR, ${@}) + soi_f23: $(call MAKE_SENSOR, ${@}) @@ -155,6 +169,9 @@ soi_f37p: soi_q03: $(call MAKE_SENSOR, ${@}) +soi_q03p: + $(call MAKE_SENSOR, ${@}) + soi_k06: $(call MAKE_SENSOR, ${@}) @@ -191,6 +208,9 @@ techpoint_tp2825: techpoint_tp2863: $(call MAKE_SENSOR, ${@}) +lontium_lt6911: + $(call MAKE_SENSOR, ${@}) + all_sensor: @$(MAKE) -f Makefile_full || exit 1; diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/Makefile b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/Makefile new file mode 100644 index 000000000..4a0e22f55 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_gc0312.a +TARGET_SO = $(MW_LIB)/libsns_gc0312.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos.c b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos.c new file mode 100644 index 000000000..0f5e654f8 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos.c @@ -0,0 +1,303 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "gc0312_cmos_ex.h" +#include "gc0312_cmos_param.h" + +#define GC0312_ID 0xb310 +#define GC0312_I2C_ADDR_1 0x21 +#define GC0312_I2C_ADDR_IS_VALID(addr) ((addr) == GC0312_I2C_ADDR_1) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastGc0312[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define GC0312_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc0312[dev]) +#define GC0312_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc0312[dev] = pstCtx) +#define GC0312_SENSOR_RESET_CTX(dev) (g_pastGc0312[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunGc0312_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +#define GC0312_RES_IS_480P(w, h) ((w) == 640 && (h) == 480) + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const GC0312_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astGc0312_mode; + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstCfg0 = &pstSnsState->astSyncInfo[0]; + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 20) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (GC0312_RES_IS_480P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) + u8SensorImageMode = GC0312_MODE_640X480P20; + else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps); + return CVI_FAILURE; + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = GC0312_MODE_640X480P20; + pstSnsState->enWDRMode = WDR_MODE_NONE; +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &gc0312_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astGc0312_mode.stImg.stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astGc0312_mode.stImg.stSnsSize.u32Height; + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc0312_rx_attr; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = gc0312_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = gc0312_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (GC0312_I2C_ADDR_IS_VALID(s32I2cAddr)) + gc0312_i2c_addr = s32I2cAddr; +} + +static CVI_S32 gc0312_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunGc0312_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + GC0312_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC0312_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + GC0312_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + (void) pstAeLib; + (void) pstAwbLib; + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = GC0312_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + (void) pstAeLib; + (void) pstAwbLib; + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC0312_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return gc0312_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsGc0312_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = CVI_NULL, + .pfnRestart = CVI_NULL, + .pfnWriteReg = gc0312_write_register, + .pfnReadReg = gc0312_read_register, + .pfnSetBusInfo = gc0312_set_bus_info, + .pfnSetInit = CVI_NULL, + .pfnMirrorFlip = CVI_NULL, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = CVI_NULL, + .pfnSnsProbe = sensor_probe, +}; diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos_ex.h new file mode 100644 index 000000000..d06a6598f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos_ex.h @@ -0,0 +1,64 @@ +#ifndef __GC0312_CMOS_EX_H_ +#define __GC0312_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +typedef enum _GC0312_MODE_E { + GC0312_MODE_640X480P20 = 0, + GC0312_MODE_NUM +} GC0312_SLAVE_MODE_E; + +typedef struct _GC0312_MODE_S { + ISP_WDR_SIZE_S stImg; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp; + SNS_ATTR_LARGE_S stAgain; + SNS_ATTR_LARGE_S stDgain; + char name[64]; +} GC0312_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastGc0312[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunGc0312_BusInfo[]; +extern CVI_U8 gc0312_i2c_addr; +extern const CVI_U32 gc0312_addr_byte; +extern const CVI_U32 gc0312_data_byte; +extern void gc0312_init(VI_PIPE ViPipe); +extern void gc0312_exit(VI_PIPE ViPipe); +extern void gc0312_standby(VI_PIPE ViPipe); +extern void gc0312_restart(VI_PIPE ViPipe); +extern int gc0312_write_register(VI_PIPE ViPipe, int addr, int data); +extern int gc0312_read_register(VI_PIPE ViPipe, int addr); +extern void gc0312_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int gc0312_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC0312_CMOS_EX_H_ */ + diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos_param.h new file mode 100644 index 000000000..cfc16cc3b --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_cmos_param.h @@ -0,0 +1,71 @@ +#ifndef __GC0312_CMOS_PARAM_H_ +#define __GC0312_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc0312_cmos_ex.h" + +static const GC0312_MODE_S g_astGc0312_mode = { + .name = "640X480P20", + .stImg = { + .stSnsSize = { + .u32Width = 640, + .u32Height = 480, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 640, + .u32Height = 480, + }, + .stMaxSize = { + .u32Width = 640, + .u32Height = 480, + }, + }, +}; + +struct combo_dev_attr_s gc0312_rx_attr = { + .input_mode = INPUT_MODE_BT601, + .mac_clk = RX_MAC_CLK_200M, + .ttl_attr = { + .vi = TTL_VI_SRC_VI0, + .ttl_fmt = TTL_VSDE_11B, + .raw_data_type = RAW_DATA_8BIT, + .func = { + 11, -1, -1, 12, + 1, 3, 4, 2, + 0, 5, 6, 7, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, + .mclk = { + .cam = 1, + .freq = CAMPLL_FREQ_24M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC0312_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_sensor_ctl.c new file mode 100644 index 000000000..72405a1e9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0312/gc0312_sensor_ctl.c @@ -0,0 +1,555 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc0312_cmos_ex.h" + +static void gc0312_linear_480p20_init(VI_PIPE ViPipe); + +CVI_U8 gc0312_i2c_addr = 0x21; +const CVI_U32 gc0312_addr_byte = 1; +const CVI_U32 gc0312_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int gc0312_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunGc0312_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc0312_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int gc0312_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int gc0312_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (gc0312_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, gc0312_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, gc0312_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (gc0312_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + + +int gc0312_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (gc0312_addr_byte == 1) { + buf[idx] = addr & 0xff; + idx++; + } + if (gc0312_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, gc0312_addr_byte + gc0312_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } +// syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +#define GC0312_CHIP_ID 0xb310 +#define GC0312_CHIP_ID_ADDR_H 0xf0 +#define GC0312_CHIP_ID_ADDR_L 0xf1 + +int gc0312_probe(VI_PIPE ViPipe) +{ + int nVal; + int nVal2; + + usleep(50); + if (gc0312_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = gc0312_read_register(ViPipe, GC0312_CHIP_ID_ADDR_H); + nVal2 = gc0312_read_register(ViPipe, GC0312_CHIP_ID_ADDR_L); + if (nVal < 0 || nVal2 < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + + if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC0312_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + printf("%d\n", ViPipe); + return CVI_SUCCESS; +} + +void gc0312_init(VI_PIPE ViPipe) +{ + gc0312_i2c_init(ViPipe); + + gc0312_linear_480p20_init(ViPipe); + + g_pastGc0312[ViPipe]->bInit = CVI_TRUE; +} + +void gc0312_exit(VI_PIPE ViPipe) +{ + gc0312_i2c_exit(ViPipe); +} + +static void gc0312_linear_480p20_init(VI_PIPE ViPipe) +{ + gc0312_write_register(ViPipe, 0xfe, 0xf0); + gc0312_write_register(ViPipe, 0xfe, 0xf0); + gc0312_write_register(ViPipe, 0xfe, 0x00); + gc0312_write_register(ViPipe, 0xfc, 0x0e); + gc0312_write_register(ViPipe, 0xfc, 0x0e); + gc0312_write_register(ViPipe, 0xf2, 0x07); + gc0312_write_register(ViPipe, 0xf3, 0x00);// output_disable + gc0312_write_register(ViPipe, 0xf7, 0x1b); + gc0312_write_register(ViPipe, 0xf8, 0x04); + gc0312_write_register(ViPipe, 0xf9, 0x0e); + gc0312_write_register(ViPipe, 0xfa, 0x11); + + ///////////////////////////////////////////////// + ///////////////// CISCTL reg ///////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x00, 0x2f); + gc0312_write_register(ViPipe, 0x01, 0x0f); + gc0312_write_register(ViPipe, 0x02, 0x04); + gc0312_write_register(ViPipe, 0x03, 0x03); + gc0312_write_register(ViPipe, 0x04, 0x50); + gc0312_write_register(ViPipe, 0x09, 0x00); + gc0312_write_register(ViPipe, 0x0a, 0x00); + gc0312_write_register(ViPipe, 0x0b, 0x00); + gc0312_write_register(ViPipe, 0x0c, 0x04); + gc0312_write_register(ViPipe, 0x0d, 0x01); + gc0312_write_register(ViPipe, 0x0e, 0xe8); + gc0312_write_register(ViPipe, 0x0f, 0x02); + gc0312_write_register(ViPipe, 0x10, 0x88); + gc0312_write_register(ViPipe, 0x16, 0x00); + gc0312_write_register(ViPipe, 0x17, 0x14); + gc0312_write_register(ViPipe, 0x18, 0x1a); + gc0312_write_register(ViPipe, 0x19, 0x14); + gc0312_write_register(ViPipe, 0x1b, 0x48); + gc0312_write_register(ViPipe, 0x1c, 0x6c);//1c travis 20140929 + gc0312_write_register(ViPipe, 0x1e, 0x6b); + gc0312_write_register(ViPipe, 0x1f, 0x28); + gc0312_write_register(ViPipe, 0x20, 0x8b);//89 travis 20140801 + gc0312_write_register(ViPipe, 0x21, 0x49); + gc0312_write_register(ViPipe, 0x22, 0xd0);//b0 travis 20140929 + gc0312_write_register(ViPipe, 0x23, 0x04); + gc0312_write_register(ViPipe, 0x24, 0x16); + gc0312_write_register(ViPipe, 0x34, 0x20); + + ///////////////////////////////////////////////// + //////////////////// BLK //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x26, 0x23); + gc0312_write_register(ViPipe, 0x28, 0xff); + gc0312_write_register(ViPipe, 0x29, 0x00); + gc0312_write_register(ViPipe, 0x32, 0x04);//00 travis 20140929 + gc0312_write_register(ViPipe, 0x33, 0x10); + gc0312_write_register(ViPipe, 0x37, 0x20); + gc0312_write_register(ViPipe, 0x38, 0x10); + gc0312_write_register(ViPipe, 0x47, 0x80); + gc0312_write_register(ViPipe, 0x4e, 0x66); + gc0312_write_register(ViPipe, 0xa8, 0x02); + gc0312_write_register(ViPipe, 0xa9, 0x80); + + ///////////////////////////////////////////////// + ////////////////// ISP reg /////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x40, 0xff); + gc0312_write_register(ViPipe, 0x41, 0x21); + gc0312_write_register(ViPipe, 0x42, 0xcf); + gc0312_write_register(ViPipe, 0x44, 0x02); + gc0312_write_register(ViPipe, 0x45, 0xa8); + gc0312_write_register(ViPipe, 0x46, 0x02); + gc0312_write_register(ViPipe, 0x4a, 0x11); + gc0312_write_register(ViPipe, 0x4b, 0x01); + gc0312_write_register(ViPipe, 0x4c, 0x20); + gc0312_write_register(ViPipe, 0x4d, 0x05); + gc0312_write_register(ViPipe, 0x4f, 0x01); + gc0312_write_register(ViPipe, 0x50, 0x01); + gc0312_write_register(ViPipe, 0x55, 0x01); + gc0312_write_register(ViPipe, 0x56, 0xe0); + gc0312_write_register(ViPipe, 0x57, 0x02); + gc0312_write_register(ViPipe, 0x58, 0x80); + + ///////////////////////////////////////////////// + /////////////////// GAIN //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x70, 0x70); + gc0312_write_register(ViPipe, 0x5a, 0x84); + gc0312_write_register(ViPipe, 0x5b, 0xc9); + gc0312_write_register(ViPipe, 0x5c, 0xed); + gc0312_write_register(ViPipe, 0x77, 0x74); + gc0312_write_register(ViPipe, 0x78, 0x40); + gc0312_write_register(ViPipe, 0x79, 0x5f); + + ///////////////////////////////////////////////// + /////////////////// DNDD ///////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x82, 0x14); + gc0312_write_register(ViPipe, 0x83, 0x0b); + gc0312_write_register(ViPipe, 0x89, 0xf0); + + ///////////////////////////////////////////////// + ////////////////// EEINTP //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x8f, 0xaa); + gc0312_write_register(ViPipe, 0x90, 0x8c); + gc0312_write_register(ViPipe, 0x91, 0x90); + gc0312_write_register(ViPipe, 0x92, 0x03); + gc0312_write_register(ViPipe, 0x93, 0x03); + gc0312_write_register(ViPipe, 0x94, 0x05); + gc0312_write_register(ViPipe, 0x95, 0x65); + gc0312_write_register(ViPipe, 0x96, 0xf0); + + ///////////////////////////////////////////////// + ///////////////////// ASDE //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x00); + + gc0312_write_register(ViPipe, 0x9a, 0x20); + gc0312_write_register(ViPipe, 0x9b, 0x80); + gc0312_write_register(ViPipe, 0x9c, 0x40); + gc0312_write_register(ViPipe, 0x9d, 0x80); + + gc0312_write_register(ViPipe, 0xa1, 0x30); + gc0312_write_register(ViPipe, 0xa2, 0x32); + gc0312_write_register(ViPipe, 0xa4, 0x80);//30 travis 20140929 + gc0312_write_register(ViPipe, 0xa5, 0x28);//30 travis 20140929 + gc0312_write_register(ViPipe, 0xaa, 0x30);//10 travis 20140929 + gc0312_write_register(ViPipe, 0xac, 0x22); + + ///////////////////////////////////////////////// + /////////////////// GAMMA /////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x00);//default + gc0312_write_register(ViPipe, 0xbf, 0x08); + gc0312_write_register(ViPipe, 0xc0, 0x16); + gc0312_write_register(ViPipe, 0xc1, 0x28); + gc0312_write_register(ViPipe, 0xc2, 0x41); + gc0312_write_register(ViPipe, 0xc3, 0x5a); + gc0312_write_register(ViPipe, 0xc4, 0x6c); + gc0312_write_register(ViPipe, 0xc5, 0x7a); + gc0312_write_register(ViPipe, 0xc6, 0x96); + gc0312_write_register(ViPipe, 0xc7, 0xac); + gc0312_write_register(ViPipe, 0xc8, 0xbc); + gc0312_write_register(ViPipe, 0xc9, 0xc9); + gc0312_write_register(ViPipe, 0xca, 0xd3); + gc0312_write_register(ViPipe, 0xcb, 0xdd); + gc0312_write_register(ViPipe, 0xcc, 0xe5); + gc0312_write_register(ViPipe, 0xcd, 0xf1); + gc0312_write_register(ViPipe, 0xce, 0xfa); + gc0312_write_register(ViPipe, 0xcf, 0xff); + ///////////////////////////////////////////////// + /////////////////// YCP ////////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xd0, 0x40); + gc0312_write_register(ViPipe, 0xd1, 0x34); + gc0312_write_register(ViPipe, 0xd2, 0x34); + gc0312_write_register(ViPipe, 0xd3, 0x40); + gc0312_write_register(ViPipe, 0xd6, 0xf2); + gc0312_write_register(ViPipe, 0xd7, 0x1b); + gc0312_write_register(ViPipe, 0xd8, 0x18); + gc0312_write_register(ViPipe, 0xdd, 0x03); + + ///////////////////////////////////////////////// + //////////////////// AEC //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x01); + gc0312_write_register(ViPipe, 0x05, 0x30); + gc0312_write_register(ViPipe, 0x06, 0x75); + gc0312_write_register(ViPipe, 0x07, 0x40); + gc0312_write_register(ViPipe, 0x08, 0xb0); + gc0312_write_register(ViPipe, 0x0a, 0xc5); + gc0312_write_register(ViPipe, 0x0b, 0x11); + gc0312_write_register(ViPipe, 0x0c, 0x00); + gc0312_write_register(ViPipe, 0x12, 0x52); + gc0312_write_register(ViPipe, 0x13, 0x38); + gc0312_write_register(ViPipe, 0x18, 0x95); + gc0312_write_register(ViPipe, 0x19, 0x96); + gc0312_write_register(ViPipe, 0x1f, 0x20); + gc0312_write_register(ViPipe, 0x20, 0xc0); + gc0312_write_register(ViPipe, 0x3e, 0x40); + gc0312_write_register(ViPipe, 0x3f, 0x57); + gc0312_write_register(ViPipe, 0x40, 0x7d); + gc0312_write_register(ViPipe, 0x03, 0x60); + gc0312_write_register(ViPipe, 0x44, 0x02); + + ///////////////////////////////////////////////// + //////////////////// AWB //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x01); + gc0312_write_register(ViPipe, 0x1c, 0x91); + gc0312_write_register(ViPipe, 0x21, 0x15); + gc0312_write_register(ViPipe, 0x50, 0x80); + gc0312_write_register(ViPipe, 0x56, 0x04); + gc0312_write_register(ViPipe, 0x59, 0x08); + gc0312_write_register(ViPipe, 0x5b, 0x02); + gc0312_write_register(ViPipe, 0x61, 0x8d); + gc0312_write_register(ViPipe, 0x62, 0xa7); + gc0312_write_register(ViPipe, 0x63, 0xd0); + gc0312_write_register(ViPipe, 0x65, 0x06); + gc0312_write_register(ViPipe, 0x66, 0x06); + gc0312_write_register(ViPipe, 0x67, 0x84); + gc0312_write_register(ViPipe, 0x69, 0x08); + gc0312_write_register(ViPipe, 0x6a, 0x25); + gc0312_write_register(ViPipe, 0x6b, 0x01); + gc0312_write_register(ViPipe, 0x6c, 0x00); + gc0312_write_register(ViPipe, 0x6d, 0x02); + gc0312_write_register(ViPipe, 0x6e, 0xf0); + gc0312_write_register(ViPipe, 0x6f, 0x80); + gc0312_write_register(ViPipe, 0x76, 0x80); + gc0312_write_register(ViPipe, 0x78, 0xaf); + gc0312_write_register(ViPipe, 0x79, 0x75); + gc0312_write_register(ViPipe, 0x7a, 0x40); + gc0312_write_register(ViPipe, 0x7b, 0x50); + gc0312_write_register(ViPipe, 0x7c, 0x0c); + + + gc0312_write_register(ViPipe, 0x90, 0xc9);//stable AWB + gc0312_write_register(ViPipe, 0x91, 0xbe); + gc0312_write_register(ViPipe, 0x92, 0xe2); + gc0312_write_register(ViPipe, 0x93, 0xc9); + gc0312_write_register(ViPipe, 0x95, 0x1b); + gc0312_write_register(ViPipe, 0x96, 0xe2); + gc0312_write_register(ViPipe, 0x97, 0x49); + gc0312_write_register(ViPipe, 0x98, 0x1b); + gc0312_write_register(ViPipe, 0x9a, 0x49); + gc0312_write_register(ViPipe, 0x9b, 0x1b); + gc0312_write_register(ViPipe, 0x9c, 0xc3); + gc0312_write_register(ViPipe, 0x9d, 0x49); + gc0312_write_register(ViPipe, 0x9f, 0xc7); + gc0312_write_register(ViPipe, 0xa0, 0xc8); + gc0312_write_register(ViPipe, 0xa1, 0x00); + gc0312_write_register(ViPipe, 0xa2, 0x00); + gc0312_write_register(ViPipe, 0x86, 0x00); + gc0312_write_register(ViPipe, 0x87, 0x00); + gc0312_write_register(ViPipe, 0x88, 0x00); + gc0312_write_register(ViPipe, 0x89, 0x00); + gc0312_write_register(ViPipe, 0xa4, 0xb9); + gc0312_write_register(ViPipe, 0xa5, 0xa0); + gc0312_write_register(ViPipe, 0xa6, 0xba); + gc0312_write_register(ViPipe, 0xa7, 0x92); + gc0312_write_register(ViPipe, 0xa9, 0xba); + gc0312_write_register(ViPipe, 0xaa, 0x80); + gc0312_write_register(ViPipe, 0xab, 0x9d); + gc0312_write_register(ViPipe, 0xac, 0x7f); + gc0312_write_register(ViPipe, 0xae, 0xbb); + gc0312_write_register(ViPipe, 0xaf, 0x9d); + gc0312_write_register(ViPipe, 0xb0, 0xc8); + gc0312_write_register(ViPipe, 0xb1, 0x97); + gc0312_write_register(ViPipe, 0xb3, 0xb7); + gc0312_write_register(ViPipe, 0xb4, 0x7f); + gc0312_write_register(ViPipe, 0xb5, 0x00); + gc0312_write_register(ViPipe, 0xb6, 0x00); + gc0312_write_register(ViPipe, 0x8b, 0x00); + gc0312_write_register(ViPipe, 0x8c, 0x00); + gc0312_write_register(ViPipe, 0x8d, 0x00); + gc0312_write_register(ViPipe, 0x8e, 0x00); + gc0312_write_register(ViPipe, 0x94, 0x55); + gc0312_write_register(ViPipe, 0x99, 0xa6); + gc0312_write_register(ViPipe, 0x9e, 0xaa); + gc0312_write_register(ViPipe, 0xa3, 0x0a); + gc0312_write_register(ViPipe, 0x8a, 0x00); + gc0312_write_register(ViPipe, 0xa8, 0x55); + gc0312_write_register(ViPipe, 0xad, 0x55); + gc0312_write_register(ViPipe, 0xb2, 0x55); + gc0312_write_register(ViPipe, 0xb7, 0x05); + gc0312_write_register(ViPipe, 0x8f, 0x00); + gc0312_write_register(ViPipe, 0xb8, 0xcb); + gc0312_write_register(ViPipe, 0xb9, 0x9b); + ///////////////////////////////////////////////// + //////////////////// CC //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x01); + + gc0312_write_register(ViPipe, 0xd0, 0x38);//skin red + gc0312_write_register(ViPipe, 0xd1, 0x00); + gc0312_write_register(ViPipe, 0xd2, 0x02); + gc0312_write_register(ViPipe, 0xd3, 0x04); + gc0312_write_register(ViPipe, 0xd4, 0x38); + gc0312_write_register(ViPipe, 0xd5, 0x12); + gc0312_write_register(ViPipe, 0xd6, 0x30); + gc0312_write_register(ViPipe, 0xd7, 0x00); + gc0312_write_register(ViPipe, 0xd8, 0x0a); + gc0312_write_register(ViPipe, 0xd9, 0x16); + gc0312_write_register(ViPipe, 0xda, 0x39); + gc0312_write_register(ViPipe, 0xdb, 0xf8); + + ///////////////////////////////////////////////// + //////////////////// LSC //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x01); + gc0312_write_register(ViPipe, 0xc1, 0x3c); + gc0312_write_register(ViPipe, 0xc2, 0x50); + gc0312_write_register(ViPipe, 0xc3, 0x00); + gc0312_write_register(ViPipe, 0xc4, 0x40); + gc0312_write_register(ViPipe, 0xc5, 0x30); + gc0312_write_register(ViPipe, 0xc6, 0x30); + gc0312_write_register(ViPipe, 0xc7, 0x10); + gc0312_write_register(ViPipe, 0xc8, 0x00); + gc0312_write_register(ViPipe, 0xc9, 0x00); + gc0312_write_register(ViPipe, 0xdc, 0x20); + gc0312_write_register(ViPipe, 0xdd, 0x10); + gc0312_write_register(ViPipe, 0xdf, 0x00); + gc0312_write_register(ViPipe, 0xde, 0x00); + + ///////////////////////////////////////////////// + /////////////////// Histogram ///////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x01, 0x10); + gc0312_write_register(ViPipe, 0x0b, 0x31); + gc0312_write_register(ViPipe, 0x0e, 0x50); + gc0312_write_register(ViPipe, 0x0f, 0x0f); + gc0312_write_register(ViPipe, 0x10, 0x6e); + gc0312_write_register(ViPipe, 0x12, 0xa0); + gc0312_write_register(ViPipe, 0x15, 0x60); + gc0312_write_register(ViPipe, 0x16, 0x60); + gc0312_write_register(ViPipe, 0x17, 0xe0); + + ///////////////////////////////////////////////// + ////////////// Measure Window /////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xcc, 0x0c); + gc0312_write_register(ViPipe, 0xcd, 0x10); + gc0312_write_register(ViPipe, 0xce, 0xa0); + gc0312_write_register(ViPipe, 0xcf, 0xe6); + + ///////////////////////////////////////////////// + ///////////////// dark sun ////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0x45, 0xf7); + gc0312_write_register(ViPipe, 0x46, 0xff); + gc0312_write_register(ViPipe, 0x47, 0x15); + gc0312_write_register(ViPipe, 0x48, 0x03); + gc0312_write_register(ViPipe, 0x4f, 0x60); + + //////////////////banding////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x00); + gc0312_write_register(ViPipe, 0x05, 0x02); + gc0312_write_register(ViPipe, 0x06, 0xd1); //HB + gc0312_write_register(ViPipe, 0x07, 0x00); + gc0312_write_register(ViPipe, 0x08, 0x22); //VB + + gc0312_write_register(ViPipe, 0xfe, 0x01); + gc0312_write_register(ViPipe, 0x25, 0x00); //anti-flicker step [11:8] + gc0312_write_register(ViPipe, 0x26, 0x6a); //anti-flicker step [7:0] + + gc0312_write_register(ViPipe, 0x27, 0x02); //exp level 0 20fps + gc0312_write_register(ViPipe, 0x28, 0x12); + gc0312_write_register(ViPipe, 0x29, 0x03); //exp level 1 12.50fps + gc0312_write_register(ViPipe, 0x2a, 0x50); + gc0312_write_register(ViPipe, 0x2b, 0x05); //7.14fps + gc0312_write_register(ViPipe, 0x2c, 0xcc); + gc0312_write_register(ViPipe, 0x2d, 0x07); //exp level 3 5.55fps + gc0312_write_register(ViPipe, 0x2e, 0x74); + gc0312_write_register(ViPipe, 0x3c, 0x20); + gc0312_write_register(ViPipe, 0xfe, 0x00); + + ///////////////////////////////////////////////// + ///////////////////// DVP //////////////////// + ///////////////////////////////////////////////// + gc0312_write_register(ViPipe, 0xfe, 0x03); + gc0312_write_register(ViPipe, 0x01, 0x00); + gc0312_write_register(ViPipe, 0x02, 0x00); + gc0312_write_register(ViPipe, 0x10, 0x00); + gc0312_write_register(ViPipe, 0x15, 0x00); + gc0312_write_register(ViPipe, 0xfe, 0x00); + ///////////////////OUTPUT////////////////////// + gc0312_write_register(ViPipe, 0xf3, 0xff);// output_enable + + + delay_ms(50); + + printf("ViPipe:%d,===GC0312 480P 20fps YUV Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/Makefile b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/Makefile new file mode 100644 index 000000000..8590b964e --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_lt6911.a +TARGET_SO = $(MW_LIB)/libsns_lt6911.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos.c b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos.c new file mode 100644 index 000000000..cceeeb08f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos.c @@ -0,0 +1,423 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "lt6911_cmos_ex.h" +#include "lt6911_cmos_param.h" + +#define LT6911_ID 6911 + +#define INPUT_WIDTH (1920) +#define INPUT_HEIGHT (1080) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastLt6911[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define LT6911_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastLt6911[dev]) +#define LT6911_SENSOR_SET_CTX(dev, pstCtx) (g_pastLt6911[dev] = pstCtx) +#define LT6911_SENSOR_RESET_CTX(dev) (g_pastLt6911[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunLt6911_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****lt6911 Lines Range*****/ + + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + (void) ViPipe; + (void) pstAeSnsDft; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + (void) ViPipe; + (void) pu32AgainLin; + (void) pu32AgainDb; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + (void) ViPipe; + (void) pu32DgainLin; + (void) pu32DgainDb; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + (void) ViPipe; + (void) pu32Again; + (void) pu32Dgain; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + + return CVI_SUCCESS; +} + + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const LT6911_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astLt6911_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "not support wdr mode\n"); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + + //pstSnsState->bSyncInit, pstSnsRegsInfo->bConfig); + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunLt6911_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + pstSnsState->bSyncInit = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = LT6911_MODE_NORMAL; + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + (void) ViPipe; + + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->u8ImgMode = LT6911_MODE_NORMAL; +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, <6911_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astLt6911_mode[0].astImg[pstSnsState->u8ImgMode].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astLt6911_mode[0].astImg[pstSnsState->u8ImgMode].stSnsSize.u32Height; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + (void) ViPipe; + (void) u8Mode; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = <6911_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = lt6911_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = lt6911_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 lt6911_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunLt6911_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_param_fix(CVI_VOID) +{ + LT6911_MODE_S *pstMode = &g_astLt6911_mode[LT6911_MODE_NORMAL]; + + pstMode->astImg[0].stSnsSize.u32Width = INPUT_WIDTH; + pstMode->astImg[0].stSnsSize.u32Height = INPUT_HEIGHT; + pstMode->astImg[0].stWndRect.u32Width = INPUT_WIDTH; + pstMode->astImg[0].stWndRect.u32Height = INPUT_HEIGHT; + pstMode->astImg[0].stMaxSize.u32Width = INPUT_WIDTH; + pstMode->astImg[0].stMaxSize.u32Height = INPUT_HEIGHT; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + LT6911_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + LT6911_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + LT6911_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + sensor_param_fix(); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = LT6911_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, LT6911_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, LT6911_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, LT6911_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + (void) ViPipe; + (void) pstInitAttr; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return lt6911_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsLT6911_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = CVI_NULL, + .pfnRestart = CVI_NULL, + .pfnMirrorFlip = CVI_NULL, + .pfnWriteReg = lt6911_write, + .pfnReadReg = lt6911_read, + .pfnSetBusInfo = lt6911_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sensor_probe, +}; \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos_ex.h new file mode 100644 index 000000000..b3863cadc --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos_ex.h @@ -0,0 +1,63 @@ +#ifndef __LT6911_CMOS_EX_H_ +#define __LT6911_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +#ifndef UNUSED +#define UNUSED(x) ((void)(x)) +#endif + + +enum lt6911_linear_regs_e { + LINEAR_REGS_NUM +}; + + +typedef enum _LT6911_MODE_E { + LT6911_MODE_NONE, + LT6911_MODE_NORMAL, + LT6911_MODE_NUM +} LT6911_MODE_E; + + +typedef struct _LT6911_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + char name[64]; +} LT6911_MODE_S; + + +extern CVI_U8 lt6911_i2c_addr; +extern const CVI_U32 lt6911_addr_byte; +extern const CVI_U32 lt6911_data_byte; +extern void lt6911_init(VI_PIPE ViPipe); +extern void lt6911_exit(VI_PIPE ViPipe); +extern void lt6911_standby(VI_PIPE ViPipe); +extern void lt6911_restart(VI_PIPE ViPipe); +extern int lt6911_write(VI_PIPE ViPipe, int addr, int data); +extern int lt6911_read(VI_PIPE ViPipe, int addr); +extern void lt6911_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int lt6911_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __LT6911_CMOS_EX_H_ */ \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos_param.h new file mode 100644 index 000000000..46ccbdd7d --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_cmos_param.h @@ -0,0 +1,75 @@ +#ifndef __LT6911_CMOS_PARAM_H_ +#define __LT6911_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "lt6911_cmos_ex.h" + +// not real time resolution +#define WIDTH 3840//3840 1920 +#define HEIGHT 2160//2160 1080 + +static LT6911_MODE_S g_astLt6911_mode[LT6911_MODE_NUM] = { + [LT6911_MODE_NORMAL] = { + .name = "lt6911", + .astImg[0] = { + .stSnsSize = { + .u32Width = WIDTH, + .u32Height = HEIGHT, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = WIDTH, + .u32Height = HEIGHT, + }, + .stMaxSize = { + .u32Width = WIDTH, + .u32Height = HEIGHT, + }, + }, + }, +}; + +struct combo_dev_attr_s lt6911_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_600M, + .mipi_attr = { + .raw_data_type = YUV422_8BIT, + .lane_id = {2, 0, 1, 3, 4}, //3, 0, 1, 2, 4 ; 1, 4, 3, 2, 0 2, 0, 1, 3, 4 3, 1, 2, 4, 0 + .pn_swap = {1, 1, 1, 1, 1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_NONE, + }, + .devno = 1, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __LT6911_CMOS_PARAM_H_ */ \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_sensor_ctl.c new file mode 100644 index 000000000..3df0b4eb6 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/lontium_lt6911/lt6911_sensor_ctl.c @@ -0,0 +1,215 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "lt6911_cmos_ex.h" + +#define LT6911_I2C_DEV 3 +#define LT6911_I2C_BANK_ADDR 0xff + +CVI_U8 lt6911_i2c_addr = 0x2b; +const CVI_U32 lt6911_addr_byte = 1; +const CVI_U32 lt6911_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int lt6911_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", LT6911_I2C_DEV); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", LT6911_I2C_DEV); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, lt6911_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int lt6911_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + + +int lt6911_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + char buf[8]; + int idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (lt6911_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, lt6911_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, lt6911_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (lt6911_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "vipipe:%d i2c r 0x%x = 0x%x\n", ViPipe, addr, data); + return data; +} + +int lt6911_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (lt6911_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + } + buf[idx] = addr & 0xff; + idx++; + + + if (lt6911_data_byte == 2) { + buf[idx] = (data >> 8) & 0xff; + idx++; + } + buf[idx] = data & 0xff; + idx++; + + ret = write(g_fd[ViPipe], buf, lt6911_addr_byte + lt6911_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + // ret = read(g_fd[ViPipe], buf, lt6911_addr_byte + lt6911_data_byte); + syslog(LOG_DEBUG, "ViPipe:%d i2c w 0x%x 0x%x\n", ViPipe, addr, data); + return CVI_SUCCESS; +} + +static int lt6911_i2c_read(VI_PIPE ViPipe, int RegAddr) +{ + uint8_t bank = RegAddr >> 8; + uint8_t addr = RegAddr & 0xff; + + lt6911_write_register(ViPipe, LT6911_I2C_BANK_ADDR, bank); + return lt6911_read_register(ViPipe, addr); +} + +static int lt6911_i2c_write(VI_PIPE ViPipe, int RegAddr, int data) +{ + uint8_t bank = RegAddr >> 8; + uint8_t addr = RegAddr & 0xff; + + lt6911_write_register(ViPipe, LT6911_I2C_BANK_ADDR, bank); + return lt6911_write_register(ViPipe, addr, data); +} + +int lt6911_read(VI_PIPE ViPipe, int addr) +{ + int data = 0; + + lt6911_i2c_write(ViPipe, 0x80ee, 0x01); + data = lt6911_i2c_read(ViPipe, addr); + lt6911_i2c_write(ViPipe, 0x80ee, 0x00); + return data; +} + +int lt6911_write(VI_PIPE ViPipe, int addr, int data) +{ + lt6911_i2c_write(ViPipe, 0x80ee, 0x01); + lt6911_i2c_write(ViPipe, addr, data); + lt6911_i2c_write(ViPipe, 0x80ee, 0x00); + return CVI_SUCCESS; +} + +#define LT6911_CHIP_ID_ADDR_H 0xa000 +#define LT6911_CHIP_ID_ADDR_L 0xa001 +#define LT6911_CHIP_ID 0x1605 + +int lt6911_probe(VI_PIPE ViPipe) +{ + int nVal; + int nVal2; + + usleep(50); + if (lt6911_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = lt6911_read(ViPipe, LT6911_CHIP_ID_ADDR_H); + nVal2 = lt6911_read(ViPipe, LT6911_CHIP_ID_ADDR_L); + if (nVal < 0 || nVal2 < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + printf("data:%02x %02x\n", nVal, nVal2); + if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != LT6911_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void lt6911_init(VI_PIPE ViPipe) +{ + lt6911_i2c_init(ViPipe); +} + +void lt6911_exit(VI_PIPE ViPipe) +{ + lt6911_i2c_exit(ViPipe); +} \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/Makefile b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/Makefile new file mode 100644 index 000000000..a91b7c4b1 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_sc2331_1L.a +TARGET_SO = $(MW_LIB)/libsns_sc2331_1L.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos.c b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos.c new file mode 100644 index 000000000..a15f1b242 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos.c @@ -0,0 +1,990 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" + +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "sc2331_1L_cmos_ex.h" +#include "sc2331_1L_cmos_param.h" + + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define SC2331_1L_ID 0xCB5C +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastSC2331_1L[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define SC2331_1L_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastSC2331_1L[dev]) +#define SC2331_1L_SENSOR_SET_CTX(dev, pstCtx) (g_pastSC2331_1L[dev] = pstCtx) +#define SC2331_1L_SENSOR_RESET_CTX(dev) (g_pastSC2331_1L[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunSC2331_1L_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 2}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16SC2331_1L_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16SC2331_1L_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +ISP_SNS_MIRRORFLIP_TYPE_E g_aeSc2331_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****SC2331_1L Lines Range*****/ +#define SC2331_1L_FULL_LINES_MAX (0x7FFF) + +/*****SC2331_1L Register Address*****/ +#define SC2331_1L_EXP_H_ADDR (0x3e00) +#define SC2331_1L_EXP_M_ADDR (0x3e01) +#define SC2331_1L_EXP_L_ADDR (0x3e02) + +#define SC2331_1L_AGAIN_H_ADDR (0x3e08) + +#define SC2331_1L_DGAIN_H_ADDR (0x3e06) +#define SC2331_1L_DGAIN_L_ADDR (0x3e07) + +#define SC2331_1L_VMAX_H_ADDR (0x320e) +#define SC2331_1L_VMAX_L_ADDR (0x320f) + +#define SC2331_1L_GAIN_DPC_ADDR (0x5799) +#define SC2331_1L_HOLD_ADDR (0x3812) + +#define SC2331_1L_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080) + +#define SC2331_1L_EXPACCURACY (0.5) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const SC2331_1L_MODE_S *pstMode; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astSC2331_1L_mode[pstSnsState->u8ImgMode]; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = SC2331_1L_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = SC2331_1L_EXPACCURACY; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u16Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u16Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u16Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u16Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max; + pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min; + pstAeSnsDft->u32MaxIntTimeTarget = pstAeSnsDft->u32MaxIntTime; + pstAeSnsDft->u32MinIntTimeTarget = pstAeSnsDft->u32MinIntTime; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case SC2331_1L_MODE_1920X1080P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > SC2331_1L_FULL_LINES_MAX) ? SC2331_1L_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_H_ADDR].u32Data = ((u32VMAX & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_L_ADDR].u32Data = (u32VMAX & 0xFF); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = 2 * pstSnsState->u32FLStd - 13; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32TmpIntTime, u32MinTime, u32MaxTime; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear exposure reg range: + * min : 3 + * max : 2 * vts - 10 + * step : 1 + */ + u32MinTime = 2; + u32MaxTime = 2 * pstSnsState->au32FL[0] - 13; + u32TmpIntTime = (u32IntTime[0] > u32MaxTime) ? u32MaxTime : u32IntTime[0]; + u32TmpIntTime = (u32TmpIntTime < u32MinTime) ? u32MinTime : u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_EXP_H_ADDR].u32Data = ((u32TmpIntTime & 0xF000) >> 12); + pstSnsRegsInfo->astI2cData[LINEAR_EXP_M_ADDR].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4); + pstSnsRegsInfo->astI2cData[LINEAR_EXP_L_ADDR].u32Data = ((u32TmpIntTime & 0x000F) << 4); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; + +} + +typedef struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +} gain_tbl_info_s; + +static struct gain_tbl_info_s AgainInfo[6] = { + { + .gainMax = 2031, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 4064, + .idxBase = 64, + .regGain = 0x08, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 8128, + .idxBase = 128, + .regGain = 0x09, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 16256, + .idxBase = 192, + .regGain = 0x0b, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 32512, + .idxBase = 256, + .regGain = 0x0f, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 32768, + .idxBase = 320, + .regGain = 0x1f, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, +}; +static CVI_U32 Again_table[321] = { + 1024, 1040, 1055, 1072, 1088, 1103, 1120, 1135, 1152, 1168, 1183, 1200, 1216, 1231, 1248, 1263, 1280, + 1296, 1311, 1328, 1344, 1359, 1376, 1391, 1408, 1424, 1439, 1456, 1472, 1487, 1504, 1519, 1536, 1552, + 1567, 1584, 1600, 1615, 1632, 1647, 1664, 1680, 1695, 1712, 1728, 1743, 1760, 1775, 1792, 1808, 1823, + 1840, 1856, 1871, 1888, 1903, 1920, 1936, 1951, 1968, 1984, 1999, 2016, 2031, 2048, 2079, 2112, 2144, + 2176, 2207, 2240, 2272, 2304, 2335, 2368, 2400, 2432, 2463, 2496, 2528, 2560, 2591, 2624, 2656, 2688, + 2719, 2752, 2784, 2816, 2847, 2880, 2912, 2944, 2975, 3008, 3040, 3072, 3103, 3136, 3168, 3200, 3231, + 3264, 3296, 3328, 3359, 3392, 3424, 3456, 3487, 3520, 3552, 3584, 3615, 3648, 3680, 3712, 3743, 3776, + 3808, 3840, 3871, 3904, 3936, 3968, 3999, 4032, 4064, 4096, 4160, 4224, 4288, 4352, 4416, 4480, 4544, + 4608, 4672, 4736, 4800, 4864, 4928, 4992, 5056, 5120, 5184, 5248, 5312, 5376, 5440, 5504, 5568, 5632, + 5696, 5760, 5824, 5888, 5952, 6016, 6080, 6144, 6208, 6272, 6336, 6400, 6464, 6528, 6592, 6656, 6720, + 6784, 6848, 6912, 6976, 7040, 7104, 7168, 7232, 7296, 7360, 7424, 7488, 7552, 7616, 7680, 7744, 7808, + 7872, 7936, 8000, 8064, 8128, 8192, 8320, 8448, 8576, 8704, 8832, 8960, 9088, 9216, 9344, 9472, 9600, + 9728, 9856, 9984, 10112, 10240, 10368, 10496, 10624, 10752, 10880, 11008, 11136, 11264, 11392, 11520, + 11648, 11776, 11904, 12032, 12160, 12288, 12416, 12544, 12672, 12800, 12928, 13056, 13184, 13312, 13440, + 13568, 13696, 13824, 13952, 14080, 14208, 14336, 14464, 14592, 14720, 14848, 14976, 15104, 15232, 15360, + 15488, 15616, 15744, 15872, 16000, 16128, 16256, 16384, 16640, 16896, 17152, 17408, 17664, 17920, 18176, + 18432, 18688, 18944, 19200, 19456, 19712, 19968, 20224, 20480, 20736, 20992, 21248, 21504, 21760, 22016, + 22272, 22528, 22784, 23040, 23296, 23552, 23808, 24064, 24320, 24576, 24832, 25088, 25344, 25600, 25856, + 26112, 26368, 26624, 26880, 27136, 27392, 27648, 27904, 28160, 28416, 28672, 28928, 29184, 29440, 29696, + 29952, 30208, 30464, 30720, 30976, 31232, 31488, 31744, 32000, 32256, 32512, 32768 +}; + +static struct gain_tbl_info_s DgainInfo[3] = { + { + .gainMax = 2031, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 4064, + .idxBase = 64, + .regGain = 0x01, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, + { + .gainMax = 4096, + .idxBase = 128, + .regGain = 0x03, + .regGainFineBase = 0x80, + .regGainFineStep = 2, + }, +}; + +static CVI_U32 Dgain_table[129] = { + 1024, 1040, 1055, 1072, 1088, 1103, 1120, 1135, 1152, 1168, 1183, 1200, 1216, 1231, 1248, + 1263, 1280, 1296, 1311, 1328, 1344, 1359, 1376, 1391, 1408, 1424, 1439, 1456, 1472, 1487, + 1504, 1519, 1536, 1552, 1567, 1584, 1600, 1615, 1632, 1647, 1664, 1680, 1695, 1712, 1728, + 1743, 1760, 1775, 1792, 1808, 1823, 1840, 1856, 1871, 1888, 1903, 1920, 1936, 1951, 1968, + 1984, 1999, 2016, 2031, 2048, 2079, 2112, 2144, 2176, 2207, 2240, 2272, 2304, 2335, 2368, + 2400, 2432, 2463, 2496, 2528, 2560, 2591, 2624, 2656, 2688, 2719, 2752, 2784, 2816, 2847, + 2880, 2912, 2944, 2975, 3008, 3040, 3072, 3103, 3136, 3168, 3200, 3231, 3264, 3296, 3328, + 3359, 3392, 3424, 3456, 3487, 3520, 3552, 3584, 3615, 3648, 3680, 3712, 3743, 3776, 3808, + 3840, 3871, 3904, 3936, 3968, 3999, 4032, 4064, 4096 +}; + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + int i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + if (*pu32AgainLin >= Again_table[320]) { + *pu32AgainLin = Again_table[320]; + *pu32AgainDb = 320; + return CVI_SUCCESS; + } + + for (i = 1; i < 321; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + int i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[128]) { + *pu32DgainLin = Dgain_table[128]; + *pu32DgainDb = 128; + return CVI_SUCCESS; + } + + for (i = 1; i < 129; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + + /* find Again register setting. */ + tbl_num = sizeof(AgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &AgainInfo[i]; + + if (u32Again >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_H_ADDR].u32Data = (info->regGain & 0xFF); + u32Again = info->regGainFineBase + (u32Again - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_L_ADDR].u32Data = (u32Again & 0xFF); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H_ADDR].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L_ADDR].u32Data = (u32Dgain & 0xFF); + + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + //pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + //pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const SC2331_1L_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astSC2331_1L_mode[pstSnsState->u8ImgMode]; + + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = SC2331_1L_MODE_1920X1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunSC2331_1L_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = sc2331_1L_i2c_addr; + pstI2c_data[i].u32AddrByteNum = sc2331_1L_addr_byte; + pstI2c_data[i].u32DataByteNum = sc2331_1L_data_byte; + } + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + //Linear Mode Regs + pstI2c_data[LINEAR_EXP_H_ADDR].u32RegAddr = SC2331_1L_EXP_H_ADDR; + pstI2c_data[LINEAR_EXP_M_ADDR].u32RegAddr = SC2331_1L_EXP_M_ADDR; + pstI2c_data[LINEAR_EXP_L_ADDR].u32RegAddr = SC2331_1L_EXP_L_ADDR; + pstI2c_data[LINEAR_AGAIN_H_ADDR].u32RegAddr = SC2331_1L_AGAIN_H_ADDR; + pstI2c_data[LINEAR_AGAIN_L_ADDR].u32RegAddr = SC2331_1L_DGAIN_L_ADDR; + pstI2c_data[LINEAR_DGAIN_H_ADDR].u32RegAddr = SC2331_1L_DGAIN_H_ADDR; + pstI2c_data[LINEAR_DGAIN_L_ADDR].u32RegAddr = SC2331_1L_DGAIN_L_ADDR; + pstI2c_data[LINEAR_VMAX_H_ADDR].u32RegAddr = SC2331_1L_VMAX_H_ADDR; + pstI2c_data[LINEAR_VMAX_L_ADDR].u32RegAddr = SC2331_1L_VMAX_L_ADDR; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (SC2331_1L_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = SC2331_1L_MODE_1920X1080P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + if (pstSnsState->bInit == CVI_TRUE && g_aeSc2331_MirrorFip[ViPipe] != eSnsMirrorFlip) { + sc2331_1L_mirror_flip(ViPipe, eSnsMirrorFlip); + g_aeSc2331_MirrorFip[ViPipe] = eSnsMirrorFlip; + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const SC2331_1L_MODE_S *pstMode = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = SC2331_1L_MODE_1920X1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astSC2331_1L_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &sc2331_1L_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astSC2331_1L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &sc2331_1L_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = sc2331_1L_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = sc2331_1L_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 sc2331_1L_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunSC2331_1L_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + SC2331_1L_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC2331_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + SC2331_1L_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = SC2331_1L_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, SC2331_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, SC2331_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, SC2331_1L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16SC2331_1L_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16SC2331_1L_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsSC2331_1L_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = sc2331_1L_standby, + .pfnRestart = sc2331_1L_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = sc2331_1L_write_register, + .pfnReadReg = sc2331_1L_read_register, + .pfnSetBusInfo = sc2331_1L_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sc2331_1L_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos_ex.h new file mode 100644 index 000000000..9678e34ad --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos_ex.h @@ -0,0 +1,80 @@ +#ifndef __SC2331_1L_CMOS_EX_H_ +#define __SC2331_1L_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum sc2331_1L_linear_regs_e { + LINEAR_EXP_H_ADDR, + LINEAR_EXP_M_ADDR, + LINEAR_EXP_L_ADDR, + LINEAR_AGAIN_H_ADDR, + LINEAR_AGAIN_L_ADDR, + LINEAR_DGAIN_H_ADDR, + LINEAR_DGAIN_L_ADDR, + LINEAR_VMAX_H_ADDR, + LINEAR_VMAX_L_ADDR, + LINEAR_REGS_NUM +}; + +typedef enum _SC2331_1L_MODE_E { + SC2331_1L_MODE_1920X1080P30 = 0, + SC2331_1L_MODE_LINEAR_NUM, + SC2331_1L_MODE_NUM +} SC2331_1L_MODE_E; + +typedef struct _SC2331_1L_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + char name[64]; +} SC2331_1L_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastSC2331_1L[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunSC2331_1L_BusInfo[]; +extern CVI_U16 g_au16SC2331_1L_GainMode[]; +extern CVI_U16 g_au16SC2331_1L_L2SMode[]; +extern const CVI_U8 sc2331_1L_i2c_addr; +extern const CVI_U32 sc2331_1L_addr_byte; +extern const CVI_U32 sc2331_1L_data_byte; +extern void sc2331_1L_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern void sc2331_1L_init(VI_PIPE ViPipe); +extern void sc2331_1L_exit(VI_PIPE ViPipe); +extern void sc2331_1L_standby(VI_PIPE ViPipe); +extern void sc2331_1L_restart(VI_PIPE ViPipe); +extern int sc2331_1L_write_register(VI_PIPE ViPipe, int addr, int data); +extern int sc2331_1L_read_register(VI_PIPE ViPipe, int addr); +extern int sc2331_1L_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC2331_1L_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos_param.h new file mode 100644 index 000000000..4ad8b58cd --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_cmos_param.h @@ -0,0 +1,125 @@ +#ifndef __SC2331_1L_CMOS_PARAM_H_ +#define __SC2331_1L_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc2331_1L_cmos_ex.h" + +static const SC2331_1L_MODE_S g_astSC2331_1L_mode[SC2331_1L_MODE_NUM] = { + [SC2331_1L_MODE_1920X1080P30] = { + .name = "1080p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 0.51, /* 1125 * 30 / 0x7FFF */ + .u32HtsDef = 2560, + .u32VtsDef = 1530, + .stExp[0] = { + .u16Min = 2,//3 + .u16Max = 1530*2 - 13, + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u16Min = 1024, + .u16Max = 32768, + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[0] = { + .u16Min = 1024, + .u16Max = 4096, + .u16Def = 1024, + .u16Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {256, 256, 256, 256, 0, 0, 0, 0 + #ifdef ARCH_CV182X + , 1092, 1092, 1092, 1092 + #endif + }, + .stAuto = { + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + #ifdef ARCH_CV182X + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + #endif + }, + }, +}; + +struct combo_dev_attr_s sc2331_1L_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {3, 2, -1, -1, -1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC2331_1L_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_sensor_ctl.c new file mode 100644 index 000000000..fc098a946 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2331_1L/sc2331_1L_sensor_ctl.c @@ -0,0 +1,388 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "cvi_sns_ctrl.h" +#include "sc2331_1L_cmos_ex.h" + +#define SC2331_1L_CHIP_ID_HI_ADDR 0x3107 +#define SC2331_1L_CHIP_ID_LO_ADDR 0x3108 +#define SC2331_1L_CHIP_ID 0xcb5c + +static void sc2331_1L_linear_1080p30_init(VI_PIPE ViPipe); + +const CVI_U8 sc2331_1L_i2c_addr = 0x30; /* I2C Address of SC2331_1L */ +const CVI_U32 sc2331_1L_addr_byte = 2; +const CVI_U32 sc2331_1L_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int sc2331_1L_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunSC2331_1L_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, sc2331_1L_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int sc2331_1L_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int sc2331_1L_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (sc2331_1L_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, sc2331_1L_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, sc2331_1L_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (sc2331_1L_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int sc2331_1L_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (sc2331_1L_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (sc2331_1L_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, sc2331_1L_addr_byte + sc2331_1L_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void sc2331_1L_prog(VI_PIPE ViPipe, int *rom) +{ + int i = 0; + + while (1) { + int lookup = rom[i++]; + int addr = (lookup >> 16) & 0xFFFF; + int data = lookup & 0xFFFF; + + if (addr == 0xFFFE) + delay_ms(data); + else if (addr != 0xFFFF) + sc2331_1L_write_register(ViPipe, addr, data); + } +} + +void sc2331_1L_standby(VI_PIPE ViPipe) +{ + sc2331_1L_write_register(ViPipe, 0x0100, 0x00); +} + +void sc2331_1L_restart(VI_PIPE ViPipe) +{ + sc2331_1L_write_register(ViPipe, 0x0100, 0x00); + delay_ms(20); + sc2331_1L_write_register(ViPipe, 0x0100, 0x01); +} + +void sc2331_1L_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastSC2331_1L[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + if (g_pastSC2331_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].bUpdate == CVI_TRUE) { + sc2331_1L_write_register(ViPipe, + g_pastSC2331_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastSC2331_1L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } + } +} + +void sc2331_1L_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = 0; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x6; + break; + case ISP_SNS_FLIP: + val |= 0x60; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x66; + break; + default: + return; + } + + sc2331_1L_write_register(ViPipe, 0x3221, val); +} + + +int sc2331_1L_probe(VI_PIPE ViPipe) +{ +int nVal; + CVI_U16 chip_id; + + usleep(4*1000); + if (sc2331_1L_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = sc2331_1L_read_register(ViPipe, SC2331_1L_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = sc2331_1L_read_register(ViPipe, SC2331_1L_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != SC2331_1L_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + +// printf("======%d\n",ViPipe); + return CVI_SUCCESS; +} + + + +/* 1080P30 and 1080P25 */ +static void sc2331_1L_linear_1080p30_init(VI_PIPE ViPipe) +{ + sc2331_1L_write_register(ViPipe, 0x0103, 0x01); + sc2331_1L_write_register(ViPipe, 0x0100, 0x00); + sc2331_1L_write_register(ViPipe, 0x36e9, 0x80); + sc2331_1L_write_register(ViPipe, 0x37f9, 0x80); + sc2331_1L_write_register(ViPipe, 0x3018, 0x1a); + sc2331_1L_write_register(ViPipe, 0x3019, 0x0e); + sc2331_1L_write_register(ViPipe, 0x301f, 0x20); + sc2331_1L_write_register(ViPipe, 0x3258, 0x0e); + sc2331_1L_write_register(ViPipe, 0x3301, 0x06); + sc2331_1L_write_register(ViPipe, 0x3302, 0x10); + sc2331_1L_write_register(ViPipe, 0x3304, 0x68); + sc2331_1L_write_register(ViPipe, 0x3306, 0x90); + sc2331_1L_write_register(ViPipe, 0x3308, 0x18); + sc2331_1L_write_register(ViPipe, 0x3309, 0x80); + sc2331_1L_write_register(ViPipe, 0x330a, 0x01); + sc2331_1L_write_register(ViPipe, 0x330b, 0x48); + sc2331_1L_write_register(ViPipe, 0x330d, 0x18); + sc2331_1L_write_register(ViPipe, 0x331c, 0x02); + sc2331_1L_write_register(ViPipe, 0x331e, 0x59); + sc2331_1L_write_register(ViPipe, 0x331f, 0x71); + sc2331_1L_write_register(ViPipe, 0x3333, 0x10); + sc2331_1L_write_register(ViPipe, 0x3334, 0x40); + sc2331_1L_write_register(ViPipe, 0x3364, 0x56); + sc2331_1L_write_register(ViPipe, 0x3390, 0x08); + sc2331_1L_write_register(ViPipe, 0x3391, 0x09); + sc2331_1L_write_register(ViPipe, 0x3392, 0x0b); + sc2331_1L_write_register(ViPipe, 0x3393, 0x0a); + sc2331_1L_write_register(ViPipe, 0x3394, 0x2a); + sc2331_1L_write_register(ViPipe, 0x3395, 0x2a); + sc2331_1L_write_register(ViPipe, 0x3396, 0x48); + sc2331_1L_write_register(ViPipe, 0x3397, 0x49); + sc2331_1L_write_register(ViPipe, 0x3398, 0x4b); + sc2331_1L_write_register(ViPipe, 0x3399, 0x06); + sc2331_1L_write_register(ViPipe, 0x339a, 0x0a); + sc2331_1L_write_register(ViPipe, 0x339b, 0x30); + sc2331_1L_write_register(ViPipe, 0x339c, 0x48); + sc2331_1L_write_register(ViPipe, 0x33ad, 0x2c); + sc2331_1L_write_register(ViPipe, 0x33ae, 0x38); + sc2331_1L_write_register(ViPipe, 0x33b3, 0x40); + sc2331_1L_write_register(ViPipe, 0x349f, 0x02); + sc2331_1L_write_register(ViPipe, 0x34a6, 0x09); + sc2331_1L_write_register(ViPipe, 0x34a7, 0x0f); + sc2331_1L_write_register(ViPipe, 0x34a8, 0x30); + sc2331_1L_write_register(ViPipe, 0x34a9, 0x28); + sc2331_1L_write_register(ViPipe, 0x34f8, 0x5f); + sc2331_1L_write_register(ViPipe, 0x34f9, 0x28); + sc2331_1L_write_register(ViPipe, 0x3630, 0xc6); + sc2331_1L_write_register(ViPipe, 0x3633, 0x33); + sc2331_1L_write_register(ViPipe, 0x3637, 0x6b); + sc2331_1L_write_register(ViPipe, 0x363c, 0xc1); + sc2331_1L_write_register(ViPipe, 0x363e, 0xc2); + sc2331_1L_write_register(ViPipe, 0x3670, 0x2e); + sc2331_1L_write_register(ViPipe, 0x3674, 0xc5); + sc2331_1L_write_register(ViPipe, 0x3675, 0xc7); + sc2331_1L_write_register(ViPipe, 0x3676, 0xcb); + sc2331_1L_write_register(ViPipe, 0x3677, 0x44); + sc2331_1L_write_register(ViPipe, 0x3678, 0x48); + sc2331_1L_write_register(ViPipe, 0x3679, 0x48); + sc2331_1L_write_register(ViPipe, 0x367c, 0x08); + sc2331_1L_write_register(ViPipe, 0x367d, 0x0b); + sc2331_1L_write_register(ViPipe, 0x367e, 0x0b); + sc2331_1L_write_register(ViPipe, 0x367f, 0x0f); + sc2331_1L_write_register(ViPipe, 0x3690, 0x33); + sc2331_1L_write_register(ViPipe, 0x3691, 0x33); + sc2331_1L_write_register(ViPipe, 0x3692, 0x33); + sc2331_1L_write_register(ViPipe, 0x3693, 0x84); + sc2331_1L_write_register(ViPipe, 0x3694, 0x85); + sc2331_1L_write_register(ViPipe, 0x3695, 0x8d); + sc2331_1L_write_register(ViPipe, 0x3696, 0x9c); + sc2331_1L_write_register(ViPipe, 0x369c, 0x0b); + sc2331_1L_write_register(ViPipe, 0x369d, 0x0f); + sc2331_1L_write_register(ViPipe, 0x369e, 0x09); + sc2331_1L_write_register(ViPipe, 0x369f, 0x0b); + sc2331_1L_write_register(ViPipe, 0x36a0, 0x0f); + sc2331_1L_write_register(ViPipe, 0x36ec, 0x0c); + sc2331_1L_write_register(ViPipe, 0x370f, 0x01); + sc2331_1L_write_register(ViPipe, 0x3722, 0x05); + sc2331_1L_write_register(ViPipe, 0x3724, 0x20); + sc2331_1L_write_register(ViPipe, 0x3725, 0x91); + sc2331_1L_write_register(ViPipe, 0x3771, 0x05); + sc2331_1L_write_register(ViPipe, 0x3772, 0x05); + sc2331_1L_write_register(ViPipe, 0x3773, 0x05); + sc2331_1L_write_register(ViPipe, 0x377a, 0x0b); + sc2331_1L_write_register(ViPipe, 0x377b, 0x0f); + sc2331_1L_write_register(ViPipe, 0x3900, 0x19); + sc2331_1L_write_register(ViPipe, 0x3905, 0xb8); + sc2331_1L_write_register(ViPipe, 0x391b, 0x80); + sc2331_1L_write_register(ViPipe, 0x391c, 0x04); + sc2331_1L_write_register(ViPipe, 0x391d, 0x81); + sc2331_1L_write_register(ViPipe, 0x3933, 0xc0); + sc2331_1L_write_register(ViPipe, 0x3934, 0x08); + sc2331_1L_write_register(ViPipe, 0x3940, 0x72); + sc2331_1L_write_register(ViPipe, 0x3941, 0x00); + sc2331_1L_write_register(ViPipe, 0x3942, 0x00); + sc2331_1L_write_register(ViPipe, 0x3943, 0x09); + sc2331_1L_write_register(ViPipe, 0x3946, 0x10); + sc2331_1L_write_register(ViPipe, 0x3957, 0x86); + sc2331_1L_write_register(ViPipe, 0x3e01, 0x8b); + sc2331_1L_write_register(ViPipe, 0x3e02, 0xd0); + sc2331_1L_write_register(ViPipe, 0x3e08, 0x00); + sc2331_1L_write_register(ViPipe, 0x440e, 0x02); + sc2331_1L_write_register(ViPipe, 0x4509, 0x28); + sc2331_1L_write_register(ViPipe, 0x450d, 0x10); + sc2331_1L_write_register(ViPipe, 0x4819, 0x09); + sc2331_1L_write_register(ViPipe, 0x481b, 0x05); + sc2331_1L_write_register(ViPipe, 0x481d, 0x14); + sc2331_1L_write_register(ViPipe, 0x481f, 0x04); + sc2331_1L_write_register(ViPipe, 0x4821, 0x0a); + sc2331_1L_write_register(ViPipe, 0x4823, 0x05); + sc2331_1L_write_register(ViPipe, 0x4825, 0x04); + sc2331_1L_write_register(ViPipe, 0x4827, 0x05); + sc2331_1L_write_register(ViPipe, 0x4829, 0x08); + sc2331_1L_write_register(ViPipe, 0x5780, 0x66); + sc2331_1L_write_register(ViPipe, 0x578d, 0x40); + sc2331_1L_write_register(ViPipe, 0x5799, 0x06); + sc2331_1L_write_register(ViPipe, 0x36e9, 0x20); + sc2331_1L_write_register(ViPipe, 0x37f9, 0x27); + + sc2331_1L_default_reg_init(ViPipe); + + sc2331_1L_write_register(ViPipe, 0x0100, 0x01); + + // printf("ViPipe:%d,===SC2331_1L 1080P 30fps 10bit LINE Init OK!===\n", ViPipe); +} + +void sc2331_1L_init(VI_PIPE ViPipe) +{ + sc2331_1L_i2c_init(ViPipe); + + //linear mode only + sc2331_1L_linear_1080p30_init(ViPipe); + + g_pastSC2331_1L[ViPipe]->bInit = CVI_TRUE; +} + +void sc2331_1L_exit(VI_PIPE ViPipe) +{ + sc2331_1L_i2c_exit(ViPipe); +} \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/Makefile b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/Makefile new file mode 100644 index 000000000..5cdee09c9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_sc2336p.a +TARGET_SO = $(MW_LIB)/libsns_sc2336p.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJ) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos.c b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos.c new file mode 100644 index 000000000..27c5fb7bf --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos.c @@ -0,0 +1,905 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "sc2336p_cmos_ex.h" +#include "sc2336p_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define SC2336P_ID 35 +#define SENSOR_SC2336P_WIDTH 1920 +#define SENSOR_SC2336P_HEIGHT 1080 +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastSC2336P[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define SC2336P_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastSC2336P[dev]) +#define SC2336P_SENSOR_SET_CTX(dev, pstCtx) (g_pastSC2336P[dev] = pstCtx) +#define SC2336P_SENSOR_RESET_CTX(dev) (g_pastSC2336P[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunSC2336P_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16SC2336P_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16SC2336P_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +SC2336P_STATE_S g_astSC2336P_State[VI_MAX_PIPE_NUM] = {{0} }; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ + +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****SC2336P Lines Range*****/ +#define SC2336P_FULL_LINES_MAX (0xFFFF) + +/*****SC2336P Register Address*****/ +#define SC2336P_SHS1_0_ADDR 0x3E00 +#define SC2336P_SHS1_1_ADDR 0x3E01 +#define SC2336P_SHS1_2_ADDR 0x3E02 +#define SC2336P_AGAIN0_ADDR 0x3E09 +#define SC2336P_DGAIN0_ADDR 0x3E06 +#define SC2336P_VMAX_ADDR 0x320E +#define SC2336P_TABLE_END 0xFFFF + +#define SC2336P_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const SC2336P_MODE_S *pstMode; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astSC2336P_mode[pstSnsState->u8ImgMode]; +#if 0 + memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S)); +#endif + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = SC2336P_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_DB; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + default: + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u16Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u16Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u16Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u16Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max; + pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astSC2336P_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astSC2336P_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astSC2336P_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case SC2336P_MODE_1080P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > SC2336P_FULL_LINES_MAX) ? SC2336P_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_ADDR].u32Data = ((u32VMAX & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_ADDR].u32Data = (u32VMAX & 0xFF); + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 6; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if (WDR_MODE_2To1_LINE != pstSnsState->enWDRMode) { + CVI_U32 u32TmpIntTime = u32IntTime[0]; + /* linear exposure reg range: + * min : 1 + * max : (vts - 6) + * step : 1 + */ + u32TmpIntTime = (u32TmpIntTime > (pstSnsState->au32FL[0] - 6)) ? + (pstSnsState->au32FL[0] - 6) : u32TmpIntTime; + if (!u32TmpIntTime) + u32TmpIntTime = 1; + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_ADDR].u32Data = ((u32TmpIntTime & 0xF000) >> 12); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_ADDR].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_2_ADDR].u32Data = (u32TmpIntTime & 0xF) << 4; + } + + return CVI_SUCCESS; + +} + +struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +}; + +static CVI_U32 Again_table[] = { + 1024, 2048, 4096, 8192, 16384, 32768 +}; + +static CVI_U32 AgainReg[] = { + 0x00, 0x08, 0x09, 0x0b, 0x0f, 0x1f +}; + +static struct gain_tbl_info_s DgainInfo[] = { + { + .gainMax = 2016, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x01, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4096, + .idxBase = 64, + .regGain = 0x03, + .regGainFineBase = 0x80, + .regGainFineStep = 0, + }, +}; + +static CVI_U32 Dgain_table[] = { + 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, + 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, + 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, + 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, + 4096, +}; + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 tableSize = sizeof(Again_table) / sizeof(CVI_U32); + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= Again_table[tableSize - 1]) { + *pu32AgainLin = Again_table[tableSize - 1]; + *pu32AgainDb = AgainReg[tableSize - 1]; + return CVI_SUCCESS; + } + + for (CVI_U32 i = 1; i < tableSize; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = AgainReg[i - 1]; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 tableSize = sizeof(Dgain_table) / sizeof(CVI_U32); + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[tableSize - 1]) { + *pu32DgainLin = Dgain_table[tableSize - 1]; + *pu32DgainDb = tableSize - 1; + return CVI_SUCCESS; + } + + for (CVI_U32 i = 1; i < tableSize; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + CVI_S32 i = 0, tbl_num = 0; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + + /* Again. */ + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_0_ADDR].u32Data = (u32Again & 0xFF); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_0_ADDR].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_1_ADDR].u32Data = (u32Dgain & 0xFF); + } + return CVI_SUCCESS; +} + + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + // pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + // pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const SC2336P_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astSC2336P_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = SC2336P_MODE_1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astSC2336P_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunSC2336P_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = sc2336p_i2c_addr; + pstI2c_data[i].u32AddrByteNum = sc2336p_addr_byte; + pstI2c_data[i].u32DataByteNum = sc2336p_data_byte; + } + + //DOL 2t1 Mode Regs + switch (pstSnsState->enWDRMode) { + case WDR_MODE_2To1_LINE: + break; + default: + //Linear Mode Regs + pstI2c_data[LINEAR_SHS1_0_ADDR].u32RegAddr = SC2336P_SHS1_0_ADDR; + pstI2c_data[LINEAR_SHS1_1_ADDR].u32RegAddr = SC2336P_SHS1_1_ADDR; + pstI2c_data[LINEAR_SHS1_2_ADDR].u32RegAddr = SC2336P_SHS1_2_ADDR; + pstI2c_data[LINEAR_AGAIN_0_ADDR].u32RegAddr = SC2336P_AGAIN0_ADDR; + pstI2c_data[LINEAR_DGAIN_0_ADDR].u32RegAddr = SC2336P_DGAIN0_ADDR; + pstI2c_data[LINEAR_DGAIN_1_ADDR].u32RegAddr = SC2336P_DGAIN0_ADDR + 1; + pstI2c_data[LINEAR_VMAX_0_ADDR].u32RegAddr = SC2336P_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1_ADDR].u32RegAddr = SC2336P_VMAX_ADDR + 1; + + break; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (SC2336P_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = SC2336P_MODE_1080P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const SC2336P_MODE_S *pstMode = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = SC2336P_MODE_1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astSC2336P_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &sc2336p_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astSC2336P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astSC2336P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &sc2336p_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = sc2336p_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = sc2336p_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 sc2336p_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunSC2336P_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + SC2336P_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC2336P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + SC2336P_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = SC2336P_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, SC2336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, SC2336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, SC2336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16SC2336P_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16SC2336P_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsSC2336P_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = sc2336p_standby, + .pfnRestart = sc2336p_restart, + .pfnMirrorFlip = sc2336p_mirror_flip, + .pfnWriteReg = sc2336p_write_register, + .pfnReadReg = sc2336p_read_register, + .pfnSetBusInfo = sc2336p_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sc2336p_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos_ex.h new file mode 100644 index 000000000..45c005be5 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos_ex.h @@ -0,0 +1,85 @@ +#ifndef __SC2336P_CMOS_EX_H_ +#define __SC2336P_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum sc2336p_linear_regs_e { + LINEAR_SHS1_0_ADDR, + LINEAR_SHS1_1_ADDR, + LINEAR_SHS1_2_ADDR, + LINEAR_AGAIN_0_ADDR, + LINEAR_DGAIN_0_ADDR, + LINEAR_DGAIN_1_ADDR, + LINEAR_VMAX_0_ADDR, + LINEAR_VMAX_1_ADDR, + LINEAR_REGS_NUM +}; + + +typedef enum _SC2336P_MODE_E { + SC2336P_MODE_1080P30 = 0, + SC2336P_MODE_LINEAR_NUM, + SC2336P_MODE_NUM +} SC2336P_MODE_E; + +typedef struct _SC2336P_STATE_S { + CVI_U32 u32Sexp_MAX; /* (2*{16’h3e23,16’h3e24} – 'd10)/2 */ +} SC2336P_STATE_S; + +typedef struct _SC2336P_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + CVI_U16 u16SexpMaxReg; /* {16’h3e23,16’h3e24} */ + char name[64]; +} SC2336P_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastSC2336P[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunSC2336P_BusInfo[]; +extern CVI_U16 g_au16SC2336P_GainMode[]; +extern CVI_U16 g_au16SC2336P_L2SMode[]; +extern const CVI_U8 sc2336p_i2c_addr; +extern const CVI_U32 sc2336p_addr_byte; +extern const CVI_U32 sc2336p_data_byte; +extern void sc2336p_init(VI_PIPE ViPipe); +extern void sc2336p_exit(VI_PIPE ViPipe); +extern void sc2336p_standby(VI_PIPE ViPipe); +extern void sc2336p_restart(VI_PIPE ViPipe); +extern int sc2336p_write_register(VI_PIPE ViPipe, int addr, int data); +extern int sc2336p_read_register(VI_PIPE ViPipe, int addr); +extern void sc2336p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int sc2336p_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC2336P_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos_param.h new file mode 100644 index 000000000..feebdae9a --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_cmos_param.h @@ -0,0 +1,125 @@ +#ifndef __SC2336P_CMOS_PARAM_H_ +#define __SC2336P_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc2336p_cmos_ex.h" + +static const SC2336P_MODE_S g_astSC2336P_mode[SC2336P_MODE_NUM] = { + [SC2336P_MODE_1080P30] = { + .name = "1080p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 0.51, /* 1125 * 30 / 0xFFFF*/ + .u32HtsDef = 2560, + .u32VtsDef = 1125, + .stExp[0] = { + .u16Min = 1, + .u16Max = 12184 - 6, + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u16Min = 1024, + .u16Max = 32768, + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[0] = { + .u16Min = 1024, + .u16Max = 4096, + .u16Def = 1024, + .u16Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {260, 260, 260, 260, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1093, 1093, 1093, 1093 +#endif + }, + .stAuto = { + {260, 260, 260, 260, 260, 252, 252, 252, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 252, 252, 252, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 252, 252, 252, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 252, 252, 252, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1093, 1093, 1093, 1093, 1093, 1091, 1091, 1091, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1091, 1091, 1091, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1091, 1091, 1091, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1091, 1091, 1091, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, +#endif + }, + }, +}; + +struct combo_dev_attr_s sc2336p_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {2, 1, 3, -1, -1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + } + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC2336P_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_sensor_ctl.c new file mode 100644 index 000000000..28af2ec0f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc2336p/sc2336p_sensor_ctl.c @@ -0,0 +1,410 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc2336p_cmos_ex.h" + +static void sc2336p_linear_1080p30_init(VI_PIPE ViPipe); + +const CVI_U8 sc2336p_i2c_addr = 0x30; /* I2C Address of SC2336P */ +const CVI_U32 sc2336p_addr_byte = 2; +const CVI_U32 sc2336p_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int sc2336p_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunSC2336P_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, sc2336p_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int sc2336p_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int sc2336p_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + char buf[8]; + int idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (sc2336p_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, sc2336p_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, sc2336p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (sc2336p_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int sc2336p_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (sc2336p_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (sc2336p_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, sc2336p_addr_byte + sc2336p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void sc2336p_prog(VI_PIPE ViPipe, int *rom) +{ + int i = 0; + + while (1) { + int lookup = rom[i++]; + int addr = (lookup >> 16) & 0xFFFF; + int data = lookup & 0xFFFF; + + if (addr == 0xFFFE) + delay_ms(data); + else if (addr != 0xFFFF) + sc2336p_write_register(ViPipe, addr, data); + } +} + +void sc2336p_standby(VI_PIPE ViPipe) +{ + sc2336p_write_register(ViPipe, 0x0100, 0x00); +} + +void sc2336p_restart(VI_PIPE ViPipe) +{ + sc2336p_write_register(ViPipe, 0x0100, 0x00); + delay_ms(20); + sc2336p_write_register(ViPipe, 0x0100, 0x01); +} + +void sc2336p_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastSC2336P[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + sc2336p_write_register(ViPipe, + g_pastSC2336P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastSC2336P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +#define SC2336P_CHIP_ID_HI_ADDR 0x3107 +#define SC2336P_CHIP_ID_LO_ADDR 0x3108 +#define SC2336P_CHIP_ID 0x9b3a + +void sc2336p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = 0; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x6; + break; + case ISP_SNS_FLIP: + val |= 0x60; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x66; + break; + default: + return; + } + + sc2336p_write_register(ViPipe, 0x3221, val); +} + +int sc2336p_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + usleep(4*1000); + if (sc2336p_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = sc2336p_read_register(ViPipe, SC2336P_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = sc2336p_read_register(ViPipe, SC2336P_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != SC2336P_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + return CVI_SUCCESS; +} + + +void sc2336p_init(VI_PIPE ViPipe) +{ + WDR_MODE_E enWDRMode; + CVI_BOOL bInit; + + bInit = g_pastSC2336P[ViPipe]->bInit; + enWDRMode = g_pastSC2336P[ViPipe]->enWDRMode; + + sc2336p_i2c_init(ViPipe); + + /* When sensor first init, config all registers */ + if (bInit == CVI_FALSE) { + if (enWDRMode == WDR_MODE_NONE) { + sc2336p_linear_1080p30_init(ViPipe); + } + } + /* When sensor switch mode(linear<->WDR or resolution), config different registers(if possible) */ + else { + if (enWDRMode == WDR_MODE_NONE) { + sc2336p_linear_1080p30_init(ViPipe); + } + } + g_pastSC2336P[ViPipe]->bInit = CVI_TRUE; +} + +void sc2336p_exit(VI_PIPE ViPipe) +{ + sc2336p_i2c_exit(ViPipe); +} + +/* 1080P30 and 1080P25 */ +static void sc2336p_linear_1080p30_init(VI_PIPE ViPipe) +{ + sc2336p_write_register(ViPipe, 0x0103, 0x01); + sc2336p_write_register(ViPipe, 0x0100, 0x00); + sc2336p_write_register(ViPipe, 0x36e9, 0x80); + sc2336p_write_register(ViPipe, 0x37f9, 0x80); + sc2336p_write_register(ViPipe, 0x301f, 0x02); + sc2336p_write_register(ViPipe, 0x3106, 0x05); + sc2336p_write_register(ViPipe, 0x3248, 0x04); + sc2336p_write_register(ViPipe, 0x3249, 0x0b); + sc2336p_write_register(ViPipe, 0x3253, 0x08); + sc2336p_write_register(ViPipe, 0x3301, 0x09); + sc2336p_write_register(ViPipe, 0x3302, 0xff); + sc2336p_write_register(ViPipe, 0x3303, 0x10); + sc2336p_write_register(ViPipe, 0x3306, 0x80); + sc2336p_write_register(ViPipe, 0x3307, 0x02); + sc2336p_write_register(ViPipe, 0x3309, 0xc8); + sc2336p_write_register(ViPipe, 0x330a, 0x01); + sc2336p_write_register(ViPipe, 0x330b, 0x30); + sc2336p_write_register(ViPipe, 0x330c, 0x16); + sc2336p_write_register(ViPipe, 0x330d, 0xff); + sc2336p_write_register(ViPipe, 0x3318, 0x02); + sc2336p_write_register(ViPipe, 0x331f, 0xb9); + sc2336p_write_register(ViPipe, 0x3321, 0x0a); + sc2336p_write_register(ViPipe, 0x3327, 0x0e); + sc2336p_write_register(ViPipe, 0x332b, 0x12); + sc2336p_write_register(ViPipe, 0x3333, 0x10); + sc2336p_write_register(ViPipe, 0x3334, 0x40); + sc2336p_write_register(ViPipe, 0x335e, 0x06); + sc2336p_write_register(ViPipe, 0x335f, 0x0a); + sc2336p_write_register(ViPipe, 0x3364, 0x1f); + sc2336p_write_register(ViPipe, 0x337c, 0x02); + sc2336p_write_register(ViPipe, 0x337d, 0x0e); + sc2336p_write_register(ViPipe, 0x3390, 0x09); + sc2336p_write_register(ViPipe, 0x3391, 0x0f); + sc2336p_write_register(ViPipe, 0x3392, 0x1f); + sc2336p_write_register(ViPipe, 0x3393, 0x20); + sc2336p_write_register(ViPipe, 0x3394, 0x20); + sc2336p_write_register(ViPipe, 0x3395, 0xe0); + sc2336p_write_register(ViPipe, 0x33a2, 0x04); + sc2336p_write_register(ViPipe, 0x33b1, 0x80); + sc2336p_write_register(ViPipe, 0x33b2, 0x68); + sc2336p_write_register(ViPipe, 0x33b3, 0x42); + sc2336p_write_register(ViPipe, 0x33f9, 0x90); + sc2336p_write_register(ViPipe, 0x33fb, 0xd0); + sc2336p_write_register(ViPipe, 0x33fc, 0x0f); + sc2336p_write_register(ViPipe, 0x33fd, 0x1f); + sc2336p_write_register(ViPipe, 0x349f, 0x03); + sc2336p_write_register(ViPipe, 0x34a6, 0x0f); + sc2336p_write_register(ViPipe, 0x34a7, 0x1f); + sc2336p_write_register(ViPipe, 0x34a8, 0x42); + sc2336p_write_register(ViPipe, 0x34a9, 0x18); + sc2336p_write_register(ViPipe, 0x34aa, 0x01); + sc2336p_write_register(ViPipe, 0x34ab, 0x43); + sc2336p_write_register(ViPipe, 0x34ac, 0x01); + sc2336p_write_register(ViPipe, 0x34ad, 0x80); + sc2336p_write_register(ViPipe, 0x3630, 0xf4); + sc2336p_write_register(ViPipe, 0x3632, 0x44); + sc2336p_write_register(ViPipe, 0x3633, 0x22); + sc2336p_write_register(ViPipe, 0x3639, 0xf4); + sc2336p_write_register(ViPipe, 0x363c, 0x47); + sc2336p_write_register(ViPipe, 0x3670, 0x09); + sc2336p_write_register(ViPipe, 0x3674, 0xf4); + sc2336p_write_register(ViPipe, 0x3675, 0xfb); + sc2336p_write_register(ViPipe, 0x3676, 0xed); + sc2336p_write_register(ViPipe, 0x367c, 0x09); + sc2336p_write_register(ViPipe, 0x367d, 0x0f); + sc2336p_write_register(ViPipe, 0x3690, 0x22); + sc2336p_write_register(ViPipe, 0x3691, 0x22); + sc2336p_write_register(ViPipe, 0x3692, 0x22); + sc2336p_write_register(ViPipe, 0x3698, 0x89); + sc2336p_write_register(ViPipe, 0x3699, 0x96); + sc2336p_write_register(ViPipe, 0x369a, 0xd0); + sc2336p_write_register(ViPipe, 0x369b, 0xd0); + sc2336p_write_register(ViPipe, 0x369c, 0x09); + sc2336p_write_register(ViPipe, 0x369d, 0x0f); + sc2336p_write_register(ViPipe, 0x36a2, 0x09); + sc2336p_write_register(ViPipe, 0x36a3, 0x0f); + sc2336p_write_register(ViPipe, 0x36a4, 0x1f); + sc2336p_write_register(ViPipe, 0x36d0, 0x01); + sc2336p_write_register(ViPipe, 0x3722, 0x81); + sc2336p_write_register(ViPipe, 0x3724, 0x41); + sc2336p_write_register(ViPipe, 0x3725, 0xc1); + sc2336p_write_register(ViPipe, 0x3728, 0x20); + sc2336p_write_register(ViPipe, 0x3900, 0x0d); + sc2336p_write_register(ViPipe, 0x3905, 0x98); + sc2336p_write_register(ViPipe, 0x391b, 0x81); + sc2336p_write_register(ViPipe, 0x391c, 0x10); + sc2336p_write_register(ViPipe, 0x3933, 0x81); + sc2336p_write_register(ViPipe, 0x3934, 0xd0); + sc2336p_write_register(ViPipe, 0x3940, 0x75); + sc2336p_write_register(ViPipe, 0x3941, 0x00); + sc2336p_write_register(ViPipe, 0x3942, 0x01); + sc2336p_write_register(ViPipe, 0x3943, 0xd1); + sc2336p_write_register(ViPipe, 0x3952, 0x02); + sc2336p_write_register(ViPipe, 0x3953, 0x0f); + sc2336p_write_register(ViPipe, 0x3e01, 0x45); + sc2336p_write_register(ViPipe, 0x3e02, 0xf0); + sc2336p_write_register(ViPipe, 0x3e08, 0x1f); + sc2336p_write_register(ViPipe, 0x3e1b, 0x14); + sc2336p_write_register(ViPipe, 0x440e, 0x02); + sc2336p_write_register(ViPipe, 0x4509, 0x38); + sc2336p_write_register(ViPipe, 0x5799, 0x06); + sc2336p_write_register(ViPipe, 0x5ae0, 0xfe); + sc2336p_write_register(ViPipe, 0x5ae1, 0x40); + sc2336p_write_register(ViPipe, 0x5ae2, 0x30); + sc2336p_write_register(ViPipe, 0x5ae3, 0x28); + sc2336p_write_register(ViPipe, 0x5ae4, 0x20); + sc2336p_write_register(ViPipe, 0x5ae5, 0x30); + sc2336p_write_register(ViPipe, 0x5ae6, 0x28); + sc2336p_write_register(ViPipe, 0x5ae7, 0x20); + sc2336p_write_register(ViPipe, 0x5ae8, 0x3c); + sc2336p_write_register(ViPipe, 0x5ae9, 0x30); + sc2336p_write_register(ViPipe, 0x5aea, 0x28); + sc2336p_write_register(ViPipe, 0x5aeb, 0x3c); + sc2336p_write_register(ViPipe, 0x5aec, 0x30); + sc2336p_write_register(ViPipe, 0x5aed, 0x28); + sc2336p_write_register(ViPipe, 0x5aee, 0xfe); + sc2336p_write_register(ViPipe, 0x5aef, 0x40); + sc2336p_write_register(ViPipe, 0x5af4, 0x30); + sc2336p_write_register(ViPipe, 0x5af5, 0x28); + sc2336p_write_register(ViPipe, 0x5af6, 0x20); + sc2336p_write_register(ViPipe, 0x5af7, 0x30); + sc2336p_write_register(ViPipe, 0x5af8, 0x28); + sc2336p_write_register(ViPipe, 0x5af9, 0x20); + sc2336p_write_register(ViPipe, 0x5afa, 0x3c); + sc2336p_write_register(ViPipe, 0x5afb, 0x30); + sc2336p_write_register(ViPipe, 0x5afc, 0x28); + sc2336p_write_register(ViPipe, 0x5afd, 0x3c); + sc2336p_write_register(ViPipe, 0x5afe, 0x30); + sc2336p_write_register(ViPipe, 0x5aff, 0x28); + sc2336p_write_register(ViPipe, 0x36e9, 0x20); + sc2336p_write_register(ViPipe, 0x37f9, 0x27); + + sc2336p_default_reg_init(ViPipe); + + sc2336p_write_register(ViPipe, 0x0100, 0x01); + + printf("ViPipe:%d,===SC2336P 1080P 30fps 10bit LINE Init OK!===\n", ViPipe); +} diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/Makefile b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/Makefile new file mode 100644 index 000000000..f2679b71f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_sc4336p.a +TARGET_SO = $(MW_LIB)/libsns_sc4336p.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos.c b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos.c new file mode 100644 index 000000000..1901daec9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos.c @@ -0,0 +1,916 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "sc4336p_cmos_ex.h" +#include "sc4336p_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define SC4336P_ID 4336 +#define SENSOR_SC4336P_WIDTH 2560 +#define SENSOR_SC4336P_HEIGHT 1440 +#define SC4336P_I2C_ADDR_1 0x30 +#define SC4336P_I2C_ADDR_2 0x32 +#define SC4336P_I2C_ADDR_IS_VALID(addr) ((addr) == SC4336P_I2C_ADDR_1 || (addr) == SC4336P_I2C_ADDR_2) + +#define SC4336P_EXPACCURACY (1) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastSC4336P[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define SC4336P_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastSC4336P[dev]) +#define SC4336P_SENSOR_SET_CTX(dev, pstCtx) (g_pastSC4336P[dev] = pstCtx) +#define SC4336P_SENSOR_RESET_CTX(dev) (g_pastSC4336P[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunSC4336P_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16SC4336P_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16SC4336P_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +ISP_SNS_MIRRORFLIP_TYPE_E g_aeSc4336p_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****SC4336P Lines Range*****/ +#define SC4336P_FULL_LINES_MAX (0x7FFF) + +/*****SC4336P Register Address*****/ +#define SC4336P_EXP_ADDR 0x3E00 +#define SC4336P_AGAIN_ADDR 0x3E09 +#define SC4336P_DGAIN_ADDR 0x3E06 +#define SC4336P_VMAX_ADDR 0x320E + +#define SC4336P_RES_IS_1440P(w, h) ((w) == 2560 && (h) == 1440) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = SC4336P_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = SC4336P_EXPACCURACY; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_DB; + pstAeSnsDft->stAgainAccu.f32Accuracy = 6; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = g_astSC4336P_mode[pstSnsState->u8ImgMode].f32MaxFps; + pstAeSnsDft->f32MinFps = g_astSC4336P_mode[pstSnsState->u8ImgMode].f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = g_astSC4336P_mode[pstSnsState->u8ImgMode].stAgain[0].u32Max; + pstAeSnsDft->u32MinAgain = g_astSC4336P_mode[pstSnsState->u8ImgMode].stAgain[0].u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = g_astSC4336P_mode[pstSnsState->u8ImgMode].stDgain[0].u32Max; + pstAeSnsDft->u32MinDgain = g_astSC4336P_mode[pstSnsState->u8ImgMode].stDgain[0].u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = g_astSC4336P_mode[pstSnsState->u8ImgMode].stExp[0].u32Max; + pstAeSnsDft->u32MinIntTime = g_astSC4336P_mode[pstSnsState->u8ImgMode].stExp[0].u32Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astSC4336P_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astSC4336P_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astSC4336P_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case SC4336P_MODE_1440P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > SC4336P_FULL_LINES_MAX) ? SC4336P_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_ADDR].u32Data = ((u32VMAX & 0x7F00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_ADDR].u32Data = (u32VMAX & 0xFF); + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = (pstSnsState->u32FLStd << 1) - 8; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32TmpIntTime, u32MinTime, u32MaxTime; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + /* linear exposure reg range: + * min : 0 + * max : vts - 8 + * step : 1 + */ + u32MinTime = 0; + u32MaxTime = pstSnsState->au32FL[0] - 8; + u32TmpIntTime = (u32IntTime[0] > u32MaxTime) ? u32MaxTime : u32IntTime[0]; + u32TmpIntTime = (u32TmpIntTime < u32MinTime) ? u32MinTime : u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_ADDR].u32Data = ((u32TmpIntTime & 0xF000) >> 12); //bit[15:12] + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_ADDR].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4); //bit[11:4] + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_2_ADDR].u32Data = ((u32TmpIntTime & 0x000F) << 4); //bit[3:0] + + return CVI_SUCCESS; +} + +struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +}; + +static struct gain_tbl_info_s DgainInfo[] = { + { + .gainMax = 2016, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x01, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 8064, + .idxBase = 64, + .regGain = 0x03, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 16128, + .idxBase = 96, + .regGain = 0x07, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, +}; + +static CVI_U32 Dgain_table[] = { + 1024, 1055, 1088, 1120, 1152, 1183, 1216, 1248, 1280, 1311, 1344, 1376, 1408, 1439, 1472, + 1504, 1536, 1567, 1600, 1632, 1664, 1695, 1728, 1760, 1792, 1823, 1856, 1888, 1920, 1951, + 1984, 2016, 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, + 2816, 2880, 2944, 3008, 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, + 3840, 3904, 3968, 4032, 4096, 4224, 4352, 4480, 4608, 4736, 4864, 4992, 5120, 5248, 5376, + 5504, 5632, 5760, 5888, 6016, 6144, 6272, 6400, 6528, 6656, 6784, 6912, 7040, 7168, 7296, + 7424, 7552, 7680, 7808, 7936, 8064, 8192, 8448, 8704, 8960, 9216, 9472, 9728, 9984, 10240, + 10496, 10752, 11008, 11264, 11520, 11776, 12032, 12288, 12544, 12800, 13056, 13312, + 13568, 13824, 14080, 14336, 14592, 14848, 15104, 15360, 15616, 15872, 16128 +}; + +static const CVI_U32 dgain_table_size = ARRAY_SIZE(Dgain_table); + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 again = *pu32AgainLin; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (again < 2048) { + *pu32AgainDb = 0x00; + *pu32AgainLin = 1024; + } else if (again < 4096) { + *pu32AgainDb = 0x08; + *pu32AgainLin = 2048; + } else if (again < 8192) { + *pu32AgainDb = 0x09; + *pu32AgainLin = 4096; + } else if (again < 16384) { + *pu32AgainDb = 0x0B; + *pu32AgainLin = 8192; + } else if (again < 32768) { + *pu32AgainDb = 0x0F; + *pu32AgainLin = 16384; + } else { + *pu32AgainDb = 0x1F; + *pu32AgainLin = 32768; + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 i; + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[dgain_table_size - 1]) { + *pu32DgainLin = Dgain_table[dgain_table_size - 1]; + *pu32DgainDb = dgain_table_size - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < dgain_table_size; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + /* find Again register setting. */ + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_ADDR].u32Data = (u32Again & 0xFF); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_ADDR].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_D_FINEGAIN_ADDR].u32Data = (u32Dgain & 0xFF); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + //pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + //pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const SC4336P_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astSC4336P_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = SC4336P_MODE_1440P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astSC4336P_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunSC4336P_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = sc4336p_i2c_addr; + pstI2c_data[i].u32AddrByteNum = sc4336p_addr_byte; + pstI2c_data[i].u32DataByteNum = sc4336p_data_byte; + } + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + //Linear Mode Regs + pstI2c_data[LINEAR_SHS1_0_ADDR].u32RegAddr = SC4336P_EXP_ADDR; + pstI2c_data[LINEAR_SHS1_1_ADDR].u32RegAddr = SC4336P_EXP_ADDR + 1; + pstI2c_data[LINEAR_SHS1_2_ADDR].u32RegAddr = SC4336P_EXP_ADDR + 2; + + pstI2c_data[LINEAR_AGAIN_ADDR].u32RegAddr = SC4336P_AGAIN_ADDR; + pstI2c_data[LINEAR_DGAIN_ADDR].u32RegAddr = SC4336P_DGAIN_ADDR; + pstI2c_data[LINEAR_D_FINEGAIN_ADDR].u32RegAddr = SC4336P_DGAIN_ADDR + 1; + + pstI2c_data[LINEAR_VMAX_0_ADDR].u32RegAddr = SC4336P_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1_ADDR].u32RegAddr = SC4336P_VMAX_ADDR + 1; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (SC4336P_RES_IS_1440P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = SC4336P_MODE_1440P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + if (pstSnsState->bInit == CVI_TRUE && g_aeSc4336p_MirrorFip[ViPipe] != eSnsMirrorFlip) { + sc4336p_mirror_flip(ViPipe, eSnsMirrorFlip); + g_aeSc4336p_MirrorFip[ViPipe] = eSnsMirrorFlip; + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const SC4336P_MODE_S *pstMode = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = SC4336P_MODE_1440P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astSC4336P_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &sc4336p_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astSC4336P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astSC4336P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &sc4336p_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = sc4336p_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = sc4336p_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (SC4336P_I2C_ADDR_IS_VALID(s32I2cAddr)) + sc4336p_i2c_addr = s32I2cAddr; +} + +static CVI_S32 sc4336p_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunSC4336P_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + SC4336P_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC4336P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + SC4336P_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = SC4336P_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, SC4336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, SC4336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, SC4336P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16SC4336P_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16SC4336P_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsSC4336P_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = sc4336p_standby, + .pfnRestart = sc4336p_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = sc4336p_write_register, + .pfnReadReg = sc4336p_read_register, + .pfnSetBusInfo = sc4336p_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = sc4336p_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos_ex.h new file mode 100644 index 000000000..d09e26b52 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos_ex.h @@ -0,0 +1,78 @@ +#ifndef __SC4336P_CMOS_EX_H_ +#define __SC4336P_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum sc4336p_linear_regs_e { + LINEAR_SHS1_0_ADDR, + LINEAR_SHS1_1_ADDR, + LINEAR_SHS1_2_ADDR, + LINEAR_AGAIN_ADDR, + LINEAR_DGAIN_ADDR, + LINEAR_D_FINEGAIN_ADDR, + LINEAR_VMAX_0_ADDR, + LINEAR_VMAX_1_ADDR, + LINEAR_REGS_NUM +}; + +typedef enum _SC4336P_MODE_E { + SC4336P_MODE_1440P30 = 0, + SC4336P_MODE_NUM +} SC4336P_MODE_E; + +typedef struct _SC4336P_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_LARGE_S stExp[2]; + SNS_ATTR_LARGE_S stAgain[2]; + SNS_ATTR_LARGE_S stDgain[2]; + char name[64]; +} SC4336P_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastSC4336P[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunSC4336P_BusInfo[]; +extern CVI_U16 g_au16SC4336P_GainMode[]; +extern CVI_U16 g_au16SC4336P_L2SMode[]; +extern CVI_U8 sc4336p_i2c_addr; +extern const CVI_U32 sc4336p_addr_byte; +extern const CVI_U32 sc4336p_data_byte; +extern void sc4336p_init(VI_PIPE ViPipe); +extern void sc4336p_exit(VI_PIPE ViPipe); +extern void sc4336p_standby(VI_PIPE ViPipe); +extern void sc4336p_restart(VI_PIPE ViPipe); +extern int sc4336p_write_register(VI_PIPE ViPipe, int addr, int data); +extern int sc4336p_read_register(VI_PIPE ViPipe, int addr); +extern void sc4336p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int sc4336p_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC4336P_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos_param.h new file mode 100644 index 000000000..d086f8ae9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_cmos_param.h @@ -0,0 +1,121 @@ +#ifndef __SC4336P_CMOS_PARAM_H_ +#define __SC4336P_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc4336p_cmos_ex.h" + +static const SC4336P_MODE_S g_astSC4336P_mode[SC4336P_MODE_NUM] = { + [SC4336P_MODE_1440P30] = { + .name = "1440p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 2560, + .u32Height = 1440, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2560, + .u32Height = 1440, + }, + .stMaxSize = { + .u32Width = 2560, + .u32Height = 1440, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 1.37, /* 1500 * 30 / 0x7FFF*/ + .u32HtsDef = 2800, + .u32VtsDef = 1500, + .stExp[0] = { + .u32Min = 0, + .u32Max = 1500 - 8, //vts - 8 + .u32Def = 400, + .u32Step = 1, + }, + .stAgain[0] = { + .u32Min = 1024, + .u32Max = 32768, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain[0] = { + .u32Min = 1024, + .u32Max = 16182, + .u32Def = 1024, + .u32Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {260, 260, 260, 260, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1093, 1093, 1093, 1093 +#endif + }, + .stAuto = { + {260, 260, 260, 260, 260, 260, 260, 260, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 260, 260, 260, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 260, 260, 260, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {260, 260, 260, 260, 260, 260, 260, 260, /*8*/260, 260, 260, 260, 260, 260, 260, 260}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, + {1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093, + /*8*/1093, 1093, 1093, 1093, 1093, 1093, 1093, 1093}, +#endif + }, + }, +}; + +struct combo_dev_attr_s sc4336p_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {2, 1, 3, -1, -1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC4336P_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_sensor_ctl.c new file mode 100644 index 000000000..fccedf9d1 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc4336p/sc4336p_sensor_ctl.c @@ -0,0 +1,384 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc4336p_cmos_ex.h" + +static void sc4336p_linear_1440p30_init(VI_PIPE ViPipe); + +CVI_U8 sc4336p_i2c_addr = 0x30; /* I2C Address of SC4336P */ +const CVI_U32 sc4336p_addr_byte = 2; +const CVI_U32 sc4336p_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int sc4336p_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunSC4336P_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, sc4336p_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int sc4336p_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int sc4336p_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (sc4336p_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, sc4336p_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, sc4336p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (sc4336p_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int sc4336p_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (sc4336p_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (sc4336p_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, sc4336p_addr_byte + sc4336p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void sc4336p_standby(VI_PIPE ViPipe) +{ + sc4336p_write_register(ViPipe, 0x0100, 0x00); +} + +void sc4336p_restart(VI_PIPE ViPipe) +{ + sc4336p_write_register(ViPipe, 0x0100, 0x00); + delay_ms(20); + sc4336p_write_register(ViPipe, 0x0100, 0x01); +} + +void sc4336p_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastSC4336P[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + sc4336p_write_register(ViPipe, + g_pastSC4336P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastSC4336P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +void sc4336p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = 0; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x6; + break; + case ISP_SNS_FLIP: + val |= 0x60; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x66; + break; + default: + return; + } + + sc4336p_write_register(ViPipe, 0x3221, val); +} + +#define SC4336P_CHIP_ID_HI_ADDR 0x3107 +#define SC4336P_CHIP_ID_LO_ADDR 0x3108 +#define SC4336P_CHIP_ID 0x9c42 + +int sc4336p_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + if (sc4336p_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + delay_ms(5); + + nVal = sc4336p_read_register(ViPipe, SC4336P_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = sc4336p_read_register(ViPipe, SC4336P_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != SC4336P_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + printf("%d\n", ViPipe); + return CVI_SUCCESS; +} + + +void sc4336p_init(VI_PIPE ViPipe) +{ + sc4336p_i2c_init(ViPipe); + + sc4336p_linear_1440p30_init(ViPipe); + + g_pastSC4336P[ViPipe]->bInit = CVI_TRUE; +} + +void sc4336p_exit(VI_PIPE ViPipe) +{ + sc4336p_i2c_exit(ViPipe); +} + +/* 1440P30 and 1440P25 */ +static void sc4336p_linear_1440p30_init(VI_PIPE ViPipe) +{ + sc4336p_write_register(ViPipe, 0x0103, 0x01); + sc4336p_write_register(ViPipe, 0x36e9, 0x80); + sc4336p_write_register(ViPipe, 0x37f9, 0x80); + sc4336p_write_register(ViPipe, 0x301f, 0x01); + sc4336p_write_register(ViPipe, 0x30b8, 0x44); + sc4336p_write_register(ViPipe, 0x3253, 0x10); + sc4336p_write_register(ViPipe, 0x3301, 0x0a); + sc4336p_write_register(ViPipe, 0x3302, 0xff); + sc4336p_write_register(ViPipe, 0x3305, 0x00); + sc4336p_write_register(ViPipe, 0x3306, 0x90); + sc4336p_write_register(ViPipe, 0x3308, 0x08); + sc4336p_write_register(ViPipe, 0x330a, 0x01); + sc4336p_write_register(ViPipe, 0x330b, 0xb0); + sc4336p_write_register(ViPipe, 0x330d, 0xf0); + sc4336p_write_register(ViPipe, 0x3314, 0x14); + sc4336p_write_register(ViPipe, 0x3333, 0x10); + sc4336p_write_register(ViPipe, 0x3334, 0x40); + sc4336p_write_register(ViPipe, 0x335e, 0x06); + sc4336p_write_register(ViPipe, 0x335f, 0x0a); + sc4336p_write_register(ViPipe, 0x3364, 0x5e); + sc4336p_write_register(ViPipe, 0x337d, 0x0e); + sc4336p_write_register(ViPipe, 0x338f, 0x20); + sc4336p_write_register(ViPipe, 0x3390, 0x08); + sc4336p_write_register(ViPipe, 0x3391, 0x09); + sc4336p_write_register(ViPipe, 0x3392, 0x0f); + sc4336p_write_register(ViPipe, 0x3393, 0x18); + sc4336p_write_register(ViPipe, 0x3394, 0x60); + sc4336p_write_register(ViPipe, 0x3395, 0xff); + sc4336p_write_register(ViPipe, 0x3396, 0x08); + sc4336p_write_register(ViPipe, 0x3397, 0x09); + sc4336p_write_register(ViPipe, 0x3398, 0x0f); + sc4336p_write_register(ViPipe, 0x3399, 0x0a); + sc4336p_write_register(ViPipe, 0x339a, 0x18); + sc4336p_write_register(ViPipe, 0x339b, 0x60); + sc4336p_write_register(ViPipe, 0x339c, 0xff); + sc4336p_write_register(ViPipe, 0x33a2, 0x04); + sc4336p_write_register(ViPipe, 0x33ad, 0x0c); + sc4336p_write_register(ViPipe, 0x33b2, 0x40); + sc4336p_write_register(ViPipe, 0x33b3, 0x30); + sc4336p_write_register(ViPipe, 0x33f8, 0x00); + sc4336p_write_register(ViPipe, 0x33f9, 0xb0); + sc4336p_write_register(ViPipe, 0x33fa, 0x00); + sc4336p_write_register(ViPipe, 0x33fb, 0xf8); + sc4336p_write_register(ViPipe, 0x33fc, 0x09); + sc4336p_write_register(ViPipe, 0x33fd, 0x1f); + sc4336p_write_register(ViPipe, 0x349f, 0x03); + sc4336p_write_register(ViPipe, 0x34a6, 0x09); + sc4336p_write_register(ViPipe, 0x34a7, 0x1f); + sc4336p_write_register(ViPipe, 0x34a8, 0x28); + sc4336p_write_register(ViPipe, 0x34a9, 0x28); + sc4336p_write_register(ViPipe, 0x34aa, 0x01); + sc4336p_write_register(ViPipe, 0x34ab, 0xe0); + sc4336p_write_register(ViPipe, 0x34ac, 0x02); + sc4336p_write_register(ViPipe, 0x34ad, 0x28); + sc4336p_write_register(ViPipe, 0x34f8, 0x1f); + sc4336p_write_register(ViPipe, 0x34f9, 0x20); + sc4336p_write_register(ViPipe, 0x3630, 0xc0); + sc4336p_write_register(ViPipe, 0x3631, 0x84); + sc4336p_write_register(ViPipe, 0x3632, 0x54); + sc4336p_write_register(ViPipe, 0x3633, 0x44); + sc4336p_write_register(ViPipe, 0x3637, 0x49); + sc4336p_write_register(ViPipe, 0x363f, 0xc0); + sc4336p_write_register(ViPipe, 0x3641, 0x28); + sc4336p_write_register(ViPipe, 0x3670, 0x56); + sc4336p_write_register(ViPipe, 0x3674, 0xb0); + sc4336p_write_register(ViPipe, 0x3675, 0xa0); + sc4336p_write_register(ViPipe, 0x3676, 0xa0); + sc4336p_write_register(ViPipe, 0x3677, 0x84); + sc4336p_write_register(ViPipe, 0x3678, 0x88); + sc4336p_write_register(ViPipe, 0x3679, 0x8d); + sc4336p_write_register(ViPipe, 0x367c, 0x09); + sc4336p_write_register(ViPipe, 0x367d, 0x0b); + sc4336p_write_register(ViPipe, 0x367e, 0x08); + sc4336p_write_register(ViPipe, 0x367f, 0x0f); + sc4336p_write_register(ViPipe, 0x3696, 0x24); + sc4336p_write_register(ViPipe, 0x3697, 0x34); + sc4336p_write_register(ViPipe, 0x3698, 0x34); + sc4336p_write_register(ViPipe, 0x36a0, 0x0f); + sc4336p_write_register(ViPipe, 0x36a1, 0x1f); + sc4336p_write_register(ViPipe, 0x36b0, 0x81); + sc4336p_write_register(ViPipe, 0x36b1, 0x83); + sc4336p_write_register(ViPipe, 0x36b2, 0x85); + sc4336p_write_register(ViPipe, 0x36b3, 0x8b); + sc4336p_write_register(ViPipe, 0x36b4, 0x09); + sc4336p_write_register(ViPipe, 0x36b5, 0x0b); + sc4336p_write_register(ViPipe, 0x36b6, 0x0f); + sc4336p_write_register(ViPipe, 0x370f, 0x01); + sc4336p_write_register(ViPipe, 0x3722, 0x09); + sc4336p_write_register(ViPipe, 0x3724, 0x21); + sc4336p_write_register(ViPipe, 0x3771, 0x09); + sc4336p_write_register(ViPipe, 0x3772, 0x05); + sc4336p_write_register(ViPipe, 0x3773, 0x05); + sc4336p_write_register(ViPipe, 0x377a, 0x0f); + sc4336p_write_register(ViPipe, 0x377b, 0x1f); + sc4336p_write_register(ViPipe, 0x3905, 0x8c); + sc4336p_write_register(ViPipe, 0x391d, 0x02); + sc4336p_write_register(ViPipe, 0x391f, 0x49); + sc4336p_write_register(ViPipe, 0x3926, 0x21); + sc4336p_write_register(ViPipe, 0x3933, 0x80); + sc4336p_write_register(ViPipe, 0x3934, 0x03); + sc4336p_write_register(ViPipe, 0x3937, 0x7b); + sc4336p_write_register(ViPipe, 0x3939, 0x00); + sc4336p_write_register(ViPipe, 0x393a, 0x00); + sc4336p_write_register(ViPipe, 0x39dc, 0x02); + sc4336p_write_register(ViPipe, 0x3e00, 0x00); + sc4336p_write_register(ViPipe, 0x3e01, 0x5d); + sc4336p_write_register(ViPipe, 0x3e02, 0x40); + sc4336p_write_register(ViPipe, 0x440e, 0x02); + sc4336p_write_register(ViPipe, 0x4509, 0x28); + sc4336p_write_register(ViPipe, 0x450d, 0x32); + sc4336p_write_register(ViPipe, 0x5000, 0x06); + sc4336p_write_register(ViPipe, 0x578d, 0x40); + sc4336p_write_register(ViPipe, 0x5799, 0x46); + sc4336p_write_register(ViPipe, 0x579a, 0x77); + sc4336p_write_register(ViPipe, 0x57d9, 0x46); + sc4336p_write_register(ViPipe, 0x57da, 0x77); + sc4336p_write_register(ViPipe, 0x5ae0, 0xfe); + sc4336p_write_register(ViPipe, 0x5ae1, 0x40); + sc4336p_write_register(ViPipe, 0x5ae2, 0x38); + sc4336p_write_register(ViPipe, 0x5ae3, 0x30); + sc4336p_write_register(ViPipe, 0x5ae4, 0x28); + sc4336p_write_register(ViPipe, 0x5ae5, 0x38); + sc4336p_write_register(ViPipe, 0x5ae6, 0x30); + sc4336p_write_register(ViPipe, 0x5ae7, 0x28); + sc4336p_write_register(ViPipe, 0x5ae8, 0x3f); + sc4336p_write_register(ViPipe, 0x5ae9, 0x34); + sc4336p_write_register(ViPipe, 0x5aea, 0x2c); + sc4336p_write_register(ViPipe, 0x5aeb, 0x3f); + sc4336p_write_register(ViPipe, 0x5aec, 0x34); + sc4336p_write_register(ViPipe, 0x5aed, 0x2c); + sc4336p_write_register(ViPipe, 0x36e9, 0x44); + sc4336p_write_register(ViPipe, 0x37f9, 0x44); + + sc4336p_default_reg_init(ViPipe); + + sc4336p_write_register(ViPipe, 0x0100, 0x01); + + delay_ms(100); + + printf("ViPipe:%d,===SC4336P 1440P 30fps 10bit LINE Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/Makefile b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/Makefile new file mode 100644 index 000000000..a4b7ecc74 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_sc5336_2L.a +TARGET_SO = $(MW_LIB)/libsns_sc5336_2L.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos.c b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos.c new file mode 100644 index 000000000..9d1077905 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos.c @@ -0,0 +1,1062 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "sc5336_2L_cmos_ex.h" +#include "sc5336_2L_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define SC5336_2L_ID 500 +#define SENSOR_SC5336_2L_WIDTH 2880 +#define SENSOR_SC5336_2L_HEIGHT 1620 +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastSC5336_2L[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define SC5336_2L_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastSC5336_2L[dev]) +#define SC5336_2L_SENSOR_SET_CTX(dev, pstCtx) (g_pastSC5336_2L[dev] = pstCtx) +#define SC5336_2L_SENSOR_RESET_CTX(dev) (g_pastSC5336_2L[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunSC5336_2L_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16SC5336_2L_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16SC5336_2L_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +SC5336_2L_STATE_S g_astSC5336_2L_State[VI_MAX_PIPE_NUM] = {{0} }; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = { + [0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE +}; + +static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****SC5336_2L Lines Range*****/ +#define SC5336_2L_FULL_LINES_MAX (0x7FFF) + +/*****SC5336_2L Register Address*****/ +#define SC5336_2L_SHS1_0_ADDR 0x3E00 +#define SC5336_2L_SHS1_1_ADDR 0x3E01 +#define SC5336_2L_SHS1_2_ADDR 0x3E02 +#define SC5336_2L_AGAIN_0_ADDR 0x3E09 +#define SC5336_2L_DGAIN_0_ADDR 0x3E06 +#define SC5336_2L_VMAX_ADDR 0x320E +#define SC5336_2L_TABLE_END 0xFFFF + +#define SC5336_2L_RES_IS_1620P(w, h) ((w) <= 2880 && (h) <= 1620) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); +#if 0 + memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S)); +#endif + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = SC5336_2L_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + default: + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].f32MaxFps; + pstAeSnsDft->f32MinFps = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].stAgain[0].u32Max; + pstAeSnsDft->u32MinAgain = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].stAgain[0].u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].stDgain[0].u32Max; + pstAeSnsDft->u32MinDgain = g_astSC5336_2L_mode[SC5336_2L_MODE_1620P30].stDgain[0].u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 4; + pstAeSnsDft->u32MinIntTime = 3; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + case WDR_MODE_2To1_LINE: + break; + } + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case SC5336_2L_MODE_1620P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > SC5336_2L_FULL_LINES_MAX) ? SC5336_2L_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_ADDR].u32Data = ((u32VMAX & 0xFF00) >> 8); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_ADDR].u32Data = (u32VMAX & 0xFF); + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 4; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + CVI_U32 u32TmpIntTime = u32IntTime[0]; + CVI_U32 maxExp = pstSnsState->au32FL[0] - 4; + + /* linear exposure reg range: + * min : 2 + * max : vts - 4 + * step : 1 + */ + u32TmpIntTime = (u32TmpIntTime > maxExp) ? maxExp : u32TmpIntTime; + if (u32TmpIntTime < 2) + u32TmpIntTime = 2; + u32IntTime[0] = u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_ADDR].u32Data = ((u32TmpIntTime & 0xF000) >> 12); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_ADDR].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_2_ADDR].u32Data = (u32TmpIntTime & 0xF) << 4; + + return CVI_SUCCESS; + +} + +struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +}; + +static struct gain_tbl_info_s AgainInfo[] = { + { + .gainMax = 2016, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x08, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 8064, + .idxBase = 64, + .regGain = 0x09, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 16128, + .idxBase = 96, + .regGain = 0x0b, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 32256, + .idxBase = 128, + .regGain = 0x0F, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 32768, + .idxBase = 160, + .regGain = 0x1F, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, +}; + +static CVI_U32 Again_table[] = { + 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, + 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, + 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, + 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, + + 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, + 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, + 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, + 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, + + 4096, 4224, 4352, 4480, 4608, 4736, 4864, 4992, + 5120, 5248, 5376, 5504, 5632, 5760, 5888, 6016, + 6144, 6272, 6400, 6528, 6656, 6784, 6912, 7040, + 7168, 7296, 7424, 7552, 7680, 7808, 7936, 8064, + + 8192, 8448, 8704, 8960, 9216, 9472, 9728, 9984, + 10240, 10496, 10752, 11008, 11264, 11520, 11776, 12032, + 12288, 12544, 12800, 13056, 13312, 13568, 13824, 14080, + 14336, 14592, 14848, 15104, 15360, 15616, 15872, 16128, + + 16384, 16896, 17408, 17920, 18432, 18944, 19456, 19968, + 20480, 20992, 21504, 22016, 22528, 23040, 23552, 24064, + 24576, 25088, 25600, 26112, 26624, 27136, 27648, 28160, + 28672, 29184, 29696, 30208, 30720, 31232, 31744, 32256, + + 32768, +}; + +static struct gain_tbl_info_s DgainInfo[] = { + { + .gainMax = 2016, + .idxBase = 0, + .regGain = 0x00, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x01, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 8064, + .idxBase = 64, + .regGain = 0x03, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, + { + .gainMax = 16128, + .idxBase = 96, + .regGain = 0x07, + .regGainFineBase = 0x80, + .regGainFineStep = 4, + }, +}; + +static CVI_U32 Dgain_table[] = { + 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, + 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, + 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, + 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, + + 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, + 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, + 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, + 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, + + 4096, 4224, 4352, 4480, 4608, 4736, 4864, 4992, + 5120, 5248, 5376, 5504, 5632, 5760, 5888, 6016, + 6144, 6272, 6400, 6528, 6656, 6784, 6912, 7040, + 7168, 7296, 7424, 7552, 7680, 7808, 7936, 8064, + + 8192, 8448, 8704, 8960, 9216, 9472, 9728, 9984, + 10240, 10496, 10752, 11008, 11264, 11520, 11776, 12032, + 12288, 12544, 12800, 13056, 13312, 13568, 13824, 14080, + 14336, 14592, 14848, 15104, 15360, 15616, 15872, 16128, +}; + +CVI_U32 AtableSize = sizeof(Again_table) / sizeof(CVI_U32); +CVI_U32 DtableSize = sizeof(Dgain_table) / sizeof(CVI_U32); + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 i; + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= Again_table[AtableSize - 1]) { + *pu32AgainLin = Again_table[AtableSize - 1]; + *pu32AgainDb = AtableSize - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < AtableSize; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 i; + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[DtableSize - 1]) { + *pu32DgainLin = Dgain_table[DtableSize - 1]; + *pu32DgainDb = DtableSize - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < DtableSize; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + + /* find Again register setting. */ + tbl_num = sizeof(AgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &AgainInfo[i]; + + if (u32Again >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_0_ADDR].u32Data = (info->regGain & 0xFF); + u32Again = info->regGainFineBase + (u32Again - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_1_ADDR].u32Data = (u32Again & 0xFF); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_0_ADDR].u32Data = (info->regGain & 0xFF); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_1_ADDR].u32Data = (u32Dgain & 0xFF); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio, + CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime) +{ + CVI_U32 u32IntTimeMaxTmp = 0; + CVI_U32 u32ShortTimeMinLimit = 5; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32MaxSexp = 2 * g_astSC5336_2L_State[ViPipe].u32Sexp_MAX - 14; + + (void) u16ManRatioEnable; + + CMOS_CHECK_POINTER(au32Ratio); + CMOS_CHECK_POINTER(au32IntTimeMax); + CMOS_CHECK_POINTER(au32IntTimeMin); + CMOS_CHECK_POINTER(pu32LFMaxIntTime); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + /* short exposure reg range: + * min : 5 + * max : 2 * (max sexp - 7) + * step : 4 + * long exposure reg range: + * min : 5 + * max : 2 * (vts - max sexp - 9) + * step : 4 + */ + u32IntTimeMaxTmp = ((2 * pstSnsState->au32FL[0] - 16) * 0x40) / (au32Ratio[0] + 0x40); + u32IntTimeMaxTmp = (u32IntTimeMaxTmp > u32MaxSexp) ? u32MaxSexp : u32IntTimeMaxTmp; + u32IntTimeMaxTmp = (u32IntTimeMaxTmp < u32ShortTimeMinLimit) ? u32ShortTimeMinLimit : u32IntTimeMaxTmp; + + if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) { + au32IntTimeMax[0] = u32IntTimeMaxTmp; + au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6; + au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6; + au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6; + au32IntTimeMin[0] = u32ShortTimeMinLimit; + au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6; + au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6; + au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6; + syslog(LOG_DEBUG, "ViPipe = %d ratio = %d, (%d, %d)\n", ViPipe, au32Ratio[0], + u32IntTimeMaxTmp, u32ShortTimeMinLimit); + } + + return CVI_SUCCESS; +} + +/* Only used in LINE_WDR mode */ +static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr) +{ + CMOS_CHECK_POINTER(pstAeFSWDRAttr); + + genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode; + gu32MaxTimeGetCnt[ViPipe] = 0; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + memcpy(pstDef->stNoiseCalibration.CalibrationCoef, + &g_stIspNoiseCalibratio, sizeof(ISP_CMOS_NOISE_CALIBRATION_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const SC5336_2L_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astSC5336_2L_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + + case WDR_MODE_2To1_LINE: + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunSC5336_2L_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = SC5336_2l_i2c_addr; + pstI2c_data[i].u32AddrByteNum = SC5336_2l_addr_byte; + pstI2c_data[i].u32DataByteNum = SC5336_2l_data_byte; + } + + //Linear Mode Regs + pstI2c_data[LINEAR_SHS1_0_ADDR].u32RegAddr = SC5336_2L_SHS1_0_ADDR; + pstI2c_data[LINEAR_SHS1_1_ADDR].u32RegAddr = SC5336_2L_SHS1_1_ADDR; + pstI2c_data[LINEAR_SHS1_2_ADDR].u32RegAddr = SC5336_2L_SHS1_2_ADDR; + pstI2c_data[LINEAR_AGAIN_0_ADDR].u32RegAddr = SC5336_2L_AGAIN_0_ADDR; + pstI2c_data[LINEAR_AGAIN_1_ADDR].u32RegAddr = SC5336_2L_DGAIN_0_ADDR + 1; + pstI2c_data[LINEAR_DGAIN_0_ADDR].u32RegAddr = SC5336_2L_DGAIN_0_ADDR; + pstI2c_data[LINEAR_DGAIN_1_ADDR].u32RegAddr = SC5336_2L_DGAIN_0_ADDR + 1; + pstI2c_data[LINEAR_VMAX_0_ADDR].u32RegAddr = SC5336_2L_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1_ADDR].u32RegAddr = SC5336_2L_VMAX_ADDR + 1; + + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (SC5336_2L_RES_IS_1620P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = SC5336_2L_MODE_1620P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const SC5336_2L_MODE_S *pstMode = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = SC5336_2L_MODE_1620P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astSC5336_2L_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &SC5336_2l_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astSC5336_2L_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &SC5336_2l_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = SC5336_2l_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = SC5336_2l_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 SC5336_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunSC5336_2L_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + SC5336_2L_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + SC5336_2L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + SC5336_2L_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = SC5336_2L_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, SC5336_2L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, SC5336_2L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, SC5336_2L_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16SC5336_2L_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16SC5336_2L_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsSC5336_2L_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = SC5336_2l_standby, + .pfnRestart = SC5336_2l_restart, + .pfnMirrorFlip = SC5336_2l_mirror_flip, + .pfnWriteReg = SC5336_2l_write_register, + .pfnReadReg = SC5336_2l_read_register, + .pfnSetBusInfo = SC5336_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = SC5336_2l_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos_ex.h new file mode 100644 index 000000000..2464599f3 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos_ex.h @@ -0,0 +1,85 @@ +#ifndef __SC5336_2L_CMOS_EX_H_ +#define __SC5336_2L_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum SC5336_2l_linear_regs_e { + LINEAR_SHS1_0_ADDR, + LINEAR_SHS1_1_ADDR, + LINEAR_SHS1_2_ADDR, + LINEAR_AGAIN_0_ADDR, + LINEAR_AGAIN_1_ADDR, + LINEAR_DGAIN_0_ADDR, + LINEAR_DGAIN_1_ADDR, + LINEAR_VMAX_0_ADDR, + LINEAR_VMAX_1_ADDR, + LINEAR_REGS_NUM +}; + +typedef enum _SC5336_2L_MODE_E { + SC5336_2L_MODE_1620P30 = 0, + SC5336_2L_MODE_LINEAR_NUM, + SC5336_2L_MODE_NUM +} SC5336_2L_MODE_E; + +typedef struct _SC5336_2L_STATE_S { + CVI_U32 u32Sexp_MAX; /* (2*{16’h3e23,16’h3e24} – 'd10)/2 */ +} SC5336_2L_STATE_S; + +typedef struct _SC5336_2L_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_LARGE_S stAgain[2]; + SNS_ATTR_LARGE_S stDgain[2]; + CVI_U16 u16SexpMaxReg; /* {16’h3e23,16’h3e24} */ + char name[64]; +} SC5336_2L_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastSC5336_2L[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunSC5336_2L_BusInfo[]; +extern CVI_U16 g_au16SC5336_2L_GainMode[]; +extern CVI_U16 g_au16SC5336_2L_L2SMode[]; +extern const CVI_U8 SC5336_2l_i2c_addr; +extern const CVI_U32 SC5336_2l_addr_byte; +extern const CVI_U32 SC5336_2l_data_byte; +extern void SC5336_2l_init(VI_PIPE ViPipe); +extern void SC5336_2l_exit(VI_PIPE ViPipe); +extern void SC5336_2l_standby(VI_PIPE ViPipe); +extern void SC5336_2l_restart(VI_PIPE ViPipe); +extern int SC5336_2l_write_register(VI_PIPE ViPipe, int addr, int data); +extern int SC5336_2l_read_register(VI_PIPE ViPipe, int addr); +extern void SC5336_2l_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int SC5336_2l_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC5336_2L_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos_param.h new file mode 100644 index 000000000..4bfdcb017 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_cmos_param.h @@ -0,0 +1,226 @@ +#ifndef __SC5336_2L_CMOS_PARAM_H_ +#define __SC5336_2L_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc5336_2L_cmos_ex.h" + +static const SC5336_2L_MODE_S g_astSC5336_2L_mode[SC5336_2L_MODE_NUM] = { + [SC5336_2L_MODE_1620P30] = { + .name = "1620p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 2880, + .u32Height = 1620, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2880, + .u32Height = 1620, + }, + .stMaxSize = { + .u32Width = 2880, + .u32Height = 1620, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 1.65, /* 1800 * 30 / 0x7FFF*/ + .u32HtsDef = 2560, /* NA */ + .u32VtsDef = 1800, + .stExp[0] = { + .u16Min = 2, + .u16Max = 1796,/* vts-4 */ + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u32Min = 1024, + .u32Max = 32768, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain[0] = { + .u32Min = 1024, + .u32Max = 16128, + .u32Def = 1024, + .u32Step = 1, + }, + }, +}; + +static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = { + { //iso 100 + {0.02792946062982082367, 3.36534714698791503906}, //B: slope, intercept + {0.02071751467883586884, 5.34583568572998046875}, //Gb: slope, intercept + {0.02110148966312408447, 5.02954530715942382813}, //Gr: slope, intercept + {0.02168512716889381409, 4.89776754379272460938}, //R: slope, intercept + }, + { //iso 200 + {0.03194080293178558350, 5.61192893981933593750}, //B: slope, intercept + {0.02428408525884151459, 7.94834280014038085938}, //Gb: slope, intercept + {0.02499442733824253082, 7.72430133819580078125}, //Gr: slope, intercept + {0.02584112435579299927, 7.20574426651000976563}, //R: slope, intercept + }, + { //iso 400 + {0.04612467437982559204, 6.88752269744873046875}, //B: slope, intercept + {0.03022909909486770630, 11.05101776123046875000}, //Gb: slope, intercept + {0.03175539523363113403, 10.60332489013671875000}, //Gr: slope, intercept + {0.03522306308150291443, 9.36425399780273437500}, //R: slope, intercept + }, + { //iso 800 + {0.06092500314116477966, 9.79670524597167968750}, //B: slope, intercept + {0.03984217345714569092, 15.30182266235351562500}, //Gb: slope, intercept + {0.04019560664892196655, 14.93132972717285156250}, //Gr: slope, intercept + {0.04470816254615783691, 13.26843166351318359375}, //R: slope, intercept + }, + { //iso 1600 + {0.08295634388923645020, 14.20334625244140625000}, //B: slope, intercept + {0.05075264349579811096, 20.99221038818359375000}, //Gb: slope, intercept + {0.05426201224327087402, 20.08068656921386718750}, //Gr: slope, intercept + {0.05945669487118721008, 19.02898788452148437500}, //R: slope, intercept + }, + { //iso 3200 + {0.09782519936561584473, 21.84967994689941406250}, //B: slope, intercept + {0.06690908223390579224, 26.53993988037109375000}, //Gb: slope, intercept + {0.06954573839902877808, 25.74129104614257812500}, //Gr: slope, intercept + {0.09061723947525024414, 22.98998260498046875000}, //R: slope, intercept + }, + { //iso 6400 + {0.14311420917510986328, 28.96467971801757812500}, //B: slope, intercept + {0.08148498833179473877, 37.93062591552734375000}, //Gb: slope, intercept + {0.08273542672395706177, 38.37096405029296875000}, //Gr: slope, intercept + {0.12093253433704376221, 33.31475067138671875000}, //R: slope, intercept + }, + { //iso 12800 + {0.17958122491836547852, 43.49506759643554687500}, //B: slope, intercept + {0.09839969873428344727, 55.43268966674804687500}, //Gb: slope, intercept + {0.10201884806156158447, 52.97607040405273437500}, //Gr: slope, intercept + {0.15302789211273193359, 47.54779434204101562500}, //R: slope, intercept + }, + { //iso 25600 + {0.25833165645599365234, 56.96470642089843750000}, //B: slope, intercept + {0.13260601460933685303, 74.69016265869140625000}, //Gb: slope, intercept + {0.14035490155220031738, 75.44366455078125000000}, //Gr: slope, intercept + {0.23465165495872497559, 60.52228164672851562500}, //R: slope, intercept + }, + { //iso 51200 + {0.37595292925834655762, 78.54853057861328125000}, //B: slope, intercept + {0.21475413441658020020, 102.12300872802734375000}, //Gb: slope, intercept + {0.20840260386466979980, 103.65763854980468750000}, //Gr: slope, intercept + {0.34428051114082336426, 87.83551025390625000000}, //R: slope, intercept + }, + { //iso 102400 + {0.51122575998306274414, 113.49224090576171875000}, //B: slope, intercept + {0.29245173931121826172, 154.26939392089843750000}, //Gb: slope, intercept + {0.31501635909080505371, 148.29017639160156250000}, //Gr: slope, intercept + {0.47034618258476257324, 124.06208038330078125000}, //R: slope, intercept + }, + { //iso 204800 + {0.67213481664657592773, 134.71751403808593750000}, //B: slope, intercept + {0.40368056297302246094, 189.80801391601562500000}, //Gb: slope, intercept + {0.43581819534301757813, 186.44682312011718750000}, //Gr: slope, intercept + {0.60127359628677368164, 160.66384887695312500000}, //R: slope, intercept + }, + { //iso 409600 + {0.81907004117965698242, 103.53753662109375000000}, //B: slope, intercept + {0.56758689880371093750, 134.64016723632812500000}, //Gb: slope, intercept + {0.60227775573730468750, 125.39395904541015625000}, //Gr: slope, intercept + {0.76318585872650146484, 111.18676757812500000000}, //R: slope, intercept + }, + { //iso 819200 + {0.81907004117965698242, 103.53753662109375000000}, //B: slope, intercept + {0.56758689880371093750, 134.64016723632812500000}, //Gb: slope, intercept + {0.60227775573730468750, 125.39395904541015625000}, //Gr: slope, intercept + {0.76318585872650146484, 111.18676757812500000000}, //R: slope, intercept + }, + { //iso 1638400 + {0.81907004117965698242, 103.53753662109375000000}, //B: slope, intercept + {0.56758689880371093750, 134.64016723632812500000}, //Gb: slope, intercept + {0.60227775573730468750, 125.39395904541015625000}, //Gr: slope, intercept + {0.76318585872650146484, 111.18676757812500000000}, //R: slope, intercept + }, + { //iso 3276800 + {0.81907004117965698242, 103.53753662109375000000}, //B: slope, intercept + {0.56758689880371093750, 134.64016723632812500000}, //Gb: slope, intercept + {0.60227775573730468750, 125.39395904541015625000}, //Gr: slope, intercept + {0.76318585872650146484, 111.18676757812500000000}, //R: slope, intercept + }, +} }; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {256, 256, 256, 256, 0, 0, 0, 0, +#ifdef ARCH_CV182X + 1092, 1092, 1092, 1092 +#endif + }, + + .stAuto = { + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, + {1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, + /*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092}, +#endif + }, + }, +}; + +struct combo_dev_attr_s SC5336_2l_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {0, 1, 2, -1, -1}, + .pn_swap = {0, 0, 0, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_VC, + .dphy = { + .enable = 1, + .hs_settle = 14, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __SC5336_2L_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_sensor_ctl.c new file mode 100644 index 000000000..3dcd1dc89 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/sms_sc5336_2L/sc5336_2L_sensor_ctl.c @@ -0,0 +1,463 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "sc5336_2L_cmos_ex.h" + +static void SC5336_2l_linear_1620p30_init(VI_PIPE ViPipe); + +const CVI_U8 SC5336_2l_i2c_addr = 0x30; /* I2C Address of SC5336_2L */ +const CVI_U32 SC5336_2l_addr_byte = 2; +const CVI_U32 SC5336_2l_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int SC5336_2l_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunSC5336_2L_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, SC5336_2l_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int SC5336_2l_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int SC5336_2l_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (SC5336_2l_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, SC5336_2l_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, SC5336_2l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (SC5336_2l_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int SC5336_2l_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (SC5336_2l_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (SC5336_2l_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, SC5336_2l_addr_byte + SC5336_2l_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void SC5336_2l_prog(VI_PIPE ViPipe, int *rom) +{ + int i = 0; + + while (1) { + int lookup = rom[i++]; + int addr = (lookup >> 16) & 0xFFFF; + int data = lookup & 0xFFFF; + + if (addr == 0xFFFE) + delay_ms(data); + else if (addr != 0xFFFF) + SC5336_2l_write_register(ViPipe, addr, data); + } +} + +void SC5336_2l_standby(VI_PIPE ViPipe) +{ + SC5336_2l_write_register(ViPipe, 0x0100, 0x00); +} + +void SC5336_2l_restart(VI_PIPE ViPipe) +{ + SC5336_2l_write_register(ViPipe, 0x0100, 0x00); + delay_ms(20); + SC5336_2l_write_register(ViPipe, 0x0100, 0x01); +} + +void SC5336_2l_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastSC5336_2L[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + SC5336_2l_write_register(ViPipe, + g_pastSC5336_2L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastSC5336_2L[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +#define SC5336_2L_CHIP_ID_HI_ADDR 0x3107 +#define SC5336_2L_CHIP_ID_LO_ADDR 0x3108 +#define SC5336_2L_CHIP_ID 0xce50 + +void SC5336_2l_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = 0; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x6; + break; + case ISP_SNS_FLIP: + val |= 0x60; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x66; + break; + default: + return; + } + + SC5336_2l_write_register(ViPipe, 0x3221, val); +} + +int SC5336_2l_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + usleep(4*1000); + if (SC5336_2l_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + nVal = SC5336_2l_read_register(ViPipe, SC5336_2L_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = SC5336_2l_read_register(ViPipe, SC5336_2L_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != SC5336_2L_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void SC5336_2l_init(VI_PIPE ViPipe) +{ + WDR_MODE_E enWDRMode; + CVI_BOOL bInit; + + bInit = g_pastSC5336_2L[ViPipe]->bInit; + enWDRMode = g_pastSC5336_2L[ViPipe]->enWDRMode; + + SC5336_2l_i2c_init(ViPipe); + + /* When sensor first init, config all registers */ + if (bInit == CVI_FALSE) { + if (enWDRMode == WDR_MODE_2To1_LINE) { + CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n"); + } else { + SC5336_2l_linear_1620p30_init(ViPipe); + } + } + /* When sensor switch mode(linear<->WDR or resolution), config different registers(if possible) */ + else { + if (enWDRMode == WDR_MODE_2To1_LINE) { + CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n"); + } else { + SC5336_2l_linear_1620p30_init(ViPipe); + } + } + g_pastSC5336_2L[ViPipe]->bInit = CVI_TRUE; +} + +void SC5336_2l_exit(VI_PIPE ViPipe) +{ + SC5336_2l_i2c_exit(ViPipe); +} + +/* 1620P30 and 1620P25 */ +static void SC5336_2l_linear_1620p30_init(VI_PIPE ViPipe) +{ + SC5336_2l_write_register(ViPipe, 0x0103, 0x01); + SC5336_2l_write_register(ViPipe, 0x36e9, 0x80); + SC5336_2l_write_register(ViPipe, 0x37f9, 0x80); + SC5336_2l_write_register(ViPipe, 0x301f, 0x01); + SC5336_2l_write_register(ViPipe, 0x320e, 0x07); + SC5336_2l_write_register(ViPipe, 0x320f, 0x08); + SC5336_2l_write_register(ViPipe, 0x3213, 0x04); + SC5336_2l_write_register(ViPipe, 0x3241, 0x00); + SC5336_2l_write_register(ViPipe, 0x3243, 0x01); + SC5336_2l_write_register(ViPipe, 0x3248, 0x02); + SC5336_2l_write_register(ViPipe, 0x3249, 0x0b); + SC5336_2l_write_register(ViPipe, 0x3253, 0x10); + SC5336_2l_write_register(ViPipe, 0x3258, 0x0c); + SC5336_2l_write_register(ViPipe, 0x3301, 0x0a); + SC5336_2l_write_register(ViPipe, 0x3305, 0x00); + SC5336_2l_write_register(ViPipe, 0x3306, 0x58); + SC5336_2l_write_register(ViPipe, 0x3308, 0x08); + SC5336_2l_write_register(ViPipe, 0x3309, 0xb0); + SC5336_2l_write_register(ViPipe, 0x330a, 0x00); + SC5336_2l_write_register(ViPipe, 0x330b, 0xc8); + SC5336_2l_write_register(ViPipe, 0x3314, 0x14); + SC5336_2l_write_register(ViPipe, 0x331f, 0xa1); + SC5336_2l_write_register(ViPipe, 0x3321, 0x10); + SC5336_2l_write_register(ViPipe, 0x3327, 0x14); + SC5336_2l_write_register(ViPipe, 0x3328, 0x0b); + SC5336_2l_write_register(ViPipe, 0x3329, 0x0e); + SC5336_2l_write_register(ViPipe, 0x3333, 0x10); + SC5336_2l_write_register(ViPipe, 0x3334, 0x40); + SC5336_2l_write_register(ViPipe, 0x3356, 0x10); + SC5336_2l_write_register(ViPipe, 0x3364, 0x5e); + SC5336_2l_write_register(ViPipe, 0x3390, 0x09); + SC5336_2l_write_register(ViPipe, 0x3391, 0x0b); + SC5336_2l_write_register(ViPipe, 0x3392, 0x0f); + SC5336_2l_write_register(ViPipe, 0x3393, 0x10); + SC5336_2l_write_register(ViPipe, 0x3394, 0x18); + SC5336_2l_write_register(ViPipe, 0x3395, 0x98); + SC5336_2l_write_register(ViPipe, 0x3396, 0x08); + SC5336_2l_write_register(ViPipe, 0x3397, 0x09); + SC5336_2l_write_register(ViPipe, 0x3398, 0x0f); + SC5336_2l_write_register(ViPipe, 0x3399, 0x0a); + SC5336_2l_write_register(ViPipe, 0x339a, 0x18); + SC5336_2l_write_register(ViPipe, 0x339b, 0x60); + SC5336_2l_write_register(ViPipe, 0x339c, 0xff); + SC5336_2l_write_register(ViPipe, 0x33ad, 0x0c); + SC5336_2l_write_register(ViPipe, 0x33ae, 0x68); + SC5336_2l_write_register(ViPipe, 0x33b2, 0x48); + SC5336_2l_write_register(ViPipe, 0x33b3, 0x28); + SC5336_2l_write_register(ViPipe, 0x33f8, 0x00); + SC5336_2l_write_register(ViPipe, 0x33f9, 0x70); + SC5336_2l_write_register(ViPipe, 0x33fa, 0x00); + SC5336_2l_write_register(ViPipe, 0x33fb, 0x90); + SC5336_2l_write_register(ViPipe, 0x33fc, 0x0b); + SC5336_2l_write_register(ViPipe, 0x33fd, 0x1f); + SC5336_2l_write_register(ViPipe, 0x349f, 0x03); + SC5336_2l_write_register(ViPipe, 0x34a6, 0x0b); + SC5336_2l_write_register(ViPipe, 0x34a7, 0x1f); + SC5336_2l_write_register(ViPipe, 0x34a8, 0x18); + SC5336_2l_write_register(ViPipe, 0x34a9, 0x08); + SC5336_2l_write_register(ViPipe, 0x34aa, 0x00); + SC5336_2l_write_register(ViPipe, 0x34ab, 0xe8); + SC5336_2l_write_register(ViPipe, 0x34ac, 0x01); + SC5336_2l_write_register(ViPipe, 0x34ad, 0x08); + SC5336_2l_write_register(ViPipe, 0x34f8, 0x1f); + SC5336_2l_write_register(ViPipe, 0x34f9, 0x08); + SC5336_2l_write_register(ViPipe, 0x3630, 0xc0); + SC5336_2l_write_register(ViPipe, 0x3631, 0x83); + SC5336_2l_write_register(ViPipe, 0x3632, 0x54); + SC5336_2l_write_register(ViPipe, 0x3633, 0x33); + SC5336_2l_write_register(ViPipe, 0x3641, 0x20); + SC5336_2l_write_register(ViPipe, 0x3670, 0x56); + SC5336_2l_write_register(ViPipe, 0x3674, 0xc0); + SC5336_2l_write_register(ViPipe, 0x3675, 0xa0); + SC5336_2l_write_register(ViPipe, 0x3676, 0xa0); + SC5336_2l_write_register(ViPipe, 0x3677, 0x83); + SC5336_2l_write_register(ViPipe, 0x3678, 0x86); + SC5336_2l_write_register(ViPipe, 0x3679, 0x8a); + SC5336_2l_write_register(ViPipe, 0x367c, 0x08); + SC5336_2l_write_register(ViPipe, 0x367d, 0x0f); + SC5336_2l_write_register(ViPipe, 0x367e, 0x08); + SC5336_2l_write_register(ViPipe, 0x367f, 0x0f); + SC5336_2l_write_register(ViPipe, 0x3696, 0x23); + SC5336_2l_write_register(ViPipe, 0x3697, 0x33); + SC5336_2l_write_register(ViPipe, 0x3698, 0x43); + SC5336_2l_write_register(ViPipe, 0x36a0, 0x09); + SC5336_2l_write_register(ViPipe, 0x36a1, 0x0f); + SC5336_2l_write_register(ViPipe, 0x36b0, 0x88); + SC5336_2l_write_register(ViPipe, 0x36b1, 0x92); + SC5336_2l_write_register(ViPipe, 0x36b2, 0xa4); + SC5336_2l_write_register(ViPipe, 0x36b3, 0xc7); + SC5336_2l_write_register(ViPipe, 0x36b4, 0x09); + SC5336_2l_write_register(ViPipe, 0x36b5, 0x0b); + SC5336_2l_write_register(ViPipe, 0x36b6, 0x0f); + SC5336_2l_write_register(ViPipe, 0x36ea, 0x0c); + SC5336_2l_write_register(ViPipe, 0x370f, 0x01); + SC5336_2l_write_register(ViPipe, 0x3721, 0x6c); + SC5336_2l_write_register(ViPipe, 0x3722, 0x89); + SC5336_2l_write_register(ViPipe, 0x3724, 0x21); + SC5336_2l_write_register(ViPipe, 0x3725, 0xb4); + SC5336_2l_write_register(ViPipe, 0x3727, 0x14); + SC5336_2l_write_register(ViPipe, 0x3771, 0x89); + SC5336_2l_write_register(ViPipe, 0x3772, 0x85); + SC5336_2l_write_register(ViPipe, 0x3773, 0x85); + SC5336_2l_write_register(ViPipe, 0x377a, 0x0b); + SC5336_2l_write_register(ViPipe, 0x377b, 0x1f); + SC5336_2l_write_register(ViPipe, 0x37fa, 0x0c); + SC5336_2l_write_register(ViPipe, 0x3901, 0x00); + SC5336_2l_write_register(ViPipe, 0x3904, 0x04); + SC5336_2l_write_register(ViPipe, 0x3905, 0x8c); + SC5336_2l_write_register(ViPipe, 0x391d, 0x04); + SC5336_2l_write_register(ViPipe, 0x391f, 0x49); + SC5336_2l_write_register(ViPipe, 0x3926, 0x21); + SC5336_2l_write_register(ViPipe, 0x3933, 0x80); + SC5336_2l_write_register(ViPipe, 0x3934, 0x0a); + SC5336_2l_write_register(ViPipe, 0x3935, 0x00); + SC5336_2l_write_register(ViPipe, 0x3936, 0xff); + SC5336_2l_write_register(ViPipe, 0x3937, 0x75); + SC5336_2l_write_register(ViPipe, 0x3938, 0x74); + SC5336_2l_write_register(ViPipe, 0x393c, 0x1e); + SC5336_2l_write_register(ViPipe, 0x39dc, 0x02); + SC5336_2l_write_register(ViPipe, 0x3e00, 0x00); + SC5336_2l_write_register(ViPipe, 0x3e01, 0x70); + SC5336_2l_write_register(ViPipe, 0x3e02, 0x00); + SC5336_2l_write_register(ViPipe, 0x3e09, 0x00); + SC5336_2l_write_register(ViPipe, 0x440d, 0x10); + SC5336_2l_write_register(ViPipe, 0x440e, 0x02); + SC5336_2l_write_register(ViPipe, 0x450d, 0x18); + SC5336_2l_write_register(ViPipe, 0x4819, 0x0b); + SC5336_2l_write_register(ViPipe, 0x481b, 0x06); + SC5336_2l_write_register(ViPipe, 0x481d, 0x17); + SC5336_2l_write_register(ViPipe, 0x481f, 0x05); + SC5336_2l_write_register(ViPipe, 0x4821, 0x0b); + SC5336_2l_write_register(ViPipe, 0x4823, 0x06); + SC5336_2l_write_register(ViPipe, 0x4825, 0x05); + SC5336_2l_write_register(ViPipe, 0x4827, 0x05); + SC5336_2l_write_register(ViPipe, 0x4829, 0x09); + SC5336_2l_write_register(ViPipe, 0x5780, 0x66); + SC5336_2l_write_register(ViPipe, 0x5787, 0x08); + SC5336_2l_write_register(ViPipe, 0x5788, 0x03); + SC5336_2l_write_register(ViPipe, 0x5789, 0x00); + SC5336_2l_write_register(ViPipe, 0x578a, 0x08); + SC5336_2l_write_register(ViPipe, 0x578b, 0x03); + SC5336_2l_write_register(ViPipe, 0x578c, 0x00); + SC5336_2l_write_register(ViPipe, 0x578d, 0x40); + SC5336_2l_write_register(ViPipe, 0x5790, 0x08); + SC5336_2l_write_register(ViPipe, 0x5791, 0x04); + SC5336_2l_write_register(ViPipe, 0x5792, 0x01); + SC5336_2l_write_register(ViPipe, 0x5793, 0x08); + SC5336_2l_write_register(ViPipe, 0x5794, 0x04); + SC5336_2l_write_register(ViPipe, 0x5795, 0x01); + SC5336_2l_write_register(ViPipe, 0x5799, 0x46); + SC5336_2l_write_register(ViPipe, 0x57aa, 0x2a); + SC5336_2l_write_register(ViPipe, 0x5ae0, 0xfe); + SC5336_2l_write_register(ViPipe, 0x5ae1, 0x40); + SC5336_2l_write_register(ViPipe, 0x5ae2, 0x38); + SC5336_2l_write_register(ViPipe, 0x5ae3, 0x30); + SC5336_2l_write_register(ViPipe, 0x5ae4, 0x0c); + SC5336_2l_write_register(ViPipe, 0x5ae5, 0x38); + SC5336_2l_write_register(ViPipe, 0x5ae6, 0x30); + SC5336_2l_write_register(ViPipe, 0x5ae7, 0x28); + SC5336_2l_write_register(ViPipe, 0x5ae8, 0x3f); + SC5336_2l_write_register(ViPipe, 0x5ae9, 0x34); + SC5336_2l_write_register(ViPipe, 0x5aea, 0x2c); + SC5336_2l_write_register(ViPipe, 0x5aeb, 0x3f); + SC5336_2l_write_register(ViPipe, 0x5aec, 0x34); + SC5336_2l_write_register(ViPipe, 0x5aed, 0x2c); + SC5336_2l_write_register(ViPipe, 0x36e9, 0x44); + SC5336_2l_write_register(ViPipe, 0x37f9, 0x44); + if (0x00 == SC5336_2l_read_register(ViPipe, 0x3040)) { + SC5336_2l_write_register(ViPipe, 0x3258, 0x0c); + SC5336_2l_write_register(ViPipe, 0x3249, 0x0b); + SC5336_2l_write_register(ViPipe, 0x3934, 0x0a); + SC5336_2l_write_register(ViPipe, 0x3935, 0x00); + SC5336_2l_write_register(ViPipe, 0x3937, 0x75); + } else if (0x03 == SC5336_2l_read_register(ViPipe, 0x3040)) { + SC5336_2l_write_register(ViPipe, 0x3258, 0x08); + SC5336_2l_write_register(ViPipe, 0x3249, 0x07); + SC5336_2l_write_register(ViPipe, 0x3934, 0x05); + SC5336_2l_write_register(ViPipe, 0x3935, 0x07); + SC5336_2l_write_register(ViPipe, 0x3937, 0x74); + } + SC5336_2l_write_register(ViPipe, 0x0100, 0x01); + SC5336_2l_default_reg_init(ViPipe); + + SC5336_2l_write_register(ViPipe, 0x0100, 0x01); + + printf("ViPipe:%d,===SC5336_2L 1620P 30fps 10bit LINE Init OK!===\n", ViPipe); +} diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/Makefile b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/Makefile new file mode 100644 index 000000000..c2c419ec9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_q03p.a +TARGET_SO = $(MW_LIB)/libsns_q03p.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJ) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos.c b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos.c new file mode 100644 index 000000000..cd81e2fd9 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos.c @@ -0,0 +1,841 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "q03p_cmos_ex.h" +#include "q03p_cmos_param.h" +// #include + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define Q03P_ID 03 +#define Q03P_I2C_ADDR_1 0x40 +#define Q03P_I2C_ADDR_2 0x44 +#define Q03P_I2C_ADDR_IS_VALID(addr) ((addr) == Q03P_I2C_ADDR_1 || (addr) == Q03P_I2C_ADDR_2) +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastQ03P[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define Q03P_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastQ03P[dev]) +#define Q03P_SENSOR_SET_CTX(dev, pstCtx) (g_pastQ03P[dev] = pstCtx) +#define Q03P_SENSOR_RESET_CTX(dev) (g_pastQ03P[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunQ03P_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16Q03P_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16Q03P_L2SMode[VI_MAX_PIPE_NUM] = {0}; +ISP_SNS_MIRRORFLIP_TYPE_E g_aeQ03P_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****Q03P Lines Range*****/ +#define Q03P_FULL_LINES_MAX (0xFFFF) + +/*****Q03P Register Address*****/ +#define Q03P_SHS1_ADDR 0x01 +#define Q03P_GAIN_ADDR 0x00 +#define Q03P_VMAX_ADDR 0x22 +#define Q03P_TABLE_END 0xff + +#define Q03P_RES_IS_1296P(w, h) ((w) <= 2304 && (h) <= 1296) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + const Q03P_MODE_S *pstMode; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astQ03P_mode[pstSnsState->u8ImgMode]; +#if 0 + memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S)); +#endif + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = Q03P_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = 2; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_DB; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + pstAeSnsDft->enBlcType = AE_BLC_TYPE_LINEAR; +#if 0 + pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0; + pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0; + + pstAeSnsDft->bAERouteExValid = CVI_FALSE; + pstAeSnsDft->stAERouteAttr.u32TotalNum = 0; + pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0; +#endif + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = pstMode->f32MaxFps; + pstAeSnsDft->f32MinFps = pstMode->f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u16Max; + pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u16Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u16Max; + pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u16Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? + g_au32InitExposure[ViPipe] : g_astQ03P_mode[Q03P_MODE_1296p30].stExp[0].u16Def; + + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 5; + pstAeSnsDft->u32MinIntTime = 1; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astQ03P_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astQ03P_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astQ03P_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case Q03P_MODE_1296p30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > Q03P_FULL_LINES_MAX) ? Q03P_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_DATA].u32Data = (u32VMAX & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_DATA].u32Data = ((u32VMAX & 0xFF00) >> 8); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 5; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + if ((u32IntTime[0] + 5) > pstSnsState->au32FL[0]) { + CVI_TRACE_SNS(CVI_DBG_ERR, "inttime over spec [%u, %u]\n", + u32IntTime[0], + pstSnsState->au32FL[0]); + return CVI_FAILURE; + } + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_DATA].u32Data = (u32IntTime[0] & 0xFF); + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_DATA].u32Data = ((u32IntTime[0] & 0xFF00) >> 8); + + return CVI_SUCCESS; + +} + +// static CVI_U32 gain_table[64] = { +// 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792, +// 1856, 1920, 1984, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200, +// 3328, 3456, 3584, 3712, 3840, 3968, 4096, 4352, 4608, 4864, 5120, 5376, 5632, +// 5888, 6144, 6400, 6656, 6912, 7168, 7424, 7680, 7936, 8192, 8704, 9216, 9728, +// 10240, 10752, 11264, 11776, 12288, 12800, 13312, 13824, 14336, 14848, 15360, +// 15872 +// }; +static CVI_U32 gain_table[96] = { + 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792, + 1856, 1920, 1984, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200, + 3328, 3456, 3584, 3712, 3840, 3968, 4096, 4352, 4608, 4864, 5120, 5376, 5632, + 5888, 6144, 6400, 6656, 6912, 7168, 7424, 7680, 7936, 8192, 8704, 9216, 9728, + 10240, 10752, 11264, 11776, 12288, 12800, 13312, 13824, 14336, 14848, 15360, + 15872,16384,17408,18432,19456,20480,21504,22528,23552,24576,25600,26624,27648, + 28672,29696,30720,31744,32768,34816,36864,38912,40960,43008,45056,47104,49152, + 51200,53248,55296,57344,59392,61440,63488 +}; +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + int i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= gain_table[95]) { + *pu32AgainLin = gain_table[95]; + *pu32AgainDb = 95; + return CVI_SUCCESS; + } + + for (i = 1; i < 95; i++) { + if (*pu32AgainLin < gain_table[i]) { + *pu32AgainLin = gain_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + *pu32DgainLin = 1024; + *pu32DgainDb = 0; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + /* linear mode */ + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_DATA].u32Data = (u32Again & 0xFF); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + //pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + //pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const Q03P_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astQ03P_mode[pstSnsState->u8ImgMode]; + + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = Q03P_MODE_1296p30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astQ03P_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunQ03P_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = q03p_i2c_addr; + pstI2c_data[i].u32AddrByteNum = q03p_addr_byte; + pstI2c_data[i].u32DataByteNum = q03p_data_byte; + } + + //DOL 2t1 Mode Regs + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + pstI2c_data[LINEAR_SHS1_0_DATA].u32RegAddr = Q03P_SHS1_ADDR; + + pstI2c_data[LINEAR_SHS1_1_DATA].u32RegAddr = Q03P_SHS1_ADDR + 1; + + pstI2c_data[LINEAR_AGAIN_DATA].u32RegAddr = Q03P_GAIN_ADDR; + + pstI2c_data[LINEAR_VMAX_0_DATA].u32RegAddr = Q03P_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_0_DATA].u8DelayFrmNum = 2; + + pstI2c_data[LINEAR_VMAX_1_DATA].u32RegAddr = Q03P_VMAX_ADDR + 1; + pstI2c_data[LINEAR_VMAX_1_DATA].u8DelayFrmNum = 2; + + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode); + return CVI_FAILURE; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (Q03P_RES_IS_1296P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = Q03P_MODE_1296p30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + if (pstSnsState->bInit == CVI_TRUE && g_aeQ03P_MirrorFip[ViPipe] != eSnsMirrorFlip) { + q03p_mirror_flip(ViPipe, eSnsMirrorFlip); + g_aeQ03P_MirrorFip[ViPipe] = eSnsMirrorFlip; + } +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const Q03P_MODE_S *pstMode = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = Q03P_MODE_1296p30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astQ03P_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &q03p_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astQ03P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astQ03P_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &q03p_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = q03p_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = q03p_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (Q03P_I2C_ADDR_IS_VALID(s32I2cAddr)) + q03p_i2c_addr = s32I2cAddr; +} + +static CVI_S32 q03p_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunQ03P_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + Q03P_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + Q03P_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + Q03P_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = Q03P_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, Q03P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, Q03P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, Q03P_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16Q03P_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16Q03P_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsQ03P_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = q03p_standby, + .pfnRestart = q03p_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = q03p_write_register, + .pfnReadReg = q03p_read_register, + .pfnSetBusInfo = q03p_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = q03p_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h new file mode 100644 index 000000000..0e41820f2 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h @@ -0,0 +1,83 @@ +#ifndef __Q03P_CMOS_EX_H_ +#define __Q03P_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +#ifndef UNUSED +#define UNUSED(x) ((void)(x)) +#endif + +enum q03p_linear_regs_e { + LINEAR_SHS1_0_DATA, + LINEAR_SHS1_1_DATA, + LINEAR_AGAIN_DATA, + LINEAR_VMAX_0_DATA, + LINEAR_VMAX_1_DATA, + LINEAR_REGS_NUM +}; + + +typedef enum _Q03P_MODE_E { + Q03P_MODE_1296p30 = 0, + Q03P_MODE_LINEAR_NUM, + Q03P_MODE_1296p30_WDR = Q03P_MODE_LINEAR_NUM, + Q03P_MODE_NUM +} Q03P_MODE_E; + +typedef struct _Q03P_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + CVI_U8 u8DgainReg; + CVI_U32 u32L2S_MAX; + char name[64]; +} Q03P_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastQ03P[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunQ03P_BusInfo[]; +extern CVI_U16 g_au16Q03P_GainMode[]; +extern CVI_U16 g_au16Q03P_L2SMode[]; +extern CVI_U8 q03p_i2c_addr; +extern const CVI_U32 q03p_addr_byte; +extern const CVI_U32 q03p_data_byte; +extern void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern void q03p_init(VI_PIPE ViPipe); +extern void q03p_exit(VI_PIPE ViPipe); +extern void q03p_standby(VI_PIPE ViPipe); +extern void q03p_restart(VI_PIPE ViPipe); +extern int q03p_write_register(VI_PIPE ViPipe, int addr, int data); +extern int q03p_read_register(VI_PIPE ViPipe, int addr); +extern int q03p_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __Q03P_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_param.h new file mode 100644 index 000000000..91d4d43f1 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_param.h @@ -0,0 +1,123 @@ +#ifndef __Q03P_CMOS_PARAM_H_ +#define __Q03P_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "q03p_cmos_ex.h" + +static const Q03P_MODE_S g_astQ03P_mode[Q03P_MODE_NUM] = { + [Q03P_MODE_1296p30] = { + .name = "1296p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 2304, + .u32Height = 1296, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 2304, + .u32Height = 1296, + }, + .stMaxSize = { + .u32Width = 2304, + .u32Height = 1296, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 0.64, /* 1400 * 30 / 0xFFFF */ + .u32HtsDef = 3600, + .u32VtsDef = 1400, + .stExp[0] = { + .u16Min = 1, + .u16Max = 1400, + .u16Def = 400, + .u16Step = 1, + }, + .stAgain[0] = { + .u16Min = 1024, + .u16Max = 15872,/* 1024 * 15.5 */ + .u16Def = 1024, + .u16Step = 1, + }, + .stDgain[0] = { + .u16Min = 1024, + .u16Max = 1024, + .u16Def = 1024, + .u16Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {64, 64, 64, 64, 0, 0, 0, 0. +#ifdef ARCH_CV182X + , 1040, 1040, 1040, 1040 +#endif + }, + + .stAuto = { + {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + 1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, +#endif + }, + }, +}; + +struct combo_dev_attr_s q03p_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_10BIT, + .lane_id = {2, 3, 4, -1, -1}, + .pn_swap = {0, 0, 0, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_24M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __Q03P_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_sensor_ctl.c new file mode 100644 index 000000000..207faafae --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_sensor_ctl.c @@ -0,0 +1,361 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "q03p_cmos_ex.h" + +#define Q03P_CHIP_ID_HI_ADDR 0x0A +#define Q03P_CHIP_ID_LO_ADDR 0x0B +#define Q03P_CHIP_ID 0x0843 + +//static void q03p_linear_1296p30_init(VI_PIPE ViPipe); +static void q03p_linear_1296p30_init(VI_PIPE ViPipe); +CVI_U8 q03p_i2c_addr = 0x40; /* I2C Address of Q03P */ +const CVI_U32 q03p_addr_byte = 1; +const CVI_U32 q03p_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int q03p_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunQ03P_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, q03p_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + printf("q03p_i2c_init success\n"); + return CVI_SUCCESS; +} + +int q03p_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int q03p_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + // add address byte 0 + buf[idx++] = addr & 0xff; + // printf("buff[%d]:%x\n",idx,buf[idx]); + ret = write(g_fd[ViPipe], buf, q03p_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + ret = read(g_fd[ViPipe], buf, q03p_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (q03p_data_byte == 1) { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int q03p_write_register(VI_PIPE ViPipe, int addr, int data) +{ + int idx = 0; + int ret; + char buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (q03p_addr_byte == 1) { + buf[idx] = addr & 0xff; + idx++; + } + if (q03p_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, q03p_addr_byte + q03p_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + // printf("q03p_write_register success\n"); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void q03p_prog(VI_PIPE ViPipe, int *rom) +{ + int i = 0; + + while (1) { + int lookup = rom[i++]; + int addr = (lookup >> 16) & 0xFFFF; + int data = lookup & 0xFFFF; + + if (addr == 0xFFFE) + delay_ms(data); + else if (addr != 0xFFFF) + q03p_write_register(ViPipe, addr, data); + } +} + +void q03p_standby(VI_PIPE ViPipe) +{ + q03p_write_register(ViPipe, 0x12, 0x40); +} + +void q03p_restart(VI_PIPE ViPipe) +{ + q03p_write_register(ViPipe, 0x12, 0x40); + delay_ms(20); + q03p_write_register(ViPipe, 0x12, 0x00); +} + +void q03p_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastQ03P[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + q03p_write_register(ViPipe, + g_pastQ03P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastQ03P[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + CVI_U8 val = q03p_read_register(ViPipe, 0x12) & ~0x30; + + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + break; + case ISP_SNS_MIRROR: + val |= 0x20; + break; + case ISP_SNS_FLIP: + val |= 0x10; + break; + case ISP_SNS_MIRROR_FLIP: + val |= 0x30; + break; + default: + return; + } + + q03p_write_register(ViPipe, 0x12, val); +} + +int q03p_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + usleep(4*1000); + if (q03p_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + printf("q03p_read_register,Q03P_CHIP_ID_HI_ADDR:%x\n ",Q03P_CHIP_ID_HI_ADDR); + nVal = q03p_read_register(ViPipe, Q03P_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + printf("q03p_read_register,Q03P_CHIP_ID_LO_ADDR:%x\n ",Q03P_CHIP_ID_LO_ADDR); + nVal = q03p_read_register(ViPipe, Q03P_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != Q03P_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +void q03p_init(VI_PIPE ViPipe) +{ + q03p_i2c_init(ViPipe); + + q03p_linear_1296p30_init(ViPipe); + g_pastQ03P[ViPipe]->bInit = CVI_TRUE; +} + +void q03p_exit(VI_PIPE ViPipe) +{ + q03p_i2c_exit(ViPipe); +} + +static void q03p_linear_1296p30_init(VI_PIPE ViPipe) +{ + q03p_write_register(ViPipe, 0x12,0x40); + q03p_write_register(ViPipe, 0x48,0x96); + q03p_write_register(ViPipe, 0x48,0x16); + q03p_write_register(ViPipe, 0x0E,0x11); + q03p_write_register(ViPipe, 0x0F,0x04); + q03p_write_register(ViPipe, 0x10,0x3F); + q03p_write_register(ViPipe, 0x11,0x80); + q03p_write_register(ViPipe, 0x46,0x00); + q03p_write_register(ViPipe, 0x0D,0xA0); + q03p_write_register(ViPipe, 0x57,0x67); + q03p_write_register(ViPipe, 0x58,0x1F); + q03p_write_register(ViPipe, 0x5F,0x41); + q03p_write_register(ViPipe, 0x60,0x28); + q03p_write_register(ViPipe, 0x64,0xD2); + q03p_write_register(ViPipe, 0xA5,0x4F); + q03p_write_register(ViPipe, 0x20,0x84); + q03p_write_register(ViPipe, 0x21,0x03); + q03p_write_register(ViPipe, 0x22,0x78); + q03p_write_register(ViPipe, 0x23,0x05); + q03p_write_register(ViPipe, 0x24,0x40); + q03p_write_register(ViPipe, 0x25,0x10); + q03p_write_register(ViPipe, 0x26,0x52); + q03p_write_register(ViPipe, 0x27,0x74); + q03p_write_register(ViPipe, 0x28,0x15); + q03p_write_register(ViPipe, 0x29,0x03); + q03p_write_register(ViPipe, 0x2A,0x6E); + q03p_write_register(ViPipe, 0x2B,0x13); + q03p_write_register(ViPipe, 0x2C,0x00); + q03p_write_register(ViPipe, 0x2D,0x00); + q03p_write_register(ViPipe, 0x2E,0x4A); + q03p_write_register(ViPipe, 0x2F,0x64); + q03p_write_register(ViPipe, 0x41,0x84); + q03p_write_register(ViPipe, 0x42,0x24); + q03p_write_register(ViPipe, 0x47,0x42); + q03p_write_register(ViPipe, 0x76,0x40); + q03p_write_register(ViPipe, 0x77,0x0B); + q03p_write_register(ViPipe, 0x80,0x03); + q03p_write_register(ViPipe, 0xAF,0x22); + q03p_write_register(ViPipe, 0xAB,0x00); + q03p_write_register(ViPipe, 0x1D,0x00); + q03p_write_register(ViPipe, 0x1E,0x04); + q03p_write_register(ViPipe, 0x6C,0x40); + q03p_write_register(ViPipe, 0x6E,0x2C); + q03p_write_register(ViPipe, 0x70,0xD9); + q03p_write_register(ViPipe, 0x71,0xD5); + q03p_write_register(ViPipe, 0x72,0xD2); + q03p_write_register(ViPipe, 0x73,0x59); + q03p_write_register(ViPipe, 0x74,0x02); + q03p_write_register(ViPipe, 0x78,0x98); + q03p_write_register(ViPipe, 0x89,0x01); + q03p_write_register(ViPipe, 0x6B,0x20); + q03p_write_register(ViPipe, 0x86,0x40); + q03p_write_register(ViPipe, 0x0C,0x10); + q03p_write_register(ViPipe, 0x31,0x10); + q03p_write_register(ViPipe, 0x32,0x31); + q03p_write_register(ViPipe, 0x33,0x5C); + q03p_write_register(ViPipe, 0x34,0x24); + q03p_write_register(ViPipe, 0x35,0x20); + q03p_write_register(ViPipe, 0x3A,0xA0); + q03p_write_register(ViPipe, 0x3B,0x00); + q03p_write_register(ViPipe, 0x3C,0xDC); + q03p_write_register(ViPipe, 0x3D,0xF0); + q03p_write_register(ViPipe, 0x3E,0xBC); + q03p_write_register(ViPipe, 0x56,0x10); + q03p_write_register(ViPipe, 0x59,0x54); + q03p_write_register(ViPipe, 0x5A,0x00); + q03p_write_register(ViPipe, 0x61,0x00); + q03p_write_register(ViPipe, 0x85,0x4A); + q03p_write_register(ViPipe, 0x8A,0x00); + q03p_write_register(ViPipe, 0x8D,0x67); + q03p_write_register(ViPipe, 0x91,0x08); + q03p_write_register(ViPipe, 0x94,0xA0); + q03p_write_register(ViPipe, 0x9C,0x61); + q03p_write_register(ViPipe, 0xA7,0x00); + q03p_write_register(ViPipe, 0xA9,0x4C); + q03p_write_register(ViPipe, 0x5B,0xA0); + q03p_write_register(ViPipe, 0x5C,0x84); + q03p_write_register(ViPipe, 0x5D,0x86); + q03p_write_register(ViPipe, 0x5E,0x03); + q03p_write_register(ViPipe, 0x65,0x02); + q03p_write_register(ViPipe, 0x66,0xC4); + q03p_write_register(ViPipe, 0x67,0x48); + q03p_write_register(ViPipe, 0x68,0x00); + q03p_write_register(ViPipe, 0x69,0x74); + q03p_write_register(ViPipe, 0x6A,0x22); + q03p_write_register(ViPipe, 0x7A,0x77); + q03p_write_register(ViPipe, 0x8F,0x90); + q03p_write_register(ViPipe, 0x45,0x01); + q03p_write_register(ViPipe, 0xA4,0xC7); + q03p_write_register(ViPipe, 0x97,0x20); + q03p_write_register(ViPipe, 0x13,0x81); + q03p_write_register(ViPipe, 0x96,0x84); + q03p_write_register(ViPipe, 0x4A,0x01); + q03p_write_register(ViPipe, 0xB1,0x00); + q03p_write_register(ViPipe, 0xA1,0x0F); + q03p_write_register(ViPipe, 0xB5,0x0C); + q03p_write_register(ViPipe, 0x7E,0x48); + q03p_write_register(ViPipe, 0x9E,0xF0); + q03p_write_register(ViPipe, 0x50,0x02); + q03p_write_register(ViPipe, 0x49,0x10); + q03p_write_register(ViPipe, 0x7F,0x56); + q03p_write_register(ViPipe, 0x8C,0xFF); + q03p_write_register(ViPipe, 0x8E,0x00); + q03p_write_register(ViPipe, 0x8B,0x01); + q03p_write_register(ViPipe, 0xBC,0x11); + q03p_write_register(ViPipe, 0x82,0x00); + q03p_write_register(ViPipe, 0x19,0x20); + q03p_write_register(ViPipe, 0x1B,0x4F); + q03p_write_register(ViPipe, 0x12,0x00); + q03p_write_register(ViPipe, 0x48,0x96); + q03p_write_register(ViPipe, 0x48,0x16); + q03p_default_reg_init(ViPipe); + printf("ViPipe:%d,===Q03P 1296P 30fps 10bit LINE Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/panel/cv180x/dsi_gm8775c.h b/middleware/v2/component/panel/cv180x/dsi_gm8775c.h index 0344a4bf0..fece5a093 100644 --- a/middleware/v2/component/panel/cv180x/dsi_gm8775c.h +++ b/middleware/v2/component/panel/cv180x/dsi_gm8775c.h @@ -154,7 +154,7 @@ const struct dsc_instr dsi_init_cmds_gm8775c[] = { // {.delay = 0, .data_type = 0x23, .size = 2, .data = data_gm8775c_41 } #endif }; -#endif + #else #error "MIPI_TX_PARAM multi-delcaration!!" #endif // _MIPI_TX_PARAM_GM8775C_1080P_H_ diff --git a/middleware/v2/component/panel/cv180x/dsi_lt9611.h b/middleware/v2/component/panel/cv180x/dsi_lt9611.h new file mode 100644 index 000000000..0c97b1b8e --- /dev/null +++ b/middleware/v2/component/panel/cv180x/dsi_lt9611.h @@ -0,0 +1,140 @@ +#ifndef _HDMI_LT9611_H_ +#define _HDMI_LT9611_H_ + +#include "linux/cvi_comm_video.h" + +static struct combo_dev_cfg_s dev_cfg_lt9611_1920x1080_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 44, + .vid_hbp_pixels = 148, + .vid_hfp_pixels = 88, + .vid_hline_pixels = 1920, + .vid_vsa_lines = 5, + .vid_vbp_lines = 36, + .vid_vfp_lines = 4, + .vid_active_lines = 1080, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 148500, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1920x1080_30Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 44, + .vid_hbp_pixels = 148, + .vid_hfp_pixels = 88, + .vid_hline_pixels = 1920, + .vid_vsa_lines = 5, + .vid_vbp_lines = 36, + .vid_vfp_lines = 4, + .vid_active_lines = 1080, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 74250, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1280x720_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 40, + .vid_hbp_pixels = 220, + .vid_hfp_pixels = 110, + .vid_hline_pixels = 1280, + .vid_vsa_lines = 5, + .vid_vbp_lines = 20, + .vid_vfp_lines = 5, + .vid_active_lines = 720, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 74250, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1024x768_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 136, + .vid_hbp_pixels = 160, + .vid_hfp_pixels = 24, + .vid_hline_pixels = 1024, + .vid_vsa_lines = 6, + .vid_vbp_lines = 29, + .vid_vfp_lines = 3, + .vid_active_lines = 768, + .vid_vsa_pos_polarity = false, + .vid_hsa_pos_polarity = false, + }, + .pixel_clk = 65000, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1280x1024_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 112, + .vid_hbp_pixels = 248, + .vid_hfp_pixels = 48, + .vid_hline_pixels = 1280, + .vid_vsa_lines = 3, + .vid_vbp_lines = 38, + .vid_vfp_lines = 1, + .vid_active_lines = 1024, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 108000, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1600x1200_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 192, + .vid_hbp_pixels = 304, + .vid_hfp_pixels = 64, + .vid_hline_pixels = 1600, + .vid_vsa_lines = 3, + .vid_vbp_lines = 46, + .vid_vfp_lines = 1, + .vid_active_lines = 1200, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 162000, +}; + +static struct hs_settle_s hs_timing_cfg_lt9611 = { .prepare = 6, .zero = 32, .trail = 5 }; + +#endif // _HDMI_LT9611_H_ \ No newline at end of file diff --git a/middleware/v2/component/panel/cv181x/dsi_gm8775c.h b/middleware/v2/component/panel/cv181x/dsi_gm8775c.h index 0344a4bf0..fece5a093 100644 --- a/middleware/v2/component/panel/cv181x/dsi_gm8775c.h +++ b/middleware/v2/component/panel/cv181x/dsi_gm8775c.h @@ -154,7 +154,7 @@ const struct dsc_instr dsi_init_cmds_gm8775c[] = { // {.delay = 0, .data_type = 0x23, .size = 2, .data = data_gm8775c_41 } #endif }; -#endif + #else #error "MIPI_TX_PARAM multi-delcaration!!" #endif // _MIPI_TX_PARAM_GM8775C_1080P_H_ diff --git a/middleware/v2/component/panel/cv181x/dsi_lt9611.h b/middleware/v2/component/panel/cv181x/dsi_lt9611.h new file mode 100644 index 000000000..0c97b1b8e --- /dev/null +++ b/middleware/v2/component/panel/cv181x/dsi_lt9611.h @@ -0,0 +1,140 @@ +#ifndef _HDMI_LT9611_H_ +#define _HDMI_LT9611_H_ + +#include "linux/cvi_comm_video.h" + +static struct combo_dev_cfg_s dev_cfg_lt9611_1920x1080_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 44, + .vid_hbp_pixels = 148, + .vid_hfp_pixels = 88, + .vid_hline_pixels = 1920, + .vid_vsa_lines = 5, + .vid_vbp_lines = 36, + .vid_vfp_lines = 4, + .vid_active_lines = 1080, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 148500, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1920x1080_30Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 44, + .vid_hbp_pixels = 148, + .vid_hfp_pixels = 88, + .vid_hline_pixels = 1920, + .vid_vsa_lines = 5, + .vid_vbp_lines = 36, + .vid_vfp_lines = 4, + .vid_active_lines = 1080, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 74250, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1280x720_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 40, + .vid_hbp_pixels = 220, + .vid_hfp_pixels = 110, + .vid_hline_pixels = 1280, + .vid_vsa_lines = 5, + .vid_vbp_lines = 20, + .vid_vfp_lines = 5, + .vid_active_lines = 720, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 74250, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1024x768_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 136, + .vid_hbp_pixels = 160, + .vid_hfp_pixels = 24, + .vid_hline_pixels = 1024, + .vid_vsa_lines = 6, + .vid_vbp_lines = 29, + .vid_vfp_lines = 3, + .vid_active_lines = 768, + .vid_vsa_pos_polarity = false, + .vid_hsa_pos_polarity = false, + }, + .pixel_clk = 65000, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1280x1024_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 112, + .vid_hbp_pixels = 248, + .vid_hfp_pixels = 48, + .vid_hline_pixels = 1280, + .vid_vsa_lines = 3, + .vid_vbp_lines = 38, + .vid_vfp_lines = 1, + .vid_active_lines = 1024, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 108000, +}; + +static struct combo_dev_cfg_s dev_cfg_lt9611_1600x1200_60Hz = { + .devno = 0, + .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, + .lane_pn_swap = {false, false, false, false, false}, + .output_mode = OUTPUT_MODE_DSI_VIDEO, + .video_mode = BURST_MODE, + .output_format = OUT_FORMAT_RGB_24_BIT, + .sync_info = { + .vid_hsa_pixels = 192, + .vid_hbp_pixels = 304, + .vid_hfp_pixels = 64, + .vid_hline_pixels = 1600, + .vid_vsa_lines = 3, + .vid_vbp_lines = 46, + .vid_vfp_lines = 1, + .vid_active_lines = 1200, + .vid_vsa_pos_polarity = true, + .vid_hsa_pos_polarity = true, + }, + .pixel_clk = 162000, +}; + +static struct hs_settle_s hs_timing_cfg_lt9611 = { .prepare = 6, .zero = 32, .trail = 5 }; + +#endif // _HDMI_LT9611_H_ \ No newline at end of file diff --git a/middleware/v2/cv180x/ko/cv180x_vcodec.ko b/middleware/v2/cv180x/ko/cv180x_vcodec.ko index 91487cdab6114f01c9fb85d67921d2efe65e5c09..a2439f18b4fc5672a1f6d38e2bdfc4a7c6276273 100644 GIT binary patch delta 64 zcmV-G0KfmJ*8`~61CUS@$=B%|av1INq0dlibFcAV0G%YeV WEoU=0Ff(Q~H)LgIHZikyGBUY(Dj6XF diff --git a/middleware/v2/cv180x/ko/cv180x_vi.ko b/middleware/v2/cv180x/ko/cv180x_vi.ko index af4d64c7e10fbe2a97d70826e68a2af13be93b7c..7a672971351cc21f86c770e2a2ec651705bc4317 100644 GIT binary patch literal 617856 zcmcG%3tUvy+AzK^vu8610uG7@l(Jz^-ttr`csX&vU?xyG=37{H@~;j;Vi$SSOv~>D z_v{%5B&7|GhMuEnsQgbJ3vp6YLPb(f-YO|id4S=f<^^jMF|qGiduGkvGfMXMd%u1^ zWA@(b@~me)>siljJ?p>IChIAZB=CPE@e?6G;kWQNTO&Q7Z^_cHWI{*85-Ru|3jb*M zXUKex;G)jw?kgIHFSjf&h+O2iWVyx05`<`B3A(+JSZ_=!UtW+BqHc?BwlVNtV2E$h zBGfmCvb2=eVbR9|rZb3`5wU@6G~(sGJoo zP}wQu@`8fdR2V6aFZ;aVhFvgdS%LURVz*u>wswZWz;a=9%L~TkN8i#pGrBS_PrH!S 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