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[middleware] add cvitek's multimedia framework

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Change-Id: Iffc3cf32b99b95ba3ba534081a97881a2e004a14
This commit is contained in:
sam.xiang
2023-02-23 00:21:19 +08:00
parent cda448c3e9
commit 89f501af2a
784 changed files with 303117 additions and 0 deletions
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middleware/v2/.gitignore vendored Normal file
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*.d
*.o
*.a
*.so
*.dep
*.dwo
lib
bin
include
tags
*_asan
sample/audio/sample_audio
sample/audio/sample_audio_aec
sample/audio/sample_audio_nr
sample/audio/sample_audio_resample
sample/audio/sample_audio_transcode
sample/audio/sample_audio_rtos
sample/cipher/sample_cipher
sample/cvg/sample_cvg
sample/mipi_tx/sample_dsi
sample/fisheye/sample_fisheye
sample/overlay/sample_overlay
sample/region/sample_region
sample/venc/sample_vcodec
sample/vdec/sample_vdec
sample/venc/sample_venc
sample/vio/sample_vio
sample/vdecvo/sample_vdecvo
sample/multivenc/sample_multivenc
sample/ir_auto/ir_auto
sample/ive/sample_16bitto8bit
sample/ive/sample_add
sample/ive/sample_and
sample/ive/sample_bernsen
sample/ive/sample_bgmodel
sample/ive/sample_cannyedge
sample/ive/sample_cannyhysedge
sample/ive/sample_csc
sample/ive/sample_dilate
sample/ive/sample_dma
sample/ive/sample_erode
sample/ive/sample_filter
sample/ive/sample_filterandcsc
sample/ive/sample_framediffmotion
sample/ive/sample_gmm
sample/ive/sample_gmm2
sample/ive/sample_gradfg
sample/ive/sample_hist
sample/ive/sample_integ
sample/ive/sample_lbp
sample/ive/sample_magandang
sample/ive/sample_map
sample/ive/sample_ncc
sample/ive/sample_normgrad
sample/ive/sample_or
sample/ive/sample_ordstatfilter
sample/ive/sample_query
sample/ive/sample_resize
sample/ive/sample_sad
sample/ive/sample_sobel
sample/ive/sample_stcandicorner
sample/ive/sample_sub
sample/ive/sample_thresh
sample/ive/sample_thresh_S16
sample/ive/sample_thresh_U16
sample/ive/sample_xor
sample/osdc/sample_osdc
sample/scene_auto/sample_scene_auto
sample/sensor_test/sensor_test
self_test/cvi_test/cvi_test
self_test/cvi_test/res
self_test/tpu/sample_tpu
self_test/vip_fpga/vip_fpga
self_test/vi_ut/vi_ut
self_test/vpss_ut/vpss_ut
self_test/vpss_ut/vpss_ut_client
self_test/vo_ut/vo_ut
self_test/rgn_ut/rgn_ut
self_test/dwa_ut/dwa_ut
self_test/vb_ut/vb_ut
self_test/sys_ut/sys_ut
self_test/fast_image_ut/fast_image_ut
self_test/audio/aud_auto_test_sample/cvi_auto_play
self_test/audio/aud_auto_test_sample/cvi_auto_record
self_test/audio/aud_auto_test_sample/cvi_auto_special
self_test/audio/audio_aec/sample_audio_aec
self_test/audio/audio_anr/sample_audio_nr
self_test/audio/audio_pcm/sample_audio_internal
self_test/audio/audio_resample/sample_audio_resample
self_test/audio/audio_transcode/sample_audio_transcode
modules/venc/vc/jpeg/driver/bm_jpg_test
modules/venc/vc/jpeg/driver/bmjpuapi/bmjpegdec
modules/venc/vc/jpeg/driver/bmjpuapi/bmjpegenc
modules/venc/vc/vcodec/codebase/cvi_h265_enc_test
modules/venc/vc/vcodec/codebase/cvi_h264_dec
modules/venc/vc/vcodec/codebase/cvi_h265_dec
modules/venc/vc/jpeg/driver/cvi_jpg_codec
modules/venc/vc/vcodec/codebase/sample/cvi_vcodec_version.h
modules/venc/vc/jpeg/driver/include/version.h
.vscode/settings.json
modules/isp

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SHELL = /bin/bash
include $(BUILD_PATH)/.config
## setup path ##
ROOT_DIR:=$(shell dirname $(realpath $(PARAM_FILE)))
export MW_PATH:= $(ROOT_DIR)
export MW_INC := $(MW_PATH)/include
export MW_LIB := $(MW_PATH)/lib
export MW_3RD_LIB := $(MW_PATH)/lib/3rd
ifeq ($(KERNEL_DIR), )
KERNEL_PATH ?= $(ROOT_DIR)/../../$(KERNEL_SRC)
ifeq ($(PROJECT_FULLNAME), )
$(error PROJECT_FULLNAME not defined! Please check!)
else
KERNEL_DIR = $(KERNEL_PATH)/build/$(PROJECT_FULLNAME)
endif
endif
ifeq ($(SDK_VER), 32bit)
export CROSS_COMPILE = $(CROSS_COMPILE_32)
SYSROOT := $(ROOT_DIR)/../../ramdisk/sysroot/sysroot-glibc-linaro-2.23-2017.05-arm-linux-gnueabihf/
KERNEL_INC := $(KERNEL_DIR)/arm/usr/include
OPT_LEVEL := -O3
else ifeq ($(SDK_VER), 64bit)
export CROSS_COMPILE = $(CROSS_COMPILE_64)
SYSROOT := $(ROOT_DIR)/../../ramdisk/sysroot/sysroot-glibc-linaro-2.23-2017.05-aarch64-linux-gnu/
KERNEL_INC := $(KERNEL_DIR)/arm64/usr/include
OPT_LEVEL := -O3
else ifeq ($(SDK_VER), uclibc)
export CROSS_COMPILE = $(CROSS_COMPILE_UCLIBC)
SYSROOT := $(ROOT_DIR)/../../ramdisk/sysroot/sysroot-uclibc/
KERNEL_INC := $(KERNEL_DIR)/arm/usr/include
OPT_LEVEL := -Os
else ifeq ($(SDK_VER), glibc_riscv64)
export CROSS_COMPILE = $(CROSS_COMPILE_GLIBC_RISCV64)
SYSROOT := $(ROOT_DIR)/../../host-tools/gcc/riscv64-linux-x86_64/sysroot
KERNEL_INC := $(KERNEL_DIR)/riscv/usr/include
OPT_LEVEL := -Os
OPT_LEVEL += -march=rv64imafdcvxthead -mcmodel=medany -mabi=lp64dv
else ifeq ($(SDK_VER), musl_riscv64)
export CROSS_COMPILE = $(CROSS_COMPILE_MUSL_RISCV64)
SYSROOT := $(ROOT_DIR)/../../host-tools/gcc/riscv64-linux-musl-x86_64/sysroot
KERNEL_INC := $(KERNEL_DIR)/riscv/usr/include
OPT_LEVEL := -Os
OPT_LEVEL += -march=rv64imafdcvxthead -mcmodel=medany -mabi=lp64d
endif
## INCLUDE PATH ##
COMMON_INC = $(MW_PATH)/sample/common/include
SYS_INC = $(MW_PATH)/modules/sys/include
VPU_INC = $(MW_PATH)/modules/vpu/include
AUD_INC = $(MW_PATH)/modules/audio/include
OSDC_INC = $(MW_PATH)/modules/osdc/include
BIN_INC = $(MW_PATH)/modules/bin/include
MODULES_DIR = $(shell if [ -d $(MW_PATH)/modules ]; then echo "exist"; else echo "noexist"; fi)
ifeq ("$(MODULES_DIR)" , "noexist")
ISP_INC = $(MW_INC)/isp/$(shell echo $(CHIP_ARCH) | tr A-Z a-z)
else
ISP_INC = $(MW_PATH)/modules/isp/include/$(shell echo $(CHIP_ARCH) | tr A-Z a-z)
endif
## LIBRARY ##
ISP_LIB := -lisp -lawb -lae -laf
ISP_OBJ := $(MW_LIB)/libisp.a $(MW_LIB)/libae.a $(MW_LIB)/libawb.a $(MW_LIB)/libaf.a
ifeq ($(CHIP_ARCH), CV183X)
else ifeq ($(CHIP_ARCH), $(filter $(CHIP_ARCH), CV182X MARS PHOBOS CV181X CV180X))
ISP_LIB += -lisp_algo
ISP_OBJ += $(MW_LIB)/libisp_algo.a
else
ifeq ($(SUBTYPE), fpga)
ISP_LIB += -lisp_algo
ISP_OBJ += $(MW_LIB)/libisp_algo.a
else
$(error UNKNOWN chip architecture - $(CHIP_ARCH))
endif
endif
## DEFINES ##
export PROJ_CFLAGS = -DF10
ifeq ($(SUBTYPE), fpga)
export FPGA_PORTING := true
else
export FPGA_PORTING := false
endif
MW_GLIBC_DEPENDENT := $(SYSROOT)/lib
## GCC COMPILER ##
CC = $(CROSS_COMPILE)gcc
CXX = $(CROSS_COMPILE)g++
AR = $(CROSS_COMPILE)ar
LD = $(CROSS_COMPILE)ld
NM = $(CROSS_COMPILE)nm
RANLIB = $(CROSS_COMPILE)ranlib
STRIP = $(CROSS_COMPILE)strip
OBJCOPY = $(CROSS_COMPILE)objcopy
### COMMON COMPILER FLAGS ###
#
# export TARGET_PACKAGES_INCLUDE and TARGET_PACKAGES_LIBDIR from build/Makefile
#
WARNING_LEVEL=-Wall -Wextra -Werror
#Generate object files by CC
CFLAGS = $(OPT_LEVEL) -std=gnu11 -g $(WARNING_LEVEL) -fPIC -ffunction-sections -fdata-sections -Wl,--gc-sections $(CVI_TARGET_PACKAGES_INCLUDE)
#Generate object files by CXX
CXXFLAGS = $(OPT_LEVEL) -std=gnu++11 -g $(WARNING_LEVEL) -fPIC -ffunction-sections -fdata-sections -Wl,--gc-sections $(CVI_TARGET_PACKAGES_INCLUDE)
#Generate dependencies files by CC and CXX
DEPFLAGS = -MMD
### COMMON AR and LD FLAGS ###
#Generate archive file by AR
ARFLAGS = rcs
#Generate shared library by LD
LDFLAGS = -shared -fPIC --gc-sections -export-dynamic -L$(MW_LIB) -L$(MW_3RD_LIB) --sysroot $(SYSROOT) $(CVI_TARGET_PACKAGES_LIBDIR)
### COMMON ELF FLAGS ###
#Generate ELF files by CC and CXX
ELFFLAGS = $(OPT_LEVEL) -Wl,--gc-sections -rdynamic -L$(MW_LIB) -L$(MW_3RD_LIB) $(CVI_TARGET_PACKAGES_LIBDIR)
ifeq ($(SDK_VER), glibc_riscv64)
CFLAGS += -mno-ldd
CXXFLAGS += -mno-ldd
else ifeq ($(SDK_VER), musl_riscv64)
CFLAGS += -mno-ldd
CXXFLAGS += -mno-ldd
endif
ifeq ($(CONFIG_DEBUG_INFO), y)
ifeq ($(CONFIG_DEBUG_INFO_SPLIT), y)
CFLAGS += -gsplit-dwarf
CXXFLAGS += -gsplit-dwarf
else ifeq ($(CONFIG_DEBUG_INFO_DWARF4), y)
CFLAGS += -gdwarf-4
CXXFLAGS += -gdwarf-4
else ifeq ($(CONFIG_DEBUG_INFO_REDUCED), y)
CFLAGS += -femit-struct-debug-baseonly -fno-var-tracking
CXXFLAGS += -femit-struct-debug-baseonly -fno-var-tracking
else
CFLAGS += -Og
CXXFLAGS += -Og
endif
endif
ifeq ($(MTRACE), y)
ifneq ($(SDK_VER),uclibc)
CFLAGS += -DMTRACE
endif
endif
ifeq ($(FPGA_PORTING), true)
CFLAGS += -DFPGA_PORTING
endif
ifeq ($(CONFIG_DDR_64MB_SIZE), y)
CFLAGS += -DDDR_64MB_SIZE
endif
SAMPLE_STATIC ?= 1
SELF_TEST_STATIC ?= 1
SAMPLE_TPU_ENABLE ?= 0
ENABLE_ISP_C906L = 0
ifeq ($(CONFIG_ENABLE_SDK_ASAN), y)
CFLAGS += -fsanitize=address -fno-omit-frame-pointer
CXXFLAGS += -fsanitize=address -fno-omit-frame-pointer
ELFFLAGS += -fsanitize=address -fno-omit-frame-pointer -g
LDFLAGS += -fsanitize=address -fno-omit-frame-pointer -fno-common -g
SAMPLE_STATIC = 0
SELF_TEST_STATIC = 0
endif
CFLAGS += -DARCH_$(CHIP_ARCH)
ifeq ("$(CVIARCH)", "CV181X")
CFLAGS += -D__CV181X__
endif
ifeq ("$(CVIARCH)", "CV180X")
CFLAGS += -D__CV180X__
endif
## COLOR ##
BLACK = "\e[30;1m"
RED = "\e[31;1m"
GREEN = "\e[32;1m"
YELLOW = "\e[33;1m"
BLUE = "\e[34;1m"
PURPLE = "\e[35;1m"
CYAN = "\e[36;1m"
WHITE = "\e[37;1m"
END= "\e[0m"

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SHELL = /bin/bash
include $(BUILD_PATH)/.config
include sensor.mk
chip_arch = $(shell echo $(CVIARCH) | tr A-Z a-z)
all:
pushd sensor/$(chip_arch) && \
$(MAKE) all && \
popd;
clean:
pushd sensor/$(chip_arch) && \
$(MAKE) clean && \
popd;

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ifeq ($(CHIP_ARCH),CV183X)
sensor-$(CONFIG_SENSOR_GCORE_GC2053) += gcore_gc2053
sensor-$(CONFIG_SENSOR_GCORE_GC2053_SLAVE) += gcore_gc2053_slave
sensor-$(CONFIG_SENSOR_GCORE_GC2053_1L) += gcore_gc2053_1L
sensor-$(CONFIG_SENSOR_GCORE_GC2093) += gcore_gc2093
sensor-$(CONFIG_SENSOR_GCORE_GC2093_SLAVE) += gcore_gc2093_slave
sensor-$(CONFIG_SENSOR_GCORE_GC4653) += gcore_gc4653
sensor-$(CONFIG_SENSOR_GCORE_GC4653_SLAVE) += gcore_gc4653_slave
sensor-$(CONFIG_SENSOR_NEXTCHIP_N5) += nextchip_n5
sensor-$(CONFIG_SENSOR_OV_OS02D10) += ov_os02d10
sensor-$(CONFIG_SENSOR_OV_OS02D10_SLAVE) += ov_os02d10_slave
sensor-$(CONFIG_SENSOR_OV_OS02K10_SLAVE) += ov_os02k10_slave
sensor-$(CONFIG_SENSOR_OV_OS04C10) += ov_os04c10
sensor-$(CONFIG_SENSOR_OV_OS04C10_SLAVE) += ov_os04c10_slave
sensor-$(CONFIG_SENSOR_OV_OS08A20) += ov_os08a20
sensor-$(CONFIG_SENSOR_OV_OS08A20_SLAVE) += ov_os08a20_slave
sensor-$(CONFIG_SENSOR_PICO_384) += pico_384
sensor-$(CONFIG_SENSOR_PICO_640) += pico_640
sensor-$(CONFIG_SENSOR_PIXELPLUS_PR2020) += pixelplus_pr2020
sensor-$(CONFIG_SENSOR_PIXELPLUS_PR2100) += pixelplus_pr2100
sensor-$(CONFIG_SENSOR_SMS_SC035HGS) += sms_sc035hgs
sensor-$(CONFIG_SENSOR_SMS_SC200AI) += sms_sc200ai
sensor-$(CONFIG_SENSOR_SMS_SC401AI) += sms_sc401ai
sensor-$(CONFIG_SENSOR_SMS_SC850SL) += sms_sc850sl
sensor-$(CONFIG_SENSOR_SMS_SC3335) += sms_sc3335
sensor-$(CONFIG_SENSOR_SMS_SC3335_SLAVE) += sms_sc3335_slave
sensor-$(CONFIG_SENSOR_SMS_SC3336) += sms_sc3336
sensor-$(CONFIG_SENSOR_SMS_SC4210) += sms_sc4210
sensor-$(CONFIG_SENSOR_SMS_SC8238) += sms_sc8238
sensor-$(CONFIG_SENSOR_SOI_F23) += soi_f23
sensor-$(CONFIG_SENSOR_SOI_F35) += soi_f35
sensor-$(CONFIG_SENSOR_SOI_F35_SLAVE) += soi_f35_slave
sensor-$(CONFIG_SENSOR_SOI_H65) += soi_h65
sensor-$(CONFIG_SENSOR_SONY_IMX290_2L) += sony_imx290_2L
sensor-$(CONFIG_SENSOR_SONY_IMX307) += sony_imx307
sensor-$(CONFIG_SENSOR_SONY_IMX307_SLAVE) += sony_imx307_slave
sensor-$(CONFIG_SENSOR_SONY_IMX307_2L) += sony_imx307_2L
sensor-$(CONFIG_SENSOR_SONY_IMX307_SUBLVDS) += sony_imx307_sublvds
sensor-$(CONFIG_SENSOR_SONY_IMX327) += sony_imx327
sensor-$(CONFIG_SENSOR_SONY_IMX327_SLAVE) += sony_imx327_slave
sensor-$(CONFIG_SENSOR_SONY_IMX327_2L) += sony_imx327_2L
sensor-$(CONFIG_SENSOR_SONY_IMX327_SUBLVDS) += sony_imx327_sublvds
sensor-$(CONFIG_SENSOR_SONY_IMX334) += sony_imx334
sensor-$(CONFIG_SENSOR_SONY_IMX335) += sony_imx335
sensor-$(CONFIG_SENSOR_SONY_IMX347) += sony_imx347
sensor-$(CONFIG_SENSOR_SONY_IMX385) += sony_imx385
sensor-$(CONFIG_SENSOR_TECHPOINT_TP2850) += techpoint_tp2850
sensor-$(CONFIG_SENSOR_VIVO_MCS369) += vivo_mcs369
sensor-$(CONFIG_SENSOR_VIVO_MCS369Q) += vivo_mcs369q
sensor-$(CONFIG_SENSOR_VIVO_MM308M2) += vivo_mm308m2
else ifeq ($(CHIP_ARCH), $(filter $(CHIP_ARCH), CV180X CV181X CV182X))
sensor-$(CONFIG_SENSOR_BRIGATES_BG0808) += brigates_bg0808
sensor-$(CONFIG_SENSOR_GCORE_GC02M1) += gcore_gc02m1
sensor-$(CONFIG_SENSOR_GCORE_GC1054) += gcore_gc1054
sensor-$(CONFIG_SENSOR_GCORE_GC2053) += gcore_gc2053
sensor-$(CONFIG_SENSOR_GCORE_GC2053_SLAVE) += gcore_gc2053_slave
sensor-$(CONFIG_SENSOR_GCORE_GC2053_1L) += gcore_gc2053_1L
sensor-$(CONFIG_SENSOR_GCORE_GC2093) += gcore_gc2093
sensor-$(CONFIG_SENSOR_GCORE_GC2145) += gcore_gc2145
sensor-$(CONFIG_SENSOR_GCORE_GC4023) += gcore_gc4023
sensor-$(CONFIG_SENSOR_GCORE_GC4653) += gcore_gc4653
sensor-$(CONFIG_SENSOR_NEXTCHIP_N5) += nextchip_n5
sensor-$(CONFIG_SENSOR_NEXTCHIP_N6) += nextchip_n6
sensor-$(CONFIG_SENSOR_OV_OS04A10) += ov_os04a10
sensor-$(CONFIG_SENSOR_OV_OS04C10) += ov_os04c10
sensor-$(CONFIG_SENSOR_OV_OS08A20) += ov_os08a20
sensor-$(CONFIG_SENSOR_OV_OV4689) += ov_ov4689
sensor-$(CONFIG_SENSOR_OV_OV6211) += ov_ov6211
sensor-$(CONFIG_SENSOR_OV_OV7251) += ov_ov7251
sensor-$(CONFIG_SENSOR_PIXELPLUS_PR2020) += pixelplus_pr2020
sensor-$(CONFIG_SENSOR_PIXELPLUS_PR2100) += pixelplus_pr2100
sensor-$(CONFIG_SENSOR_SMS_SC035GS) += sms_sc035gs
sensor-$(CONFIG_SENSOR_SMS_SC035GS_1L) += sms_sc035gs_1L
sensor-$(CONFIG_SENSOR_SMS_SC035HGS) += sms_sc035hgs
sensor-$(CONFIG_SENSOR_SMS_SC200AI) += sms_sc200ai
sensor-$(CONFIG_SENSOR_SMS_SC301IOT) += sms_sc301iot
sensor-$(CONFIG_SENSOR_SMS_SC401AI) += sms_sc401ai
sensor-$(CONFIG_SENSOR_SMS_SC500AI) += sms_sc500ai
sensor-$(CONFIG_SENSOR_SMS_SC501AI_2L) += sms_sc501ai_2L
sensor-$(CONFIG_SENSOR_SMS_SC531AI_2L) += sms_sc531ai_2L
sensor-$(CONFIG_SENSOR_SMS_SC3332) += sms_sc3332
sensor-$(CONFIG_SENSOR_SMS_SC3335) += sms_sc3335
sensor-$(CONFIG_SENSOR_SMS_SC3336) += sms_sc3336
sensor-$(CONFIG_SENSOR_SMS_SC2335) += sms_sc2335
sensor-$(CONFIG_SENSOR_SMS_SC2336) += sms_sc2336
sensor-$(CONFIG_SENSOR_SMS_SC4336) += sms_sc4336
sensor-$(CONFIG_SENSOR_SOI_F23) += soi_f23
sensor-$(CONFIG_SENSOR_SOI_F35) += soi_f35
sensor-$(CONFIG_SENSOR_SOI_F37P) += soi_f37p
sensor-$(CONFIG_SENSOR_SOI_K06) += soi_k06
sensor-$(CONFIG_SENSOR_SOI_Q03) += soi_q03
sensor-$(CONFIG_SENSOR_SONY_IMX307) += sony_imx307
sensor-$(CONFIG_SENSOR_SONY_IMX307_SLAVE) += sony_imx307_slave
sensor-$(CONFIG_SENSOR_SONY_IMX307_2L) += sony_imx307_2L
sensor-$(CONFIG_SENSOR_SONY_IMX327) += sony_imx327
sensor-$(CONFIG_SENSOR_SONY_IMX327_SLAVE) += sony_imx327_slave
sensor-$(CONFIG_SENSOR_SONY_IMX327_2L) += sony_imx327_2L
sensor-$(CONFIG_SENSOR_SONY_IMX327_FPGA) += sony_imx327_fpga
sensor-$(CONFIG_SENSOR_SONY_IMX327_SUBLVDS) += sony_imx327_sublvds
sensor-$(CONFIG_SENSOR_SONY_IMX335) += sony_imx335
else
$(error not supported chip arch cv180x/cv181x/cv182x/cv183x)
endif

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
include ../../../../../$(shell echo $(MW_VER))/component/isp/sensor.mk
define MAKE_SENSOR
pushd $(1) && \
$(MAKE) all && \
popd
endef
.PHONY : prepare clean $(sensor-y)
all: prepare $(sensor-y) all_sensor
prepare:
@echo "#################################################"
@echo "#"
@echo "# Compiling 'component libs' Configs as below..."
@echo "# SENSOR_LIST=$(sensor-y)"
@echo "#"
@echo "#################################################"
brigates_bg0808:
$(call MAKE_SENSOR, ${@})
gcore_gc02m1:
$(call MAKE_SENSOR, ${@})
gcore_gc1054:
$(call MAKE_SENSOR, ${@})
gcore_gc2053:
$(call MAKE_SENSOR, ${@})
gcore_gc2053_slave:
$(call MAKE_SENSOR, ${@})
gcore_gc2053_1L:
$(call MAKE_SENSOR, ${@})
gcore_gc2093:
$(call MAKE_SENSOR, ${@})
gcore_gc2145:
$(call MAKE_SENSOR, ${@})
gcore_gc4023:
$(call MAKE_SENSOR, ${@})
gcore_gc4653:
$(call MAKE_SENSOR, ${@})
nextchip_n5:
$(call MAKE_SENSOR, ${@})
nextchip_n6:
$(call MAKE_SENSOR, ${@})
ov_os04a10:
$(call MAKE_SENSOR, ${@})
ov_os04c10:
$(call MAKE_SENSOR, ${@})
ov_os08a20:
$(call MAKE_SENSOR, ${@})
ov_ov4689:
$(call MAKE_SENSOR, ${@})
ov_ov6211:
$(call MAKE_SENSOR, ${@})
ov_ov7251:
$(call MAKE_SENSOR, ${@})
pixelplus_pr2020:
$(call MAKE_SENSOR, ${@})
pixelplus_pr2100:
$(call MAKE_SENSOR, ${@})
sms_sc035gs:
$(call MAKE_SENSOR, ${@})
sms_sc035gs_1L:
$(call MAKE_SENSOR, ${@})
sms_sc035hgs:
$(call MAKE_SENSOR, ${@})
sms_sc200ai:
$(call MAKE_SENSOR, ${@})
sms_sc301iot:
$(call MAKE_SENSOR, ${@})
sms_sc401ai:
$(call MAKE_SENSOR, ${@})
sms_sc500ai:
$(call MAKE_SENSOR, ${@})
sms_sc501ai_2L:
$(call MAKE_SENSOR, ${@})
sms_sc3332:
$(call MAKE_SENSOR, ${@})
sms_sc531ai_2L:
$(call MAKE_SENSOR, ${@})
sms_sc3335:
$(call MAKE_SENSOR, ${@})
sms_sc3336:
$(call MAKE_SENSOR, ${@})
sms_sc2335:
$(call MAKE_SENSOR, ${@})
sms_sc2336:
$(call MAKE_SENSOR, ${@})
sms_sc4336:
$(call MAKE_SENSOR, ${@})
soi_f23:
$(call MAKE_SENSOR, ${@})
soi_f35:
$(call MAKE_SENSOR, ${@})
soi_f37p:
$(call MAKE_SENSOR, ${@})
soi_q03:
$(call MAKE_SENSOR, ${@})
soi_k06:
$(call MAKE_SENSOR, ${@})
sony_imx307:
$(call MAKE_SENSOR, ${@})
sony_imx307_slave:
$(call MAKE_SENSOR, ${@})
sony_imx307_2L:
$(call MAKE_SENSOR, ${@})
sony_imx327:
$(call MAKE_SENSOR, ${@})
sony_imx327_slave:
$(call MAKE_SENSOR, ${@})
sony_imx327_2L:
$(call MAKE_SENSOR, ${@})
sony_imx327_fpga:
$(call MAKE_SENSOR, ${@})
sony_imx327_sublvds:
$(call MAKE_SENSOR, ${@})
sony_imx335:
$(call MAKE_SENSOR, ${@})
all_sensor:
@$(MAKE) -f Makefile_full || exit 1;
clean:
@for x in `find ./ -maxdepth 2 -mindepth 2 -name "Makefile" `; \
do cd `dirname $$x`; if [ $$? ]; then $(MAKE) clean; cd -; fi; done
@echo "#"
@$(MAKE) clean -f Makefile_full || exit 1;

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
include ../../sensor.mk
SRCS = $(shell find $(sensor-y) -name '*.c')
OBJS = $(SRCS:.c=.o)
TARGET_A = $(MW_LIB)/libsns_full.a
TARGET_SO = $(MW_LIB)/libsns_full.so
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@)
$(TARGET_SO): $(OBJS_PATH)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@)
clean:
@rm -f $(TARGET_A) $(TARGET_SO)

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_bg0808.a
TARGET_SO = $(MW_LIB)/libsns_bg0808.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

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#ifndef __BG0808_CMOS_EX_H_
#define __BG0808_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
enum bg0808_linear_regs_e {
LINEAR_EXP_H_ADDR,//0x0c
LINEAR_EXP_L_ADDR,//0x0d
LINEAR_AGAIN_ADDR,//0x00a2
LINEAR_CLAMP_MODE,//0x73 need change when again changed
LINEAR_DGAIN_H_ADDR,//0x00c0
LINEAR_DGAIN_L_ADDR,//0x00c1
LINEAR_VMAX_H_ADDR,//0x0010
LINEAR_VMAX_L_ADDR,//0x0011
LINEAR_SHADOW_ADDR,//0x001d
LINEAR_REGS_NUM
};
enum bg0808_wdr_regs_e {
WDR_EXP_H_ADDR,
WDR_EXP_L_ADDR,
WDR_SEXP_H_ADDR,//0x22
WDR_SEXP_L_ADDR,//0x23
WDR_AGAIN_ADDR,//0x00a2
WDR_SAGAIN_ADDR,//0x00a4
WDR_CLAMP_MODE,//0x73 need change when again changed
WDR_DGAIN_H_ADDR,
WDR_DGAIN_L_ADDR,
WDR_SDGAIN_H_ADDR,//0x00c2
WDR_SDGAIN_L_ADDR,//0x00c3
WDR_VMAX_H_ADDR,
WDR_VMAX_L_ADDR,
WDR_SHADOW_ADDR,
WDR_REGS_NUM
};
typedef enum _BG0808_MODE_E {
BG0808_MODE_1920X1080P30 = 0,
BG0808_MODE_LINEAR_NUM,
BG0808_MODE_1920X1080P30_WDR = BG0808_MODE_LINEAR_NUM,
BG0808_MODE_NUM
} BG0808_MODE_E;
typedef struct _BG0808_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
CVI_U32 u32IspResTime;
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
char name[64];
} BG0808_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastBG0808[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunBG0808_BusInfo[];
extern CVI_U16 g_au16BG0808_GainMode[];
extern CVI_U16 g_au16BG0808_L2SMode[];
extern CVI_U8 bg0808_i2c_addr;
extern const CVI_U32 bg0808_addr_byte;
extern const CVI_U32 bg0808_data_byte;
extern void bg0808_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern void bg0808_init(VI_PIPE ViPipe);
extern void bg0808_exit(VI_PIPE ViPipe);
extern void bg0808_standby(VI_PIPE ViPipe);
extern void bg0808_restart(VI_PIPE ViPipe);
extern int bg0808_write_register(VI_PIPE ViPipe, int addr, int data);
extern int bg0808_read_register(VI_PIPE ViPipe, int addr);
extern int bg0808_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __BG0808_CMOS_EX_H_ */

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#ifndef __BG0808_CMOS_PARAM_H_
#define __BG0808_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "bg0808_cmos_ex.h"
static const BG0808_MODE_S g_astBG0808_mode[BG0808_MODE_NUM] = {
[BG0808_MODE_1920X1080P30] = {
.name = "1080p30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1920,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.52, /* 1125(0x465) * 30 / 0xFFFF */
.u32HtsDef = 2200,
.u32VtsDef = 1125,
.stExp[0] = {
.u16Min = 1,
.u16Max = 1124,//vts - 1
.u16Def = 400,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 5120,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16324,
.u32Def = 1024,
.u32Step = 1,
},
},
[BG0808_MODE_1920X1080P30_WDR] = {
.name = "1080p30wdr",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
.astImg[1] = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.52, /* 1125(0x465) * 30 / 0xFFFF */
.u32HtsDef = 2200,
.u32VtsDef = 1125,
.stExp[0] = {//sexp
.u16Min = 1,
.u16Max = 1124,//vts - 1
.u16Def = 400,
.u16Step = 1,
},
.stExp[1] = {
.u16Min = 1,
.u16Max = 1124,//vts - 1
.u16Def = 400,
.u16Step = 1,
},
.u32IspResTime = 34, /* ceil((u32Vts * f32MaxFps) / 1000); about 1ms*/
.stAgain[0] = {//sagain
.u32Min = 1024,
.u32Max = 5120,
.u32Def = 1024,
.u32Step = 1,
},
.stAgain[1] = {
.u32Min = 1024,
.u32Max = 5120,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {//sagain
.u32Min = 1024,
.u32Max = 16324,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[1] = {
.u32Min = 1024,
.u32Max = 16324,
.u32Def = 1024,
.u32Step = 1,
},
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
#if 0
.stManual = {0, 0, 0, 0, 0, 0, 0, 0, 1024, 1024, 1024, 1024},
.stAuto = {
{0, 0, 0, 0, 0, 0, 0, 0, /*8*/0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, /*8*/0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, /*8*/0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, /*8*/0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
/*8*/1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024},
{1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
/*8*/1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024},
{1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
/*8*/1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024},
{1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
/*8*/1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024},
},
#endif
#if 1 //use test result as blc offset
.stManual = {28, 28, 28, 28, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1031, 1031, 1031, 1031
#endif
},
.stAuto = {
{28, 28, 28, 28, 28, 28, 28, 28, /*8*/28, 28, 28, 28, 28, 28, 28, 28},
{28, 28, 28, 28, 28, 28, 28, 28, /*8*/28, 28, 28, 28, 28, 28, 28, 28},
{28, 28, 28, 28, 28, 28, 28, 28, /*8*/28, 28, 28, 28, 28, 28, 28, 28},
{28, 28, 28, 28, 28, 28, 28, 28, /*8*/28, 28, 28, 28, 28, 28, 28, 28},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1031, 1031, 1031, 1031, 1031, 1031, 1031, 1031,
/*8*/1031, 1031, 1031, 1031, 1031, 1031, 1031, 1031},
{1031, 1031, 1031, 1031, 1031, 1031, 1031, 1031,
/*8*/1031, 1031, 1031, 1031, 1031, 1031, 1031, 1031},
{1031, 1031, 1031, 1031, 1031, 1031, 1031, 1031,
/*8*/1031, 1031, 1031, 1031, 1031, 1031, 1031, 1031},
{1031, 1031, 1031, 1031, 1031, 1031, 1031, 1031,
/*8*/1031, 1031, 1031, 1031, 1031, 1031, 1031, 1031},
#endif
},
#endif
},
};
struct combo_dev_attr_s bg0808_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {2, 0, 1, -1, -1},
.wdr_mode = CVI_MIPI_WDR_MODE_VC,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_24M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __BG0808_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "bg0808_cmos_ex.h"
#define BG0808_CHIP_ID_HI_ADDR 0x0000
#define BG0808_CHIP_ID_LO_ADDR 0x0001
#define BG0808_CHIP_ID 0x0808
static void bg0808_linear_1080P30_init(VI_PIPE ViPipe);
static void bg0808_wdr_1080P30_2to1_init(VI_PIPE ViPipe);
CVI_U8 bg0808_i2c_addr = 0x32; /* I2C Address of BG0808 */
const CVI_U32 bg0808_addr_byte = 2;
const CVI_U32 bg0808_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int bg0808_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunBG0808_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, bg0808_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int bg0808_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
int bg0808_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (bg0808_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, bg0808_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, bg0808_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (bg0808_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int bg0808_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (bg0808_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (bg0808_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, bg0808_addr_byte + bg0808_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
void bg0808_standby(VI_PIPE ViPipe)
{
(void) ViPipe;
CVI_TRACE_SNS(CVI_DBG_NOTICE, "unsupport standby.\n");
}
void bg0808_restart(VI_PIPE ViPipe)
{
(void) ViPipe;
CVI_TRACE_SNS(CVI_DBG_NOTICE, "unsupport restart.\n");
}
void bg0808_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastBG0808[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
if (g_pastBG0808[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].bUpdate == CVI_TRUE) {
bg0808_write_register(ViPipe,
g_pastBG0808[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastBG0808[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
}
void bg0808_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 val = 0;
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
val |= 0x2;
break;
case ISP_SNS_FLIP:
val |= 0x1;
break;
case ISP_SNS_MIRROR_FLIP:
val |= 0x3;
break;
default:
return;
}
bg0808_write_register(ViPipe, 0x0020, val);
bg0808_write_register(ViPipe, 0x001d, 0x02);
}
int bg0808_probe(VI_PIPE ViPipe)
{
int nVal;
CVI_U16 chip_id;
delay_ms(4);
if (bg0808_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = bg0808_read_register(ViPipe, BG0808_CHIP_ID_HI_ADDR);
if (nVal < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
chip_id = (nVal & 0xFF) << 8;
nVal = bg0808_read_register(ViPipe, BG0808_CHIP_ID_LO_ADDR);
if (nVal < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
chip_id |= (nVal & 0xFF);
if (chip_id != BG0808_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void bg0808_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode;
CVI_U8 u8ImgMode;
enWDRMode = g_pastBG0808[ViPipe]->enWDRMode;
u8ImgMode = g_pastBG0808[ViPipe]->u8ImgMode;
if (g_fd[ViPipe] < 0)
bg0808_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
if (u8ImgMode == BG0808_MODE_1920X1080P30_WDR) {
bg0808_wdr_1080P30_2to1_init(ViPipe);
} else {
}
} else {
bg0808_linear_1080P30_init(ViPipe);
}
g_pastBG0808[ViPipe]->bInit = CVI_TRUE;
}
void bg0808_exit(VI_PIPE ViPipe)
{
bg0808_i2c_exit(ViPipe);
}
/* 1080P30 and 1080P25 */
static void bg0808_linear_1080P30_init(VI_PIPE ViPipe)
{
delay_ms(20);
bg0808_write_register(ViPipe, 0x00b1, 0x55);
bg0808_write_register(ViPipe, 0x00cc, 0x07);
bg0808_write_register(ViPipe, 0x00e4, 0x14);
bg0808_write_register(ViPipe, 0x00fa, 0x7f);
bg0808_write_register(ViPipe, 0x0391, 0x84);
bg0808_write_register(ViPipe, 0x0390, 0x06);
bg0808_write_register(ViPipe, 0x0398, 0x15);
bg0808_write_register(ViPipe, 0x03b2, 0x00);//hs trail, default 0x3c
bg0808_write_register(ViPipe, 0x03b3, 0x78);
bg0808_write_register(ViPipe, 0x03c3, 0x10);
bg0808_write_register(ViPipe, 0x0392, 0x00);
bg0808_write_register(ViPipe, 0x0045, 0x01);
bg0808_write_register(ViPipe, 0x0046, 0x03);
bg0808_write_register(ViPipe, 0x0074, 0x00);
bg0808_write_register(ViPipe, 0x0075, 0x04);
bg0808_write_register(ViPipe, 0x00ae, 0x0a);
bg0808_write_register(ViPipe, 0x00d0, 0x02);
bg0808_write_register(ViPipe, 0x00b2, 0x05);
bg0808_write_register(ViPipe, 0x0120, 0x01);
bg0808_write_register(ViPipe, 0x01a5, 0x07);
bg0808_write_register(ViPipe, 0x007c, 0x04);
bg0808_write_register(ViPipe, 0x00a8, 0x0f);
bg0808_write_register(ViPipe, 0x0030, 0x30);
bg0808_write_register(ViPipe, 0x0032, 0x01);
bg0808_write_register(ViPipe, 0x0033, 0xed);
bg0808_write_register(ViPipe, 0x0034, 0x1e);
bg0808_write_register(ViPipe, 0x002c, 0x00);
bg0808_write_register(ViPipe, 0x002d, 0x2b);
bg0808_write_register(ViPipe, 0x002e, 0x02);
bg0808_write_register(ViPipe, 0x000e, 0x08);
bg0808_write_register(ViPipe, 0x000f, 0x98);
bg0808_write_register(ViPipe, 0x0010, 0x04);
bg0808_write_register(ViPipe, 0x0011, 0x65);
bg0808_write_register(ViPipe, 0x0070, 0x00);
bg0808_write_register(ViPipe, 0x0071, 0x01);
bg0808_write_register(ViPipe, 0x0069, 0x01);
bg0808_write_register(ViPipe, 0x004b, 0x02);
bg0808_write_register(ViPipe, 0x004c, 0x02);
bg0808_write_register(ViPipe, 0x0049, 0x00);
bg0808_write_register(ViPipe, 0x004a, 0x08);
bg0808_write_register(ViPipe, 0x004d, 0x0b);
bg0808_write_register(ViPipe, 0x004e, 0x01);
bg0808_write_register(ViPipe, 0x004f, 0x00);
bg0808_write_register(ViPipe, 0x0050, 0x2a);
bg0808_write_register(ViPipe, 0x0051, 0x00);
bg0808_write_register(ViPipe, 0x0052, 0x4a);
bg0808_write_register(ViPipe, 0x0055, 0x04);
bg0808_write_register(ViPipe, 0x0056, 0x00);
bg0808_write_register(ViPipe, 0x0057, 0x1e);
bg0808_write_register(ViPipe, 0x0084, 0x00);
bg0808_write_register(ViPipe, 0x0085, 0xb9);
bg0808_write_register(ViPipe, 0x0058, 0x02);
bg0808_write_register(ViPipe, 0x005a, 0x00);
bg0808_write_register(ViPipe, 0x005b, 0x4a);
bg0808_write_register(ViPipe, 0x005c, 0x00);
bg0808_write_register(ViPipe, 0x005d, 0x4a);
bg0808_write_register(ViPipe, 0x0086, 0x01);
bg0808_write_register(ViPipe, 0x0087, 0xda);
bg0808_write_register(ViPipe, 0x0088, 0x02);
bg0808_write_register(ViPipe, 0x006f, 0x02);
bg0808_write_register(ViPipe, 0x005e, 0x01);
bg0808_write_register(ViPipe, 0x0043, 0x02);
bg0808_write_register(ViPipe, 0x0044, 0x02);
bg0808_write_register(ViPipe, 0x0039, 0x00);
bg0808_write_register(ViPipe, 0x003a, 0xa0);
bg0808_write_register(ViPipe, 0x0037, 0x00);
bg0808_write_register(ViPipe, 0x0038, 0x80);
bg0808_write_register(ViPipe, 0x006d, 0x0d);
bg0808_write_register(ViPipe, 0x0064, 0x15);
bg0808_write_register(ViPipe, 0x00a1, 0x0c);
bg0808_write_register(ViPipe, 0x00aa, 0x0c);
bg0808_write_register(ViPipe, 0x00bc, 0x02);
bg0808_write_register(ViPipe, 0x0046, 0x00);
//blc
bg0808_write_register(ViPipe, 0x0130, 0x00);// blc, default 0x18
bg0808_write_register(ViPipe, 0x0131, 0x18);
bg0808_write_register(ViPipe, 0x001d, 0x01);
bg0808_default_reg_init(ViPipe);
delay_ms(20);
printf("ViPipe:%d,===BG0808 1080P 30fps 10bit LINE Init OK!===\n", ViPipe);
}
static void bg0808_wdr_1080P30_2to1_init(VI_PIPE ViPipe)
{
delay_ms(20);
bg0808_write_register(ViPipe, 0x00b1, 0x55);
bg0808_write_register(ViPipe, 0x00cc, 0x07);
bg0808_write_register(ViPipe, 0x00e4, 0x14);
bg0808_write_register(ViPipe, 0x00fa, 0x7f);
bg0808_write_register(ViPipe, 0x0391, 0x84);
bg0808_write_register(ViPipe, 0x0390, 0x06);
bg0808_write_register(ViPipe, 0x03c3, 0x10);
bg0808_write_register(ViPipe, 0x0392, 0x00);
bg0808_write_register(ViPipe, 0x03b2, 0x00);//hs trail, default 0x3c
bg0808_write_register(ViPipe, 0x03b3, 0x78);
bg0808_write_register(ViPipe, 0x0045, 0x01);
bg0808_write_register(ViPipe, 0x0046, 0x03);
bg0808_write_register(ViPipe, 0x0074, 0x00);
bg0808_write_register(ViPipe, 0x0075, 0x04);
bg0808_write_register(ViPipe, 0x00ae, 0x0a);
bg0808_write_register(ViPipe, 0x00d0, 0x02);
bg0808_write_register(ViPipe, 0x00b2, 0x05);
bg0808_write_register(ViPipe, 0x0120, 0x01);
bg0808_write_register(ViPipe, 0x01a5, 0x07);
bg0808_write_register(ViPipe, 0x007c, 0x04);
bg0808_write_register(ViPipe, 0x00a8, 0x0f);
bg0808_write_register(ViPipe, 0x0032, 0x00);
bg0808_write_register(ViPipe, 0x0033, 0x35);
bg0808_write_register(ViPipe, 0x0034, 0x00);
bg0808_write_register(ViPipe, 0x002c, 0x00);
bg0808_write_register(ViPipe, 0x002d, 0x13);
bg0808_write_register(ViPipe, 0x002e, 0x00);
bg0808_write_register(ViPipe, 0x000e, 0x11);
bg0808_write_register(ViPipe, 0x000f, 0x30);
bg0808_write_register(ViPipe, 0x0010, 0x04);
bg0808_write_register(ViPipe, 0x0011, 0x65);
bg0808_write_register(ViPipe, 0x0070, 0x00);
bg0808_write_register(ViPipe, 0x0071, 0x01);
bg0808_write_register(ViPipe, 0x0069, 0x01);
bg0808_write_register(ViPipe, 0x004b, 0x04);
bg0808_write_register(ViPipe, 0x004c, 0x04);
bg0808_write_register(ViPipe, 0x0049, 0x00);
bg0808_write_register(ViPipe, 0x004a, 0x0f);
bg0808_write_register(ViPipe, 0x004d, 0x14);
bg0808_write_register(ViPipe, 0x004e, 0x01);
bg0808_write_register(ViPipe, 0x004f, 0x00);
bg0808_write_register(ViPipe, 0x0050, 0x53);
bg0808_write_register(ViPipe, 0x0051, 0x00);
bg0808_write_register(ViPipe, 0x0052, 0x93);
bg0808_write_register(ViPipe, 0x0055, 0x08);
bg0808_write_register(ViPipe, 0x0056, 0x00);
bg0808_write_register(ViPipe, 0x0057, 0x3b);
bg0808_write_register(ViPipe, 0x0084, 0x01);
bg0808_write_register(ViPipe, 0x0085, 0x72);
bg0808_write_register(ViPipe, 0x0058, 0x04);
bg0808_write_register(ViPipe, 0x005a, 0x00);
bg0808_write_register(ViPipe, 0x005b, 0x93);
bg0808_write_register(ViPipe, 0x005c, 0x00);
bg0808_write_register(ViPipe, 0x005d, 0x93);
bg0808_write_register(ViPipe, 0x0086, 0x03);
bg0808_write_register(ViPipe, 0x0087, 0x8e);
bg0808_write_register(ViPipe, 0x0088, 0x04);
bg0808_write_register(ViPipe, 0x006f, 0x04);
bg0808_write_register(ViPipe, 0x005e, 0x01);
bg0808_write_register(ViPipe, 0x0043, 0x04);
bg0808_write_register(ViPipe, 0x0044, 0x04);
bg0808_write_register(ViPipe, 0x0039, 0x01);
bg0808_write_register(ViPipe, 0x003a, 0x40);
bg0808_write_register(ViPipe, 0x0037, 0x01);
bg0808_write_register(ViPipe, 0x0038, 0x00);
bg0808_write_register(ViPipe, 0x006d, 0x0e);
bg0808_write_register(ViPipe, 0x0064, 0x16);
bg0808_write_register(ViPipe, 0x0021, 0x01);
bg0808_write_register(ViPipe, 0x0041, 0x01);
bg0808_write_register(ViPipe, 0x0042, 0x40);
bg0808_write_register(ViPipe, 0x003f, 0x01);
bg0808_write_register(ViPipe, 0x0040, 0x00);
bg0808_write_register(ViPipe, 0x0098, 0x00);
bg0808_write_register(ViPipe, 0x0099, 0x88);
bg0808_write_register(ViPipe, 0x009a, 0x01);
bg0808_write_register(ViPipe, 0x009b, 0x88);
bg0808_write_register(ViPipe, 0x009c, 0x01);
bg0808_write_register(ViPipe, 0x009d, 0x72);
bg0808_write_register(ViPipe, 0x009e, 0x03);
bg0808_write_register(ViPipe, 0x009f, 0x8e);
bg0808_write_register(ViPipe, 0x00a1, 0x0c);
bg0808_write_register(ViPipe, 0x00a3, 0x0c);
bg0808_write_register(ViPipe, 0x00aa, 0x0c);
bg0808_write_register(ViPipe, 0x00ab, 0x0c);
bg0808_write_register(ViPipe, 0x00bc, 0x02);
bg0808_write_register(ViPipe, 0x0046, 0x00);
//blc
bg0808_write_register(ViPipe, 0x0130, 0x00);// blc, default 0x18
bg0808_write_register(ViPipe, 0x0131, 0x18);
bg0808_write_register(ViPipe, 0x001d, 0x01);
bg0808_default_reg_init(ViPipe);
delay_ms(20);
printf("ViPipe:%d,===BG0808 1080P 30fps 10bit WDR2TO1 Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/gcore_gc02m1/Makefile Normal file
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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc02m1.a
TARGET_SO = $(MW_LIB)/libsns_gc02m1.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

874
middleware/v2/component/isp/sensor/cv180x/gcore_gc02m1/gc02m1_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "gc02m1_cmos_ex.h"
#include "gc02m1_cmos_param.h"
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#include "cvi_type.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#include <linux/cvi_type.h>
#endif
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define GC02M1_ID 0x02e0
#define GC02M1_I2C_ADDR_1 0x37
#define GC02M1_I2C_ADDR_2 0x10
#define GC02M1_I2C_ADDR_IS_VALID(addr) ((addr) == GC02M1_I2C_ADDR_1 || (addr) == GC02M1_I2C_ADDR_2)
/****************************************************************************
* global variables *
***************************************************************************/
ISP_SNS_STATE_S *g_pastGc02m1[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define GC02M1_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc02m1[dev])
#define GC02M1_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc02m1[dev] = pstCtx)
#define GC02M1_SENSOR_RESET_CTX(dev) (g_pastGc02m1[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunGc02m1_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 3},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc02m1_MirrorFip[VI_MAX_PIPE_NUM] = {ISP_SNS_NORMAL};
CVI_U16 g_au16Gc02m1_GainMode[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
***************************************************************************/
static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = {
[0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE
};
static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Gc02m1 Lines Range*****/
#define GC02M1_FULL_LINES_MAX (0x3fff)
/*****Gc02m1 Register Address*****/
#define GC02M1_PAGE_0_ADDR 0xfe
#define GC02M1_EXP_H_ADDR 0x03 //bit[13:8]
#define GC02M1_EXP_L_ADDR 0x04
#define GC02M1_AGAIN_ADDR 0xb6 //bit[4:0]
#define GC02M1_VTS_H_ADDR 0x41 //bit[13:8]
#define GC02M1_VTS_L_ADDR 0x42
#define GC02M1_MIRROR_FLIP_ADDR 0x17
#define GC02M1_RES_IS_1200P(w, h) ((w) <= 1600 && (h) <= 1200)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = GC02M1_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = g_astGc02m1_mode[GC02M1_MODE_1600X1200P30].f32MaxFps;
pstAeSnsDft->f32MinFps = g_astGc02m1_mode[GC02M1_MODE_1600X1200P30].f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = 60880;
pstAeSnsDft->u32MinAgain = 1024;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = 1024;
pstAeSnsDft->u32MinDgain = 1024;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
g_au32InitExposure[ViPipe] : g_astGc02m1_mode[GC02M1_MODE_1600X1200P30].stExp[0].u16Def;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstAeSnsDft->u32MinIntTime = g_astGc02m1_mode[GC02M1_MODE_1600X1200P30].stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_astGc02m1_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_astGc02m1_mode[pstSnsState->u8ImgMode].f32MaxFps;
f32MinFps = g_astGc02m1_mode[pstSnsState->u8ImgMode].f32MinFps;
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > GC02M1_FULL_LINES_MAX) ? GC02M1_FULL_LINES_MAX : u32VMAX;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_VTS_H].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_L].u32Data = (u32VMAX & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_H].u32Data = ((u32IntTime[0] >> 8) & 0x3F);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_L].u32Data = (u32IntTime[0] & 0xFF);
return CVI_SUCCESS;
}
static CVI_U32 regValTable[] = {
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
};
static CVI_U32 gain_table[] = {
16 * 64,
16 * 96,
16 * 127,
16 * 157,
16 * 197,
16 * 226,
16 * 259,
16 * 287,
16 * 318,
16 * 356,
16 * 391,
16 * 419,
16 * 450,
16 * 480,
16 * 513,
16 * 646,
};
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
int i;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
int total = ARRAY_SIZE(gain_table);
if (*pu32AgainLin >= gain_table[total - 1]) {
*pu32AgainDb = total - 1;
*pu32AgainLin = gain_table[total - 1];
return CVI_SUCCESS;
}
for (i = 0; i < total; i++) {
if (*pu32AgainLin < gain_table[i]) {
*pu32AgainDb = i - 1;
break;
}
}
*pu32AgainLin = gain_table[i - 1];
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
UNUSED(ViPipe);
*pu32DgainLin = 1024;
*pu32DgainDb = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32Again;
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* only surpport linear mode */
u32Again = pu32Again[0];
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN].u32Data = regValTable[u32Again];
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
{
UNUSED(ViPipe);
UNUSED(u16ManRatioEnable);
UNUSED(au32Ratio);
UNUSED(au32IntTimeMax);
UNUSED(au32IntTimeMin);
UNUSED(pu32LFMaxIntTime);
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode\n");
return CVI_SUCCESS;
}
/* Only used in LINE_WDR mode */
static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr)
{
CMOS_CHECK_POINTER(pstAeFSWDRAttr);
genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode;
gu32MaxTimeGetCnt[ViPipe] = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
UNUSED(ViPipe);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const GC02M1_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astGc02m1_mode[pstSnsState->u8ImgMode];
if (pstSnsState->enWDRMode != WDR_MODE_NONE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
} else {
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
UNUSED(ViPipe);
UNUSED(u8Mode);
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunGc02m1_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = gc02m1_i2c_addr;
pstI2c_data[i].u32AddrByteNum = gc02m1_addr_byte;
pstI2c_data[i].u32DataByteNum = gc02m1_data_byte;
}
pstI2c_data[LINEAR_PAGE_0].u32RegAddr = GC02M1_PAGE_0_ADDR;
pstI2c_data[LINEAR_PAGE_0].u32Data = 0;
pstI2c_data[LINEAR_EXP_H].u32RegAddr = GC02M1_EXP_H_ADDR;
pstI2c_data[LINEAR_EXP_L].u32RegAddr = GC02M1_EXP_L_ADDR;
pstI2c_data[LINEAR_AGAIN].u32RegAddr = GC02M1_AGAIN_ADDR;
pstI2c_data[LINEAR_VTS_H].u32RegAddr = GC02M1_VTS_H_ADDR;
pstI2c_data[LINEAR_VTS_L].u32RegAddr = GC02M1_VTS_L_ADDR;
pstI2c_data[LINEAR_MIRROR_FLIP].u32RegAddr = GC02M1_MIRROR_FLIP_ADDR;
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0, shutterUpdate = 0, vtsUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
if (i == LINEAR_AGAIN)
gainsUpdate = 1;
if (i <= LINEAR_EXP_L && i >= LINEAR_EXP_H)
shutterUpdate = 1;
if ((i >= LINEAR_VTS_H) && (i <= LINEAR_VTS_L))
vtsUpdate = 1;
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN].bUpdate = CVI_TRUE;
}
if (shutterUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_L].bUpdate = CVI_TRUE;
}
if (vtsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_L].bUpdate = CVI_TRUE;
}
/* check update isp crop or not */
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 30) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (GC02M1_RES_IS_1200P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = GC02M1_MODE_1600X1200P30;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps);
return CVI_FAILURE;
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U8 value;
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeGc02m1_MirrorFip[ViPipe] != eSnsMirrorFlip) {
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
value = 0;
break;
case ISP_SNS_MIRROR:
value = 0x01;
break;
case ISP_SNS_FLIP:
value = 0x02;
break;
case ISP_SNS_MIRROR_FLIP:
value = 0x03;
break;
default:
return;
}
pstSnsRegsInfo->astI2cData[LINEAR_MIRROR_FLIP].u32Data = value;
g_aeGc02m1_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = GC02M1_MODE_1600X1200P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astGc02m1_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[0] = g_astGc02m1_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[1] = g_astGc02m1_mode[pstSnsState->u8ImgMode].u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC02M1_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &gc02m1_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_astGc02m1_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astGc02m1_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc02m1_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = gc02m1_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = gc02m1_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (GC02M1_I2C_ADDR_IS_VALID(s32I2cAddr))
gc02m1_i2c_addr = s32I2cAddr;
}
static CVI_S32 gc02m1_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunGc02m1_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC02M1_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
GC02M1_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC02M1_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
GC02M1_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = GC02M1_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC02M1_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, GC02M1_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, GC02M1_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Gc02m1_GainMode[ViPipe] = pstInitAttr->enGainMode;
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return gc02m1_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsGc02m1_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = gc02m1_standby,
.pfnRestart = gc02m1_restart,
.pfnWriteReg = gc02m1_write_register,
.pfnReadReg = gc02m1_read_register,
.pfnSetBusInfo = gc02m1_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = sensor_probe,
};

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#ifndef __GC02M1_CMOS_EX_H_
#define __GC02M1_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#ifndef UNUSED
#define UNUSED(x) ((void)(x))
#endif
enum gc02m1_linear_regs_e {
LINEAR_PAGE_0,
LINEAR_EXP_H,
LINEAR_EXP_L,
LINEAR_AGAIN,
LINEAR_VTS_H,
LINEAR_VTS_L,
LINEAR_MIRROR_FLIP,
LINEAR_REGS_NUM
};
typedef enum _GC02M1_MODE_E {
GC02M1_MODE_1600X1200P30 = 0,
GC02M1_MODE_LINEAR_NUM,
GC02M1_MODE_NUM
} GC02M1_MODE_E;
typedef struct _GC02M1_STATE_S {
CVI_U32 u32Sexp_MAX;
} GC02M1_STATE_S;
typedef struct _GC02M1_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
char name[64];
} GC02M1_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc02m1[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc02m1_BusInfo[];
extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc02m1_MirrorFip[VI_MAX_PIPE_NUM];
extern CVI_U8 gc02m1_i2c_addr;
extern const CVI_U32 gc02m1_addr_byte;
extern const CVI_U32 gc02m1_data_byte;
extern void gc02m1_init(VI_PIPE ViPipe);
extern void gc02m1_exit(VI_PIPE ViPipe);
extern void gc02m1_standby(VI_PIPE ViPipe);
extern void gc02m1_restart(VI_PIPE ViPipe);
extern int gc02m1_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc02m1_read_register(VI_PIPE ViPipe, int addr);
extern int gc02m1_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC02M1_CMOS_EX_H_ */

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#ifndef __GC02M1_CMOS_PARAM_H_
#define __GC02M1_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc02m1_cmos_ex.h"
static const GC02M1_MODE_S g_astGc02m1_mode[GC02M1_MODE_NUM] = {
[GC02M1_MODE_1600X1200P30] = {
.name = "1600X1200P30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1600,
.u32Height = 1200,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1600,
.u32Height = 1200,
},
.stMaxSize = {
.u32Width = 1600,
.u32Height = 1200,
},
},
.f32MaxFps = 30,
.f32MinFps = 2.32, /* 1268 * 30 / 0x3FFF */
.u32HtsDef = 1774,
.u32VtsDef = 1268,
.stExp[0] = {
.u16Min = 1,
.u16Max = 1268 - 8,
.u16Def = 100,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 16 * 646,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 1024,
.u32Def = 1024,
.u32Step = 1,
},
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {256, 256, 256, 256, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1092, 1092, 1092, 1092
#endif
},
.stAuto = {
{256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256 },
{256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256 },
{256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256 },
{256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256, 256 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
1092, 1092},
#endif
},
},
};
struct combo_dev_attr_s gc02m1_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {0, 1, -1, -1, -1},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC02M1_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc02m1_cmos_ex.h"
#define GC02M1_CHIP_ID_ADDR_H 0xf0
#define GC02M1_CHIP_ID_ADDR_L 0xf1
#define GC02M1_CHIP_ID 0x02e0
#define GC02M1_MIRROR_NORMAL 1
#define GC02M1_MIRROR_H 0
#define GC02M1_MIRROR_V 0
#define GC02M1_MIRROR_HV 0
#if GC02M1_MIRROR_NORMAL
#define GC02M1_MIRROR 0x80
#elif GC02M1_MIRROR_H
#define GC02M1_MIRROR 0x81
#elif GC02M1_MIRROR_V
#define GC02M1_MIRROR 0x82
#elif GC02M1_MIRROR_HV
#define GC02M1_MIRROR 0x83
#else
#define GC02M1_MIRROR 0x80
#endif
static void gc02m1_linear_1200p30_init(VI_PIPE ViPipe);
CVI_U8 gc02m1_i2c_addr = 0x37;
const CVI_U32 gc02m1_addr_byte = 1;
const CVI_U32 gc02m1_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc02m1_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc02m1_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc02m1_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc02m1_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc02m1_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (gc02m1_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, gc02m1_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, gc02m1_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (gc02m1_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_INFO, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int gc02m1_write_register(VI_PIPE ViPipe, int addr, int data)
{
int idx = 0;
int ret;
char buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc02m1_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
if (gc02m1_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc02m1_addr_byte + gc02m1_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
ret = read(g_fd[ViPipe], buf, gc02m1_addr_byte + gc02m1_data_byte);
syslog(LOG_INFO, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void gc02m1_standby(VI_PIPE ViPipe)
{
int nVal;
gc02m1_write_register(ViPipe, 0xfe, 0x00);
nVal = gc02m1_read_register(ViPipe, 0x3e);
nVal &= ~(0x1 << 7);
nVal &= ~(0x1 << 4);
gc02m1_write_register(ViPipe, 0x3e, nVal);
gc02m1_write_register(ViPipe, 0xfc, 0x01);
nVal = gc02m1_read_register(ViPipe, 0xf9);
nVal |= (0x1 << 0);
gc02m1_write_register(ViPipe, 0xf9, nVal);
printf("gc02m1 standby\n");
}
void gc02m1_restart(VI_PIPE ViPipe)
{
int nVal;
nVal = gc02m1_read_register(ViPipe, 0xf9);
nVal &= ~(0x1 << 0);
gc02m1_write_register(ViPipe, 0xf9, nVal);
usleep(1);
gc02m1_write_register(ViPipe, 0xfc, 0x8e);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
nVal = gc02m1_read_register(ViPipe, 0x3e);
nVal |= (0x1 << 7);
nVal |= (0x1 << 4);
gc02m1_write_register(ViPipe, 0x3e, nVal);
printf("gc02m1 restart\n");
}
void gc02m1_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastGc02m1[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
gc02m1_write_register(ViPipe,
g_pastGc02m1[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastGc02m1[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
int gc02m1_probe(VI_PIPE ViPipe)
{
int nVal;
int nVal2;
usleep(50);
if (gc02m1_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = gc02m1_read_register(ViPipe, GC02M1_CHIP_ID_ADDR_H);
nVal2 = gc02m1_read_register(ViPipe, GC02M1_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC02M1_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void gc02m1_init(VI_PIPE ViPipe)
{
gc02m1_i2c_init(ViPipe);
gc02m1_linear_1200p30_init(ViPipe);
g_pastGc02m1[ViPipe]->bInit = CVI_TRUE;
}
void gc02m1_exit(VI_PIPE ViPipe)
{
gc02m1_i2c_exit(ViPipe);
}
static void gc02m1_linear_1200p30_init(VI_PIPE ViPipe)
{
usleep(10 * 1000);
/*system*/
gc02m1_write_register(ViPipe, 0xfc, 0x01);
gc02m1_write_register(ViPipe, 0xf4, 0x41);
gc02m1_write_register(ViPipe, 0xf5, 0xc0);
gc02m1_write_register(ViPipe, 0xf6, 0x44);
gc02m1_write_register(ViPipe, 0xf8, 0x32);
gc02m1_write_register(ViPipe, 0xf9, 0x82);
gc02m1_write_register(ViPipe, 0xfa, 0x00);
gc02m1_write_register(ViPipe, 0xfd, 0x80);
gc02m1_write_register(ViPipe, 0xfc, 0x81);
gc02m1_write_register(ViPipe, 0xfe, 0x03);
gc02m1_write_register(ViPipe, 0x01, 0x0b);
gc02m1_write_register(ViPipe, 0xf7, 0x01);
gc02m1_write_register(ViPipe, 0xfc, 0x80);
gc02m1_write_register(ViPipe, 0xfc, 0x80);
gc02m1_write_register(ViPipe, 0xfc, 0x80);
gc02m1_write_register(ViPipe, 0xfc, 0x8e);
/*CISCTL*/
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0x87, 0x09);
gc02m1_write_register(ViPipe, 0xee, 0x72);
gc02m1_write_register(ViPipe, 0xfe, 0x01);
gc02m1_write_register(ViPipe, 0x8c, 0x90);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0x90, 0x00);
gc02m1_write_register(ViPipe, 0x03, 0x04);
gc02m1_write_register(ViPipe, 0x04, 0x7d);
gc02m1_write_register(ViPipe, 0x41, 0x04);
gc02m1_write_register(ViPipe, 0x42, 0xf4);
gc02m1_write_register(ViPipe, 0x05, 0x04);
gc02m1_write_register(ViPipe, 0x06, 0x48);
gc02m1_write_register(ViPipe, 0x07, 0x00);
gc02m1_write_register(ViPipe, 0x08, 0x18);
gc02m1_write_register(ViPipe, 0x9d, 0x18);
gc02m1_write_register(ViPipe, 0x09, 0x00);
gc02m1_write_register(ViPipe, 0x0a, 0x02);
gc02m1_write_register(ViPipe, 0x0d, 0x04);
gc02m1_write_register(ViPipe, 0x0e, 0xbc);
gc02m1_write_register(ViPipe, 0x17, GC02M1_MIRROR);
gc02m1_write_register(ViPipe, 0x19, 0x04);
gc02m1_write_register(ViPipe, 0x24, 0x00);
gc02m1_write_register(ViPipe, 0x56, 0x20);
gc02m1_write_register(ViPipe, 0x5b, 0x00);
gc02m1_write_register(ViPipe, 0x5e, 0x01);
/*analog Register width*/
gc02m1_write_register(ViPipe, 0x21, 0x3c);
gc02m1_write_register(ViPipe, 0x44, 0x20);
gc02m1_write_register(ViPipe, 0xcc, 0x01);
/*analog mode*/
gc02m1_write_register(ViPipe, 0x1a, 0x04);
gc02m1_write_register(ViPipe, 0x1f, 0x11);
gc02m1_write_register(ViPipe, 0x27, 0x30);
gc02m1_write_register(ViPipe, 0x2b, 0x00);
gc02m1_write_register(ViPipe, 0x33, 0x00);
gc02m1_write_register(ViPipe, 0x53, 0x90);
gc02m1_write_register(ViPipe, 0xe6, 0x50);
/*analog voltage*/
gc02m1_write_register(ViPipe, 0x39, 0x07);
gc02m1_write_register(ViPipe, 0x43, 0x04);
gc02m1_write_register(ViPipe, 0x46, 0x2a);
gc02m1_write_register(ViPipe, 0x7c, 0xa0);
gc02m1_write_register(ViPipe, 0xd0, 0xbe);
gc02m1_write_register(ViPipe, 0xd1, 0x60);
gc02m1_write_register(ViPipe, 0xd2, 0x40);
gc02m1_write_register(ViPipe, 0xd3, 0xf3);
gc02m1_write_register(ViPipe, 0xde, 0x1d);
/*analog current*/
gc02m1_write_register(ViPipe, 0xcd, 0x05);
gc02m1_write_register(ViPipe, 0xce, 0x6f);
/*CISCTL RESET*/
gc02m1_write_register(ViPipe, 0xfc, 0x88);
gc02m1_write_register(ViPipe, 0xfe, 0x10);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0xfc, 0x8e);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0xfc, 0x88);
gc02m1_write_register(ViPipe, 0xfe, 0x10);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0xfc, 0x8e);
gc02m1_write_register(ViPipe, 0xfe, 0x04);
gc02m1_write_register(ViPipe, 0xe0, 0x01);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
/*ISP*/
gc02m1_write_register(ViPipe, 0xfe, 0x01);
gc02m1_write_register(ViPipe, 0x53, 0x44);
gc02m1_write_register(ViPipe, 0x87, 0x53);
gc02m1_write_register(ViPipe, 0x89, 0x03);
/*Gain*/
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0xb0, 0x74);
gc02m1_write_register(ViPipe, 0xb1, 0x04);
gc02m1_write_register(ViPipe, 0xb2, 0x00);
gc02m1_write_register(ViPipe, 0xb6, 0x00);
gc02m1_write_register(ViPipe, 0xfe, 0x04);
gc02m1_write_register(ViPipe, 0xd8, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x40);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x60);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0xc0);
gc02m1_write_register(ViPipe, 0xc0, 0x2a);
gc02m1_write_register(ViPipe, 0xc0, 0x80);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x40);
gc02m1_write_register(ViPipe, 0xc0, 0xa0);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x90);
gc02m1_write_register(ViPipe, 0xc0, 0x19);
gc02m1_write_register(ViPipe, 0xc0, 0xc0);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0xD0);
gc02m1_write_register(ViPipe, 0xc0, 0x2F);
gc02m1_write_register(ViPipe, 0xc0, 0xe0);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x90);
gc02m1_write_register(ViPipe, 0xc0, 0x39);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x01);
gc02m1_write_register(ViPipe, 0xc0, 0x20);
gc02m1_write_register(ViPipe, 0xc0, 0x04);
gc02m1_write_register(ViPipe, 0xc0, 0x20);
gc02m1_write_register(ViPipe, 0xc0, 0x01);
gc02m1_write_register(ViPipe, 0xc0, 0xe0);
gc02m1_write_register(ViPipe, 0xc0, 0x0f);
gc02m1_write_register(ViPipe, 0xc0, 0x40);
gc02m1_write_register(ViPipe, 0xc0, 0x01);
gc02m1_write_register(ViPipe, 0xc0, 0xe0);
gc02m1_write_register(ViPipe, 0xc0, 0x1a);
gc02m1_write_register(ViPipe, 0xc0, 0x60);
gc02m1_write_register(ViPipe, 0xc0, 0x01);
gc02m1_write_register(ViPipe, 0xc0, 0x20);
gc02m1_write_register(ViPipe, 0xc0, 0x25);
gc02m1_write_register(ViPipe, 0xc0, 0x80);
gc02m1_write_register(ViPipe, 0xc0, 0x01);
gc02m1_write_register(ViPipe, 0xc0, 0xa0);
gc02m1_write_register(ViPipe, 0xc0, 0x2c);
gc02m1_write_register(ViPipe, 0xc0, 0xa0);
gc02m1_write_register(ViPipe, 0xc0, 0x01);
gc02m1_write_register(ViPipe, 0xc0, 0xe0);
gc02m1_write_register(ViPipe, 0xc0, 0x32);
gc02m1_write_register(ViPipe, 0xc0, 0xc0);
gc02m1_write_register(ViPipe, 0xc0, 0x01);
gc02m1_write_register(ViPipe, 0xc0, 0x20);
gc02m1_write_register(ViPipe, 0xc0, 0x38);
gc02m1_write_register(ViPipe, 0xc0, 0xe0);
gc02m1_write_register(ViPipe, 0xc0, 0x01);
gc02m1_write_register(ViPipe, 0xc0, 0x60);
gc02m1_write_register(ViPipe, 0xc0, 0x3c);
gc02m1_write_register(ViPipe, 0xc0, 0x00);
gc02m1_write_register(ViPipe, 0xc0, 0x02);
gc02m1_write_register(ViPipe, 0xc0, 0xa0);
gc02m1_write_register(ViPipe, 0xc0, 0x40);
gc02m1_write_register(ViPipe, 0xc0, 0x80);
gc02m1_write_register(ViPipe, 0xc0, 0x02);
gc02m1_write_register(ViPipe, 0xc0, 0x18);
gc02m1_write_register(ViPipe, 0xc0, 0x5c);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0x9f, 0x10);
/*BLK*/
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0x26, 0x20);
gc02m1_write_register(ViPipe, 0xfe, 0x01);
gc02m1_write_register(ViPipe, 0x40, 0x22);
gc02m1_write_register(ViPipe, 0x46, 0x7f);
gc02m1_write_register(ViPipe, 0x49, 0x0f);
gc02m1_write_register(ViPipe, 0x4a, 0xf0);
gc02m1_write_register(ViPipe, 0xfe, 0x04);
gc02m1_write_register(ViPipe, 0x14, 0x80);
gc02m1_write_register(ViPipe, 0x15, 0x80);
gc02m1_write_register(ViPipe, 0x16, 0x80);
gc02m1_write_register(ViPipe, 0x17, 0x80);
/*ant _blooming*/
gc02m1_write_register(ViPipe, 0xfe, 0x01);
gc02m1_write_register(ViPipe, 0x41, 0x20);
gc02m1_write_register(ViPipe, 0x4c, 0x00);
gc02m1_write_register(ViPipe, 0x4d, 0x0c);
gc02m1_write_register(ViPipe, 0x44, 0x08);
gc02m1_write_register(ViPipe, 0x48, 0x03);
/*Window 1600X1200*/
gc02m1_write_register(ViPipe, 0xfe, 0x01);
gc02m1_write_register(ViPipe, 0x90, 0x01);
gc02m1_write_register(ViPipe, 0x91, 0x00);
gc02m1_write_register(ViPipe, 0x92, 0x06);
gc02m1_write_register(ViPipe, 0x93, 0x00);
gc02m1_write_register(ViPipe, 0x94, 0x06);
gc02m1_write_register(ViPipe, 0x95, 0x04);
gc02m1_write_register(ViPipe, 0x96, 0xb0);
gc02m1_write_register(ViPipe, 0x97, 0x06);
gc02m1_write_register(ViPipe, 0x98, 0x40);
/*mipi*/
gc02m1_write_register(ViPipe, 0xfe, 0x03);
gc02m1_write_register(ViPipe, 0x01, 0x23);
gc02m1_write_register(ViPipe, 0x03, 0xce);
gc02m1_write_register(ViPipe, 0x04, 0x48);
gc02m1_write_register(ViPipe, 0x15, 0x00);
gc02m1_write_register(ViPipe, 0x21, 0x10);
gc02m1_write_register(ViPipe, 0x22, 0x05);
gc02m1_write_register(ViPipe, 0x23, 0x20);
gc02m1_write_register(ViPipe, 0x25, 0x20);
gc02m1_write_register(ViPipe, 0x26, 0x08);
gc02m1_write_register(ViPipe, 0x29, 0x06);
gc02m1_write_register(ViPipe, 0x2a, 0x0a);
gc02m1_write_register(ViPipe, 0x2b, 0x08);
/*out*/
gc02m1_write_register(ViPipe, 0xfe, 0x01);
gc02m1_write_register(ViPipe, 0x8c, 0x10);
gc02m1_write_register(ViPipe, 0xfe, 0x00);
gc02m1_write_register(ViPipe, 0x3e, 0x90);
gc02m1_default_reg_init(ViPipe);
usleep(10 * 1000);
printf("ViPipe:%d,===GC02M1 1200P 30fps 10bit LINEAR Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/gcore_gc1054/Makefile Normal file
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@ -0,0 +1,36 @@
SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc1054.a
TARGET_SO = $(MW_LIB)/libsns_gc1054.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

900
middleware/v2/component/isp/sensor/cv180x/gcore_gc1054/gc1054_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "gc1054_cmos_ex.h"
#include "gc1054_cmos_param.h"
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define GC1054_ID 1054
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_STATE_S *g_pastGc1054[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define GC1054_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc1054[dev])
#define GC1054_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc1054[dev] = pstCtx)
#define GC1054_SENSOR_RESET_CTX(dev) (g_pastGc1054[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunGc1054_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
GC1054_STATE_S g_astGc1054_State[VI_MAX_PIPE_NUM] = { {0} };
ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc1054_MirrorFip[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc1054_GainMode[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc1054_L2SMode[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
****************************************************************************/
static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = {
[0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE
};
static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Gc1054 Lines Range*****/
#define GC1054_FULL_LINES_MAX (8931) // 0x1FFF(Max VB) + 724 + 16
/*****Gc1054 Register Address*****/
#define GC1054_EXP_PAGE_ADDR 0xfe
#define GC1054_EXP_H_ADDR 0x03
#define GC1054_EXP_L_ADDR 0x04
#define GC1054_AGAIN_PAGE_ADDR 0xfe
#define GC1054_AGAIN_ADDR 0xb6
#define GC1054_VB_PAGE_ADDR 0xfe
#define GC1054_VB_H_ADDR 0x07
#define GC1054_VB_L_ADDR 0x08
#define GC1054_FLIP_MIRROR_PAGE_ADDR 0xfe
#define GC1054_FLIP_MIRROR_ADDR 0x17
#define GC1054_RES_IS_720P(w, h) ((w) <= 1280 && (h) <= 720)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
const GC1054_MODE_S *pstMode;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_stGc1054_mode;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = GC1054_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
#if 0
pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0;
pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0;
pstAeSnsDft->bAERouteExValid = CVI_FALSE;
pstAeSnsDft->stAERouteAttr.u32TotalNum = 0;
pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0;
#endif
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = pstMode->stAgain.u32Max;
pstAeSnsDft->u32MinAgain = pstMode->stAgain.u32Min;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = pstMode->stDgain.u32Max;
pstAeSnsDft->u32MinDgain = pstMode->stDgain.u32Min;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] :
pstMode->stExp.u16Def;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp.u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp.u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
case WDR_MODE_2To1_LINE:
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX = 0, u32VB = 0;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_stGc1054_mode.u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_stGc1054_mode.f32MaxFps;
f32MinFps = g_stGc1054_mode.f32MinFps;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > GC1054_FULL_LINES_MAX) ? GC1054_FULL_LINES_MAX : u32VMAX;
u32VB = u32VMAX - 724 - 16;
pstSnsRegsInfo->astI2cData[LINEAR_VB_H].u32Data = ((u32VB & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VB_L].u32Data = (u32VB & 0xFF);
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_H].u32Data = ((u32IntTime[0] & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_L].u32Data = (u32IntTime[0] & 0xFF);
return CVI_SUCCESS;
}
static CVI_U32 gain_table[11] = {
16*64,
16*91,
16*127,
16*182,
16*258,
16*369,
16*516,
16*738,
16*1032,
16*1491,
16*2084,
};
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
int i;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
if (*pu32AgainLin >= gain_table[11 - 1]) { //max 32.5625x
*pu32AgainDb = 11 - 1;
*pu32AgainLin = gain_table[11 - 1];
return CVI_SUCCESS;
}
for (i = 1; i < 11; i++) {
if (*pu32AgainLin < gain_table[i]) {
*pu32AgainDb = i - 1;
break;
}
}
*pu32AgainLin = gain_table[i - 1];
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
*pu32DgainLin = 1024;
*pu32DgainDb = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN].u32Data = *pu32Again;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
{
UNUSED(ViPipe);
UNUSED(u16ManRatioEnable);
UNUSED(au32Ratio);
UNUSED(au32IntTimeMax);
UNUSED(au32IntTimeMin);
UNUSED(pu32LFMaxIntTime);
return CVI_SUCCESS;
}
/* Only used in LINE_WDR mode */
static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr)
{
CMOS_CHECK_POINTER(pstAeFSWDRAttr);
genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode;
gu32MaxTimeGetCnt[ViPipe] = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
memcpy(pstDef->stNoiseCalibration.CalibrationCoef,
&g_stIspNoiseCalibratio, sizeof(ISP_CMOS_NOISE_CALIBRATION_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
UNUSED(ViPipe);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const GC1054_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_stGc1054_mode;
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsState->bSyncInit = CVI_FALSE;
switch (u8Mode) {
case WDR_MODE_NONE:
pstSnsState->u8ImgMode = GC1054_MODE_1280X720P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_stGc1054_mode.u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_NONE\n");
break;
case WDR_MODE_2To1_LINE:
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_FAILURE;
}
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunGc1054_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = gc1054_i2c_addr;
pstI2c_data[i].u32AddrByteNum = gc1054_addr_byte;
pstI2c_data[i].u32DataByteNum = gc1054_data_byte;
}
pstI2c_data[LINEAR_EXP_PAGE].u32RegAddr = GC1054_EXP_PAGE_ADDR;
pstI2c_data[LINEAR_EXP_PAGE].u32Data = 0;
pstI2c_data[LINEAR_EXP_H].u32RegAddr = GC1054_EXP_H_ADDR;
pstI2c_data[LINEAR_EXP_L].u32RegAddr = GC1054_EXP_L_ADDR;
pstI2c_data[LINEAR_GAIN_PAGE].u32RegAddr = GC1054_AGAIN_PAGE_ADDR;
pstI2c_data[LINEAR_GAIN_PAGE].u32Data = 1;
pstI2c_data[LINEAR_AGAIN].u32RegAddr = GC1054_AGAIN_ADDR;
pstI2c_data[LINEAR_VB_PAGE].u32RegAddr = GC1054_VB_PAGE_ADDR;
pstI2c_data[LINEAR_VB_PAGE].u32Data = 0;
pstI2c_data[LINEAR_VB_H].u32RegAddr = GC1054_VB_H_ADDR;
pstI2c_data[LINEAR_VB_L].u32RegAddr = GC1054_VB_L_ADDR;
pstI2c_data[LINEAR_FLIP_MIRROR_PAGE].u32RegAddr = GC1054_FLIP_MIRROR_PAGE_ADDR;
pstI2c_data[LINEAR_FLIP_MIRROR_PAGE].u32Data = 0;
pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = GC1054_FLIP_MIRROR_ADDR;
pstI2c_data[LINEAR_FLIP_MIRROR].u32Data = 0xc0;
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0, expUpdate = 0, vbUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
if (i == LINEAR_AGAIN)
gainsUpdate = 1;
if ((i >= LINEAR_EXP_H) && (i <= LINEAR_EXP_L))
expUpdate = 1;
if ((i >= LINEAR_VB_H) && (i <= LINEAR_VB_L))
vbUpdate = 1;
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_GAIN_PAGE].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN].bUpdate = CVI_TRUE;
}
if (expUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_PAGE].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_L].bUpdate = CVI_TRUE;
}
if (vbUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_VB_PAGE].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VB_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VB_L].bUpdate = CVI_TRUE;
}
if (pstI2c_data[LINEAR_FLIP_MIRROR].bUpdate == CVI_TRUE) {
pstI2c_data[LINEAR_FLIP_MIRROR_PAGE].bUpdate = CVI_TRUE;
}
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
pstCfg0->ispCfg.u8DelayFrmNum = 1;
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 30) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (GC1054_RES_IS_720P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = GC1054_MODE_1280X720P30;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps);
return CVI_FAILURE;
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 value = 0xC0;
CVI_U8 start_x = 3;
CVI_U8 start_y = 2;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_ISP_INFO_S *pstIspCfg0 = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstIspCfg0 = &pstSnsState->astSyncInfo[0].ispCfg;
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeGc1054_MirrorFip[ViPipe] != eSnsMirrorFlip) {
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
value = 0xC0;
start_x = 3;
start_y = 2;
break;
case ISP_SNS_MIRROR:
value = 0xC1;
start_x = 4;
start_y = 2;
break;
case ISP_SNS_FLIP:
value = 0xC2;
start_x = 3;
start_y = 3;
break;
case ISP_SNS_MIRROR_FLIP:
value = 0xC3;
start_x = 4;
start_y = 3;
break;
default:
return;
}
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 1;
pstIspCfg0->img_size[0].stWndRect.s32X = start_x;
pstIspCfg0->img_size[0].stWndRect.s32Y = start_y;
g_aeGc1054_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = GC1054_MODE_1280X720P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_stGc1054_mode.u32VtsDef;
pstSnsState->au32FL[0] = g_stGc1054_mode.u32VtsDef;
pstSnsState->au32FL[1] = g_stGc1054_mode.u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &gc1054_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_stGc1054_mode.stImg.stSnsSize.u32Width;
pstRxAttr->img_size.height = g_stGc1054_mode.stImg.stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc1054_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = gc1054_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = gc1054_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_S32 gc1054_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunGc1054_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
GC1054_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC1054_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
GC1054_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = GC1054_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC1054_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, GC1054_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, GC1054_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Gc1054_GainMode[ViPipe] = pstInitAttr->enGainMode;
g_au16Gc1054_L2SMode[ViPipe] = pstInitAttr->enL2SMode;
return CVI_SUCCESS;
}
ISP_SNS_OBJ_S stSnsGc1054_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = gc1054_standby,
.pfnRestart = gc1054_restart,
.pfnWriteReg = gc1054_write_register,
.pfnReadReg = gc1054_read_register,
.pfnSetBusInfo = gc1054_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = CVI_NULL,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = CVI_NULL,
};

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#ifndef __GC1054_CMOS_EX_H_
#define __GC1054_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#ifndef UNUSED
#define UNUSED(x) ((void)(x))
#endif
enum gc1054_linear_regs_e {
LINEAR_EXP_PAGE = 0, //fe
LINEAR_EXP_H, //03
LINEAR_EXP_L, //04
LINEAR_GAIN_PAGE, //fe
LINEAR_AGAIN, //b6
LINEAR_VB_PAGE, //fe
LINEAR_VB_H, //07
LINEAR_VB_L, //08
LINEAR_FLIP_MIRROR_PAGE, //fe
LINEAR_FLIP_MIRROR, //17
LINEAR_REGS_NUM
};
typedef enum _GC1054_MODE_E {
GC1054_MODE_1280X720P30 = 0,
GC1054_MODE_NUM
} GC1054_SLAVE_MODE_E;
typedef struct _GC1054_STATE_S {
CVI_U32 u32Sexp_MAX;
} GC1054_STATE_S;
typedef struct _GC1054_MODE_S {
ISP_WDR_SIZE_S stImg;
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp;
SNS_ATTR_LARGE_S stAgain;
SNS_ATTR_LARGE_S stDgain;
char name[64];
} GC1054_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc1054[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc1054_BusInfo[];
extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc1054_MirrorFip[VI_MAX_PIPE_NUM];
extern const CVI_U8 gc1054_i2c_addr;
extern const CVI_U32 gc1054_addr_byte;
extern const CVI_U32 gc1054_data_byte;
extern void gc1054_init(VI_PIPE ViPipe);
extern void gc1054_exit(VI_PIPE ViPipe);
extern void gc1054_standby(VI_PIPE ViPipe);
extern void gc1054_restart(VI_PIPE ViPipe);
extern int gc1054_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc1054_read_register(VI_PIPE ViPipe, int addr);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC1054_CMOS_EX_H_ */

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#ifndef __GC1054_CMOS_PARAM_H_
#define __GC1054_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc1054_cmos_ex.h"
static const GC1054_MODE_S g_stGc1054_mode = {
.name = "1280X720P30",
.stImg = {
.stSnsSize = {
.u32Width = 1288,
.u32Height = 724,
},
.stWndRect = {
.s32X = 3,
.s32Y = 2,
.u32Width = 1280,
.u32Height = 720,
},
.stMaxSize = {
.u32Width = 1288,
.u32Height = 724,
},
},
.f32MaxFps = 30,
.f32MinFps = 2.63, /* 782 * 30 / 8931*/
.u32HtsDef = 1726,
.u32VtsDef = 782, /* WIN_H + VB + 16 */
.stExp = {
.u16Min = 1,
.u16Max = 782 - 1, /* VtsDef - 1*/
.u16Def = 100,
.u16Step = 1,
},
.stAgain = {
.u32Min = 1024,
.u32Max = 16 * 2084,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain = {
.u32Min = 1024,
.u32Max = 1024,
.u32Def = 1024,
.u32Step = 1,
},
};
static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = {
{ //iso 100
{0.05999477580189704895, 0.13019448518753051758}, //B: slope, intercept
{0.06732148677110671997, -1.36387133598327636719}, //Gb: slope, intercept
{0.06651904433965682983, -1.10093510150909423828}, //Gr: slope, intercept
{0.06406146287918090820, 0.33316791057586669922}, //R: slope, intercept
},
{ //iso 200
{0.06256803125143051147, 4.54908418655395507813}, //B: slope, intercept
{0.06911934912204742432, 2.79023528099060058594}, //Gb: slope, intercept
{0.06846688687801361084, 2.88726186752319335938}, //Gr: slope, intercept
{0.06652788817882537842, 4.40276956558227539063}, //R: slope, intercept
},
{ //iso 400
{0.06841833144426345825, 11.72280883789062500000}, //B: slope, intercept
{0.07257881015539169312, 10.86985683441162109375}, //Gb: slope, intercept
{0.07174283266067504883, 11.20646286010742187500}, //Gr: slope, intercept
{0.07294593751430511475, 11.17350578308105468750}, //R: slope, intercept
},
{ //iso 800
{0.07805790752172470093, 20.62956619262695312500}, //B: slope, intercept
{0.07694032043218612671, 22.20356750488281250000}, //Gb: slope, intercept
{0.07647507637739181519, 22.50957298278808593750}, //Gr: slope, intercept
{0.08402533829212188721, 19.11953735351562500000}, //R: slope, intercept
},
{ //iso 1600
{0.09468275308609008789, 34.07563018798828125000}, //B: slope, intercept
{0.08710632473230361938, 39.15500259399414062500}, //Gb: slope, intercept
{0.08662072569131851196, 39.37175750732421875000}, //Gr: slope, intercept
{0.10222808271646499634, 31.34789276123046875000}, //R: slope, intercept
},
{ //iso 3200
{0.12651191651821136475, 49.56183242797851562500}, //B: slope, intercept
{0.10816962271928787231, 59.42719650268554687500}, //Gb: slope, intercept
{0.10751257836818695068, 59.90552902221679687500}, //Gr: slope, intercept
{0.13802853226661682129, 45.09576034545898437500}, //R: slope, intercept
},
{ //iso 6400
{0.17422541975975036621, 70.04063415527343750000}, //B: slope, intercept
{0.14234761893749237061, 85.51583862304687500000}, //Gb: slope, intercept
{0.14159946143627166748, 86.23278045654296875000}, //Gr: slope, intercept
{0.19450971484184265137, 62.65447235107421875000}, //R: slope, intercept
},
{ //iso 12800
{0.24947367608547210693, 108.30633544921875000000}, //B: slope, intercept
{0.19751225411891937256, 130.88159179687500000000}, //Gb: slope, intercept
{0.19614629447460174561, 132.49082946777343750000}, //Gr: slope, intercept
{0.28106108307838439941, 97.15969085693359375000}, //R: slope, intercept
},
{ //iso 25600
{0.35420843958854675293, 137.06745910644531250000}, //B: slope, intercept
{0.27778801321983337402, 168.72366333007812500000}, //Gb: slope, intercept
{0.27540388703346252441, 170.54939270019531250000}, //Gr: slope, intercept
{0.39949953556060791016, 123.29409790039062500000}, //R: slope, intercept
},
{ //iso 51200
{0.45704349875450134277, 179.20147705078125000000}, //B: slope, intercept
{0.32142028212547302246, 246.71363830566406250000}, //Gb: slope, intercept
{0.31958609819412231445, 246.82630920410156250000}, //Gr: slope, intercept
{0.51058447360992431641, 161.86299133300781250000}, //R: slope, intercept
},
{ //iso 102400
{0.61760461330413818359, 222.90534973144531250000}, //B: slope, intercept
{0.42568457126617431641, 319.29257202148437500000}, //Gb: slope, intercept
{0.41750904917716979980, 324.93432617187500000000}, //Gr: slope, intercept
{0.67956107854843139648, 203.78948974609375000000}, //R: slope, intercept
},
{ //iso 204800
{0.63289469480514526367, 216.99952697753906250000}, //B: slope, intercept
{0.44890350103378295898, 306.80810546875000000000}, //Gb: slope, intercept
{0.44229975342750549316, 310.13763427734375000000}, //Gr: slope, intercept
{0.69596910476684570313, 196.70443725585937500000}, //R: slope, intercept
},
{ //iso 409600
{0.71106964349746704102, 187.98352050781250000000}, //B: slope, intercept
{0.55859673023223876953, 246.22378540039062500000}, //Gb: slope, intercept
{0.55284017324447631836, 249.86463928222656250000}, //Gr: slope, intercept
{0.77318203449249267578, 168.85035705566406250000}, //R: slope, intercept
},
{ //iso 819200
{0.70888006687164306641, 188.44216918945312500000}, //B: slope, intercept
{0.56110274791717529297, 245.46603393554687500000}, //Gb: slope, intercept
{0.55100852251052856445, 250.33049011230468750000}, //Gr: slope, intercept
{0.76897650957107543945, 169.31251525878906250000}, //R: slope, intercept
},
{ //iso 1638400
{0.70520979166030883789, 188.93899536132812500000}, //B: slope, intercept
{0.56178557872772216797, 245.21235656738281250000}, //Gb: slope, intercept
{0.55338454246520996094, 249.57423400878906250000}, //Gr: slope, intercept
{0.77306479215621948242, 168.86497497558593750000}, //R: slope, intercept
},
{ //iso 3276800
{0.71255809068679809570, 187.86839294433593750000}, //B: slope, intercept
{0.56056070327758789063, 245.57748413085937500000}, //Gb: slope, intercept
{0.55358195304870605469, 249.62020874023437500000}, //Gr: slope, intercept
{0.77431541681289672852, 168.74313354492187500000}, //R: slope, intercept
},
} };
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {256, 256, 256, 256, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1092, 1092, 1092, 1092
#endif
},
.stAuto = {
{256, 256, 257, 257, 259, 259, 260, 267, 278, 298, 366, 383, 366, 373, 372, 372 },
{256, 256, 257, 257, 258, 259, 261, 266, 274, 297, 379, 377, 372, 365, 373, 374 },
{256, 256, 257, 257, 258, 259, 261, 266, 275, 296, 376, 388, 366, 374, 376, 372 },
{256, 256, 257, 257, 258, 259, 260, 264, 274, 294, 362, 363, 365, 361, 353, 367 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1092, 1092, 1093, 1093, 1093, 1093, 1093, 1095,
1099, 1104, 1125, 1130, 1125, 1127, 1126, 1126},
{1092, 1092, 1093, 1093, 1093, 1093, 1094, 1095,
1097, 1104, 1128, 1128, 1126, 1124, 1127, 1127},
{1092, 1092, 1093, 1093, 1093, 1093, 1094, 1095,
1098, 1104, 1128, 1131, 1125, 1127, 1128, 1126},
{1092, 1092, 1093, 1093, 1093, 1093, 1093, 1095,
1097, 1103, 1123, 1124, 1124, 1123, 1121, 1125},
#endif
},
},
};
struct combo_dev_attr_s gc1054_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {3, 4, -1, -1, -1},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
.dphy = {
.enable = 1,
.hs_settle = 8,
},
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.devno = 1,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC1054_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc1054_cmos_ex.h"
static void gc1054_linear_720p30_init(VI_PIPE ViPipe);
const CVI_U8 gc1054_i2c_addr = 0x21;//0x42
const CVI_U32 gc1054_addr_byte = 1;
const CVI_U32 gc1054_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc1054_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc1054_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc1054_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc1054_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc1054_read_register(VI_PIPE ViPipe, int addr)
{
/* TODO:*/
UNUSED(ViPipe);
UNUSED(addr);
return CVI_SUCCESS;
}
int gc1054_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc1054_addr_byte == 1) {
buf[idx] = addr & 0xff;
idx++;
}
if (gc1054_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc1054_addr_byte + gc1054_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
//ret = read(g_fd[ViPipe], buf, gc1054_addr_byte + gc1054_data_byte);
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void gc1054_standby(VI_PIPE ViPipe)
{
UNUSED(ViPipe);
printf("gc1054_standby\n");
}
void gc1054_restart(VI_PIPE ViPipe)
{
UNUSED(ViPipe);
printf("gc1054_restart\n");
}
void gc1054_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastGc1054[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
gc1054_write_register(ViPipe,
g_pastGc1054[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastGc1054[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
void gc1054_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode = g_pastGc1054[ViPipe]->enWDRMode;
gc1054_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n");
} else {
gc1054_linear_720p30_init(ViPipe);
}
g_pastGc1054[ViPipe]->bInit = CVI_TRUE;
}
void gc1054_exit(VI_PIPE ViPipe)
{
gc1054_i2c_exit(ViPipe);
}
static void gc1054_linear_720p30_init(VI_PIPE ViPipe)
{
/****system****/
gc1054_write_register(ViPipe, 0xf2, 0x00);
gc1054_write_register(ViPipe, 0xf6, 0x00);
gc1054_write_register(ViPipe, 0xfc, 0x04);
gc1054_write_register(ViPipe, 0xf7, 0x01);
gc1054_write_register(ViPipe, 0xf8, 0x0b);
gc1054_write_register(ViPipe, 0xf9, 0x06);
gc1054_write_register(ViPipe, 0xfa, 0x80);
gc1054_write_register(ViPipe, 0xfc, 0x0e);
/****CISCTL & ANALOG****/
gc1054_write_register(ViPipe, 0xfe, 0x00);
gc1054_write_register(ViPipe, 0x03, 0x02);
gc1054_write_register(ViPipe, 0x04, 0xa6);
gc1054_write_register(ViPipe, 0x05, 0x02); //HB
gc1054_write_register(ViPipe, 0x06, 0x07);
gc1054_write_register(ViPipe, 0x07, 0x00); //VB
gc1054_write_register(ViPipe, 0x08, 0x2a);
gc1054_write_register(ViPipe, 0x09, 0x00);
gc1054_write_register(ViPipe, 0x0a, 0x04); //row start
gc1054_write_register(ViPipe, 0x0b, 0x00);
gc1054_write_register(ViPipe, 0x0c, 0x00); //col start
gc1054_write_register(ViPipe, 0x0d, 0x02);
gc1054_write_register(ViPipe, 0x0e, 0xd8); //height 724
gc1054_write_register(ViPipe, 0x0f, 0x05);
gc1054_write_register(ViPipe, 0x10, 0x10); //width 1288
gc1054_write_register(ViPipe, 0x17, 0xc0);
gc1054_write_register(ViPipe, 0x18, 0x02);
gc1054_write_register(ViPipe, 0x19, 0x08);
gc1054_write_register(ViPipe, 0x1a, 0x18);
gc1054_write_register(ViPipe, 0x1d, 0x12);
gc1054_write_register(ViPipe, 0x1e, 0x50);
gc1054_write_register(ViPipe, 0x1f, 0x80);
gc1054_write_register(ViPipe, 0x21, 0x3a);
gc1054_write_register(ViPipe, 0x23, 0xe8);
gc1054_write_register(ViPipe, 0x25, 0x10);
gc1054_write_register(ViPipe, 0x28, 0x20);
gc1054_write_register(ViPipe, 0x34, 0x0a); //data low
gc1054_write_register(ViPipe, 0x3c, 0x10);
gc1054_write_register(ViPipe, 0x3d, 0x0e);
gc1054_write_register(ViPipe, 0xcc, 0x8f);
gc1054_write_register(ViPipe, 0xcd, 0x9a);
gc1054_write_register(ViPipe, 0xcf, 0x70);
gc1054_write_register(ViPipe, 0xd0, 0x9a);
gc1054_write_register(ViPipe, 0xd1, 0xc5);
gc1054_write_register(ViPipe, 0xd2, 0xed); //data high
gc1054_write_register(ViPipe, 0xd8, 0x3c); //dacin offset
gc1054_write_register(ViPipe, 0xd9, 0x7a);
gc1054_write_register(ViPipe, 0xda, 0x12);
gc1054_write_register(ViPipe, 0xdb, 0x50);
gc1054_write_register(ViPipe, 0xde, 0x0c);
gc1054_write_register(ViPipe, 0xe3, 0x60);
gc1054_write_register(ViPipe, 0xe4, 0x78);
gc1054_write_register(ViPipe, 0xfe, 0x01);
gc1054_write_register(ViPipe, 0xe3, 0x01);
gc1054_write_register(ViPipe, 0xe6, 0x16); //ramps offset
gc1054_write_register(ViPipe, 0xfe, 0x01);
gc1054_write_register(ViPipe, 0x80, 0x50);
gc1054_write_register(ViPipe, 0x88, 0x73);
gc1054_write_register(ViPipe, 0x89, 0x03);
gc1054_write_register(ViPipe, 0x90, 0x01);
gc1054_write_register(ViPipe, 0x92, 0x00); //crop win 2<=y<=4
gc1054_write_register(ViPipe, 0x94, 0x00); //crop win 2<=x<=5
gc1054_write_register(ViPipe, 0x95, 0x02); //crop win height
gc1054_write_register(ViPipe, 0x96, 0xd4);
gc1054_write_register(ViPipe, 0x97, 0x05); //crop win width
gc1054_write_register(ViPipe, 0x98, 0x08);
/*blk*/
gc1054_write_register(ViPipe, 0xfe, 0x01);
gc1054_write_register(ViPipe, 0x40, 0x22);
gc1054_write_register(ViPipe, 0x43, 0x03);
gc1054_write_register(ViPipe, 0x4e, 0x3c);
gc1054_write_register(ViPipe, 0x4f, 0x00);
gc1054_write_register(ViPipe, 0x60, 0x00);
gc1054_write_register(ViPipe, 0x61, 0x80);
/*gain*/
gc1054_write_register(ViPipe, 0xfe, 0x01);
gc1054_write_register(ViPipe, 0xb0, 0x48);
gc1054_write_register(ViPipe, 0xb1, 0x01);
gc1054_write_register(ViPipe, 0xb2, 0x00);
gc1054_write_register(ViPipe, 0xb6, 0x00);
gc1054_write_register(ViPipe, 0xfe, 0x02);
gc1054_write_register(ViPipe, 0x01, 0x00);
gc1054_write_register(ViPipe, 0x02, 0x01);
gc1054_write_register(ViPipe, 0x03, 0x02);
gc1054_write_register(ViPipe, 0x04, 0x03);
gc1054_write_register(ViPipe, 0x05, 0x04);
gc1054_write_register(ViPipe, 0x06, 0x05);
gc1054_write_register(ViPipe, 0x07, 0x06);
gc1054_write_register(ViPipe, 0x08, 0x0e);
gc1054_write_register(ViPipe, 0x09, 0x16);
gc1054_write_register(ViPipe, 0x0a, 0x1e);
gc1054_write_register(ViPipe, 0x0b, 0x36);
gc1054_write_register(ViPipe, 0x0c, 0x3e);
gc1054_write_register(ViPipe, 0x0d, 0x56);
gc1054_write_register(ViPipe, 0xfe, 0x02);
gc1054_write_register(ViPipe, 0xb0, 0x00); //col_gain[11:8]
gc1054_write_register(ViPipe, 0xb1, 0x00);
gc1054_write_register(ViPipe, 0xb2, 0x00);
gc1054_write_register(ViPipe, 0xb3, 0x11);
gc1054_write_register(ViPipe, 0xb4, 0x22);
gc1054_write_register(ViPipe, 0xb5, 0x54);
gc1054_write_register(ViPipe, 0xb6, 0xb8);
gc1054_write_register(ViPipe, 0xb7, 0x60);
gc1054_write_register(ViPipe, 0xb9, 0x00); //col_gain[12]
gc1054_write_register(ViPipe, 0xba, 0xc0);
gc1054_write_register(ViPipe, 0xc0, 0x20); //col_gain[7:0]
gc1054_write_register(ViPipe, 0xc1, 0x2d);
gc1054_write_register(ViPipe, 0xc2, 0x40);
gc1054_write_register(ViPipe, 0xc3, 0x5b);
gc1054_write_register(ViPipe, 0xc4, 0x80);
gc1054_write_register(ViPipe, 0xc5, 0xb5);
gc1054_write_register(ViPipe, 0xc6, 0x00);
gc1054_write_register(ViPipe, 0xc7, 0x6a);
gc1054_write_register(ViPipe, 0xc8, 0x00);
gc1054_write_register(ViPipe, 0xc9, 0xd4);
gc1054_write_register(ViPipe, 0xca, 0x00);
gc1054_write_register(ViPipe, 0xcb, 0xa8);
gc1054_write_register(ViPipe, 0xcc, 0x00);
gc1054_write_register(ViPipe, 0xcd, 0x50);
gc1054_write_register(ViPipe, 0xce, 0x00);
gc1054_write_register(ViPipe, 0xcf, 0xa1);
/****DARKSUN****/
gc1054_write_register(ViPipe, 0xfe, 0x02);
gc1054_write_register(ViPipe, 0x54, 0xf7);
gc1054_write_register(ViPipe, 0x55, 0xf0);
gc1054_write_register(ViPipe, 0x56, 0x00);
gc1054_write_register(ViPipe, 0x57, 0x00);
gc1054_write_register(ViPipe, 0x58, 0x00);
gc1054_write_register(ViPipe, 0x5a, 0x04);
/****DD****/
gc1054_write_register(ViPipe, 0xfe, 0x04);
gc1054_write_register(ViPipe, 0x40, 0x40); //blc 0x40-10bit
gc1054_write_register(ViPipe, 0x81, 0x8a);
/****DVP & MIPI****/
gc1054_write_register(ViPipe, 0xfe, 0x03);
gc1054_write_register(ViPipe, 0x01, 0x03);
gc1054_write_register(ViPipe, 0x02, 0x11);
gc1054_write_register(ViPipe, 0x03, 0x90);
gc1054_write_register(ViPipe, 0x10, 0x90);
gc1054_write_register(ViPipe, 0x11, 0x2b);
gc1054_write_register(ViPipe, 0x12, 0x4a); //lwc 1280*5/4
gc1054_write_register(ViPipe, 0x13, 0x06);
gc1054_write_register(ViPipe, 0x15, 0x06);
gc1054_write_register(ViPipe, 0x21, 0x02);
gc1054_write_register(ViPipe, 0x22, 0x02);
gc1054_write_register(ViPipe, 0x23, 0x08);
gc1054_write_register(ViPipe, 0x24, 0x02);
gc1054_write_register(ViPipe, 0x25, 0x10);
gc1054_write_register(ViPipe, 0x26, 0x04);
gc1054_write_register(ViPipe, 0x29, 0x02);
gc1054_write_register(ViPipe, 0x2a, 0x02);
gc1054_write_register(ViPipe, 0x2b, 0x08);
gc1054_write_register(ViPipe, 0x42, 0x08);
gc1054_write_register(ViPipe, 0x43, 0x05);
gc1054_write_register(ViPipe, 0xfe, 0x00);
gc1054_default_reg_init(ViPipe);
delay_ms(40);
printf("ViPipe:%d,===GC1054 720P 30fps 10bit LINE Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/gcore_gc2053/Makefile Normal file
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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc2053.a
TARGET_SO = $(MW_LIB)/libsns_gc2053.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

883
middleware/v2/component/isp/sensor/cv180x/gcore_gc2053/gc2053_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "gc2053_cmos_ex.h"
#include "gc2053_cmos_param.h"
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define GC2053_ID 2053
#define GC2053_I2C_ADDR_1 0x3f
#define GC2053_I2C_ADDR_2 0x37
#define GC2053_I2C_ADDR_IS_VALID(addr) ((addr) == GC2053_I2C_ADDR_1 || (addr) == GC2053_I2C_ADDR_2)
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_STATE_S *g_pastGc2053[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define GC2053_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc2053[dev])
#define GC2053_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc2053[dev] = pstCtx)
#define GC2053_SENSOR_RESET_CTX(dev) (g_pastGc2053[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunGc2053_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
GC2053_STATE_S g_astGc2053_State[VI_MAX_PIPE_NUM] = { {0} };
ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2053_MirrorFip[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc2053_GainMode[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc2053_L2SMode[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
****************************************************************************/
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Gc2053 Lines Range*****/
#define GC2053_FULL_LINES_MAX (0x3fff)
/*****Gc2053 Register Address*****/
#define GC2053_EXP_H_ADDR 0x03
#define GC2053_EXP_L_ADDR 0x04
#define GC2053_AGAIN_H_ADDR 0xb4
#define GC2053_AGAIN_L_ADDR 0xb3
#define GC2053_COL_AGAIN_H_ADDR 0xb8
#define GC2053_COL_AGAIN_L_ADDR 0xb9
#define GC2053_DGAIN_H_ADDR 0xb1
#define GC2053_DGAIN_L_ADDR 0xb2
#define GC2053_VTS_H_ADDR 0x41 //(frame length)
#define GC2053_VTS_L_ADDR 0x42
#define GC2053_RES_IS_1080P(w, h) ((w) == 1920 && (h) == 1080)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
const GC2053_MODE_S *pstMode;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_stGc2053_mode;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = GC2053_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
#if 0
pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0;
pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0;
pstAeSnsDft->bAERouteExValid = CVI_FALSE;
pstAeSnsDft->stAERouteAttr.u32TotalNum = 0;
pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0;
#endif
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = 3985*16;
pstAeSnsDft->u32MinAgain = 1024;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = 10240;
pstAeSnsDft->u32MinDgain = 1024;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] :
pstMode->stExp.u16Def;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp.u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp.u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
case WDR_MODE_2To1_LINE:
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX = 0;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_stGc2053_mode.u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_stGc2053_mode.f32MaxFps;
f32MinFps = g_stGc2053_mode.f32MinFps;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > GC2053_FULL_LINES_MAX) ? GC2053_FULL_LINES_MAX : u32VMAX;
pstSnsRegsInfo->astI2cData[LINEAR_VTS_H].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_L].u32Data = (u32VMAX & 0xFF);
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_H].u32Data = ((u32IntTime[0] & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_L].u32Data = (u32IntTime[0] & 0xFF);
return CVI_SUCCESS;
}
static CVI_U32 regValTable[25][4] = {
{0x00, 0x00, 0x01, 0x00},
{0x00, 0x10, 0x01, 0x0c},
{0x00, 0x20, 0x01, 0x1b},
{0x00, 0x30, 0x01, 0x2c},
{0x00, 0x40, 0x01, 0x3f},
{0x00, 0x50, 0x02, 0x16},
{0x00, 0x60, 0x02, 0x35},
{0x00, 0x70, 0x03, 0x16},
{0x00, 0x80, 0x04, 0x02},
{0x00, 0x90, 0x04, 0x31},
{0x00, 0xa0, 0x05, 0x32},
{0x00, 0xb0, 0x06, 0x35},
{0x00, 0xc0, 0x08, 0x04},
{0x00, 0x5a, 0x09, 0x19},
{0x00, 0x83, 0x0b, 0x0f},
{0x00, 0x93, 0x0d, 0x12},
{0x00, 0x84, 0x10, 0x00},
{0x00, 0x94, 0x12, 0x3a},
{0x01, 0x2c, 0x1a, 0x02},
{0x01, 0x3c, 0x1b, 0x20},
{0x00, 0x8c, 0x20, 0x0f},
{0x00, 0x9c, 0x26, 0x07},
{0x02, 0x64, 0x36, 0x21},
{0x02, 0x74, 0x37, 0x3a},
{0x00, 0xc6, 0x3d, 0x02},
};
static CVI_U32 gain_table[25] = {
64*16, 76*16, 90*16, 108*16, 127*16, 148*16, 180*16, 216*16, 255*16, 300*16,
361*16, 422*16, 504*16, 593*16, 722*16, 850*16, 1008*16, 1182*16, 1408*16, 1689*16,
2021*16, 2391*16, 2850*16, 3369*16, 3985*16,/* 4805*16, 5768*16, 6806*16, 7723*16,*/
};
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
int i, total;
CVI_U32 pregain;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
total = sizeof(gain_table) / sizeof(CVI_U32);
if (*pu32AgainLin >= gain_table[total - 1]) {
*pu32AgainLin = *pu32AgainDb = gain_table[total - 1];
return CVI_SUCCESS;
}
for (i = 1; i < total; i++) {
if (*pu32AgainLin < gain_table[i])
break;
}
i--;
// find the pregain
pregain = *pu32AgainLin * 64 / gain_table[i];
// set the Db as the AE algo gain, we need this to do gain update
*pu32AgainDb = *pu32AgainLin;
// set the Lin as the closest sensor gain for AE algo reference
*pu32AgainLin = pregain * gain_table[i] / 64;
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
CVI_U32 pregain;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
// find the pregain
pregain = *pu32DgainLin * 64 / 1024;
// set the Db as the AE algo gain, we need this to do gain update
*pu32DgainDb = *pu32DgainLin;
// set the Lin as the closest sensor gain for AE algo reference
*pu32DgainLin = pregain * 16;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32Again;
CVI_U32 u32Dgain;
int i, total;
total = sizeof(gain_table) / sizeof(CVI_U32);
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* only surpport linear mode */
u32Again = pu32Again[0];
/* To kepp the linearity. we assume AE algo adjusts the dgain only when the again reachs the maximum value */
if (u32Again < (3985*16)) {
for (i = 1; i < total; i++) {
if (*pu32Again < gain_table[i])
break;
}
i--;
// find the pregain
u32Dgain = u32Again * 64 / gain_table[i];
u32Again = i;
} else {
u32Again = total - 1;
// find the pregain
u32Dgain = pu32Dgain[0] * 64 / 1024;
}
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_H].u32Data = regValTable[u32Again][0];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_L].u32Data = regValTable[u32Again][1];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_H].u32Data = regValTable[u32Again][2];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_L].u32Data = regValTable[u32Again][3];
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 6);
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0x3F) << 2;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
//pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
//pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
memcpy(pstDef->stNoiseCalibration.CalibrationCoef,
&g_stIspNoiseCalibratio, sizeof(ISP_CMOS_NOISE_CALIBRATION_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
UNUSED(ViPipe);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const GC2053_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_stGc2053_mode;
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsState->bSyncInit = CVI_FALSE;
switch (u8Mode) {
case WDR_MODE_NONE:
pstSnsState->u8ImgMode = GC2053_MODE_1920X1080P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_stGc2053_mode.u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_NONE\n");
break;
case WDR_MODE_2To1_LINE:
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_FAILURE;
}
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunGc2053_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = gc2053_i2c_addr;
pstI2c_data[i].u32AddrByteNum = gc2053_addr_byte;
pstI2c_data[i].u32DataByteNum = gc2053_data_byte;
}
pstI2c_data[LINEAR_EXP_H].u32RegAddr = GC2053_EXP_H_ADDR;
pstI2c_data[LINEAR_EXP_L].u32RegAddr = GC2053_EXP_L_ADDR;
pstI2c_data[LINEAR_AGAIN_H].u32RegAddr = GC2053_AGAIN_H_ADDR;
pstI2c_data[LINEAR_AGAIN_L].u32RegAddr = GC2053_AGAIN_L_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_H].u32RegAddr = GC2053_COL_AGAIN_H_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_L].u32RegAddr = GC2053_COL_AGAIN_L_ADDR;
pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = GC2053_DGAIN_H_ADDR;
pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = GC2053_DGAIN_L_ADDR;
pstI2c_data[LINEAR_VTS_H].u32RegAddr = GC2053_VTS_H_ADDR;
pstI2c_data[LINEAR_VTS_L].u32RegAddr = GC2053_VTS_L_ADDR;
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
if ((i >= LINEAR_AGAIN_H) && (i <= LINEAR_DGAIN_L))
gainsUpdate = 1;
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_L].bUpdate = CVI_TRUE;
}
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 30) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (GC2053_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = GC2053_MODE_1920X1080P30;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps);
return CVI_FAILURE;
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeGc2053_MirrorFip[ViPipe] != eSnsMirrorFlip) {
gc2053_mirror_flip(ViPipe, eSnsMirrorFlip);
g_aeGc2053_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = GC2053_MODE_1920X1080P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_stGc2053_mode.u32VtsDef;
pstSnsState->au32FL[0] = g_stGc2053_mode.u32VtsDef;
pstSnsState->au32FL[1] = g_stGc2053_mode.u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &gc2053_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_stGc2053_mode.stImg.stSnsSize.u32Width;
pstRxAttr->img_size.height = g_stGc2053_mode.stImg.stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc2053_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = gc2053_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = gc2053_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (GC2053_I2C_ADDR_IS_VALID(s32I2cAddr))
gc2053_i2c_addr = s32I2cAddr;
}
static CVI_S32 gc2053_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunGc2053_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC2053_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
GC2053_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC2053_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
GC2053_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = GC2053_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC2053_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, GC2053_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, GC2053_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Gc2053_GainMode[ViPipe] = pstInitAttr->enGainMode;
g_au16Gc2053_L2SMode[ViPipe] = pstInitAttr->enL2SMode;
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return gc2053_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsGc2053_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = gc2053_standby,
.pfnRestart = gc2053_restart,
.pfnWriteReg = gc2053_write_register,
.pfnReadReg = gc2053_read_register,
.pfnSetBusInfo = gc2053_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = sensor_probe,
};

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#ifndef __GC2053_CMOS_EX_H_
#define __GC2053_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#ifndef UNUSED
#define UNUSED(x) ((void)(x))
#endif
enum gc2053_linear_regs_e {
LINEAR_EXP_H = 0,//03
LINEAR_EXP_L, //04
LINEAR_AGAIN_H, //b4
LINEAR_AGAIN_L, //b3
LINEAR_COL_AGAIN_H, //b8
LINEAR_COL_AGAIN_L, //b9
LINEAR_DGAIN_H, //b1
LINEAR_DGAIN_L, //b2
LINEAR_VTS_H, //0x41 (frame length)
LINEAR_VTS_L,//0x42
LINEAR_REGS_NUM
};
typedef enum _GC2053_MODE_E {
GC2053_MODE_1920X1080P30 = 0,
GC2053_MODE_NUM
} GC2053_SLAVE_MODE_E;
typedef struct _GC2053_STATE_S {
CVI_U32 u32Sexp_MAX;
} GC2053_STATE_S;
typedef struct _GC2053_MODE_S {
ISP_WDR_SIZE_S stImg;
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp;
SNS_ATTR_LARGE_S stAgain;
SNS_ATTR_LARGE_S stDgain;
char name[64];
} GC2053_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc2053[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc2053_BusInfo[];
extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2053_MirrorFip[VI_MAX_PIPE_NUM];
extern CVI_U8 gc2053_i2c_addr;
extern const CVI_U32 gc2053_addr_byte;
extern const CVI_U32 gc2053_data_byte;
extern void gc2053_init(VI_PIPE ViPipe);
extern void gc2053_exit(VI_PIPE ViPipe);
extern void gc2053_standby(VI_PIPE ViPipe);
extern void gc2053_restart(VI_PIPE ViPipe);
extern int gc2053_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc2053_read_register(VI_PIPE ViPipe, int addr);
extern void gc2053_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int gc2053_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2053_CMOS_EX_H_ */

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#ifndef __GC2053_CMOS_PARAM_H_
#define __GC2053_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2053_cmos_ex.h"
static const GC2053_MODE_S g_stGc2053_mode = {
.name = "1920X1080P30",
.stImg = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
.f32MaxFps = 30,
.f32MinFps = 2.07, /* 1125 * 30 / 0x3FFF */
.u32HtsDef = 2200,
.u32VtsDef = 1125,
.stExp = {
.u16Min = 1,
.u16Max = 0x3fff,
.u16Def = 0x2000,
.u16Step = 1,
},
.stAgain = {
.u32Min = 64,
.u32Max = 62977,
.u32Def = 64,
.u32Step = 1,
},
.stDgain = {
.u32Min = 64*16,
.u32Max = 7073*16,
.u32Def = 581*16,
.u32Step = 10*16,
},
};
static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = {
{ //iso 100
{0.05999477580189704895, 0.13019448518753051758}, //B: slope, intercept
{0.06732148677110671997, -1.36387133598327636719}, //Gb: slope, intercept
{0.06651904433965682983, -1.10093510150909423828}, //Gr: slope, intercept
{0.06406146287918090820, 0.33316791057586669922}, //R: slope, intercept
},
{ //iso 200
{0.06256803125143051147, 4.54908418655395507813}, //B: slope, intercept
{0.06911934912204742432, 2.79023528099060058594}, //Gb: slope, intercept
{0.06846688687801361084, 2.88726186752319335938}, //Gr: slope, intercept
{0.06652788817882537842, 4.40276956558227539063}, //R: slope, intercept
},
{ //iso 400
{0.06841833144426345825, 11.72280883789062500000}, //B: slope, intercept
{0.07257881015539169312, 10.86985683441162109375}, //Gb: slope, intercept
{0.07174283266067504883, 11.20646286010742187500}, //Gr: slope, intercept
{0.07294593751430511475, 11.17350578308105468750}, //R: slope, intercept
},
{ //iso 800
{0.07805790752172470093, 20.62956619262695312500}, //B: slope, intercept
{0.07694032043218612671, 22.20356750488281250000}, //Gb: slope, intercept
{0.07647507637739181519, 22.50957298278808593750}, //Gr: slope, intercept
{0.08402533829212188721, 19.11953735351562500000}, //R: slope, intercept
},
{ //iso 1600
{0.09468275308609008789, 34.07563018798828125000}, //B: slope, intercept
{0.08710632473230361938, 39.15500259399414062500}, //Gb: slope, intercept
{0.08662072569131851196, 39.37175750732421875000}, //Gr: slope, intercept
{0.10222808271646499634, 31.34789276123046875000}, //R: slope, intercept
},
{ //iso 3200
{0.12651191651821136475, 49.56183242797851562500}, //B: slope, intercept
{0.10816962271928787231, 59.42719650268554687500}, //Gb: slope, intercept
{0.10751257836818695068, 59.90552902221679687500}, //Gr: slope, intercept
{0.13802853226661682129, 45.09576034545898437500}, //R: slope, intercept
},
{ //iso 6400
{0.17422541975975036621, 70.04063415527343750000}, //B: slope, intercept
{0.14234761893749237061, 85.51583862304687500000}, //Gb: slope, intercept
{0.14159946143627166748, 86.23278045654296875000}, //Gr: slope, intercept
{0.19450971484184265137, 62.65447235107421875000}, //R: slope, intercept
},
{ //iso 12800
{0.24947367608547210693, 108.30633544921875000000}, //B: slope, intercept
{0.19751225411891937256, 130.88159179687500000000}, //Gb: slope, intercept
{0.19614629447460174561, 132.49082946777343750000}, //Gr: slope, intercept
{0.28106108307838439941, 97.15969085693359375000}, //R: slope, intercept
},
{ //iso 25600
{0.35420843958854675293, 137.06745910644531250000}, //B: slope, intercept
{0.27778801321983337402, 168.72366333007812500000}, //Gb: slope, intercept
{0.27540388703346252441, 170.54939270019531250000}, //Gr: slope, intercept
{0.39949953556060791016, 123.29409790039062500000}, //R: slope, intercept
},
{ //iso 51200
{0.45704349875450134277, 179.20147705078125000000}, //B: slope, intercept
{0.32142028212547302246, 246.71363830566406250000}, //Gb: slope, intercept
{0.31958609819412231445, 246.82630920410156250000}, //Gr: slope, intercept
{0.51058447360992431641, 161.86299133300781250000}, //R: slope, intercept
},
{ //iso 102400
{0.61760461330413818359, 222.90534973144531250000}, //B: slope, intercept
{0.42568457126617431641, 319.29257202148437500000}, //Gb: slope, intercept
{0.41750904917716979980, 324.93432617187500000000}, //Gr: slope, intercept
{0.67956107854843139648, 203.78948974609375000000}, //R: slope, intercept
},
{ //iso 204800
{0.63289469480514526367, 216.99952697753906250000}, //B: slope, intercept
{0.44890350103378295898, 306.80810546875000000000}, //Gb: slope, intercept
{0.44229975342750549316, 310.13763427734375000000}, //Gr: slope, intercept
{0.69596910476684570313, 196.70443725585937500000}, //R: slope, intercept
},
{ //iso 409600
{0.71106964349746704102, 187.98352050781250000000}, //B: slope, intercept
{0.55859673023223876953, 246.22378540039062500000}, //Gb: slope, intercept
{0.55284017324447631836, 249.86463928222656250000}, //Gr: slope, intercept
{0.77318203449249267578, 168.85035705566406250000}, //R: slope, intercept
},
{ //iso 819200
{0.70888006687164306641, 188.44216918945312500000}, //B: slope, intercept
{0.56110274791717529297, 245.46603393554687500000}, //Gb: slope, intercept
{0.55100852251052856445, 250.33049011230468750000}, //Gr: slope, intercept
{0.76897650957107543945, 169.31251525878906250000}, //R: slope, intercept
},
{ //iso 1638400
{0.70520979166030883789, 188.93899536132812500000}, //B: slope, intercept
{0.56178557872772216797, 245.21235656738281250000}, //Gb: slope, intercept
{0.55338454246520996094, 249.57423400878906250000}, //Gr: slope, intercept
{0.77306479215621948242, 168.86497497558593750000}, //R: slope, intercept
},
{ //iso 3276800
{0.71255809068679809570, 187.86839294433593750000}, //B: slope, intercept
{0.56056070327758789063, 245.57748413085937500000}, //Gb: slope, intercept
{0.55358195304870605469, 249.62020874023437500000}, //Gr: slope, intercept
{0.77431541681289672852, 168.74313354492187500000}, //R: slope, intercept
},
} };
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {257, 257, 257, 257, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1093, 1093, 1093, 1093
#endif
},
.stAuto = {
{257, 257, 257, 257, 259, 259, 260, 267, 278, 298, 366, 383, 366, 373, 372, 372 },
{257, 257, 257, 257, 258, 259, 261, 266, 274, 297, 379, 377, 372, 365, 373, 374 },
{257, 257, 257, 257, 258, 259, 261, 266, 275, 296, 376, 388, 366, 374, 376, 372 },
{257, 257, 257, 257, 258, 259, 260, 264, 274, 294, 362, 363, 365, 361, 353, 367 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1093, 1093, 1093, 1093, 1093, 1093, 1093, 1095,
1099, 1104, 1125, 1130, 1125, 1127, 1126, 1126},
{1093, 1093, 1093, 1093, 1093, 1093, 1094, 1095,
1097, 1104, 1128, 1128, 1126, 1124, 1127, 1127},
{1093, 1093, 1093, 1093, 1093, 1093, 1094, 1095,
1098, 1104, 1128, 1131, 1125, 1127, 1128, 1126},
{1093, 1093, 1093, 1093, 1093, 1093, 1093, 1095,
1097, 1103, 1123, 1124, 1124, 1123, 1121, 1125},
#endif
},
},
};
struct combo_dev_attr_s gc2053_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {1, 3, 2, -1, -1},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2053_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2053_cmos_ex.h"
#define GC2053_CHIP_ID_ADDR_H 0xf0
#define GC2053_CHIP_ID_ADDR_L 0xf1
#define GC2053_CHIP_ID 0x2053
static void gc2053_linear_1080p30_init(VI_PIPE ViPipe);
CVI_U8 gc2053_i2c_addr = 0x37;//0x6e
const CVI_U32 gc2053_addr_byte = 1;
const CVI_U32 gc2053_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc2053_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc2053_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc2053_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc2053_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc2053_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (gc2053_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, gc2053_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, gc2053_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (gc2053_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int gc2053_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc2053_addr_byte == 1) {
buf[idx] = addr & 0xff;
idx++;
}
if (gc2053_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc2053_addr_byte + gc2053_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
//syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void gc2053_standby(VI_PIPE ViPipe)
{
gc2053_write_register(ViPipe, 0x3e, 0x00);
gc2053_write_register(ViPipe, 0xf7, 0x00);
gc2053_write_register(ViPipe, 0xfc, 0x01);
gc2053_write_register(ViPipe, 0xf9, 0x83);
printf("gc2053_standby\n");
}
void gc2053_restart(VI_PIPE ViPipe)
{
gc2053_write_register(ViPipe, 0xf9, 0x82);
delay_ms(2);
gc2053_write_register(ViPipe, 0xf7, 0x01);
gc2053_write_register(ViPipe, 0xfc, 0x8e);
gc2053_write_register(ViPipe, 0x3e, 0x91);
printf("gc2053_restart\n");
}
void gc2053_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastGc2053[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
gc2053_write_register(ViPipe,
g_pastGc2053[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastGc2053[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
void gc2053_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 value = 0;
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
value = 0x01;
break;
case ISP_SNS_FLIP:
value = 0x02;
break;
case ISP_SNS_MIRROR_FLIP:
value = 0x03;
break;
default:
return;
}
gc2053_write_register(ViPipe, 0xfe, 0x00);
gc2053_write_register(ViPipe, 0x17, value);
}
int gc2053_probe(VI_PIPE ViPipe)
{
int nVal;
int nVal2;
usleep(50);
if (gc2053_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = gc2053_read_register(ViPipe, GC2053_CHIP_ID_ADDR_H);
nVal2 = gc2053_read_register(ViPipe, GC2053_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC2053_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void gc2053_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode = g_pastGc2053[ViPipe]->enWDRMode;
gc2053_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n");
} else {
gc2053_linear_1080p30_init(ViPipe);
}
g_pastGc2053[ViPipe]->bInit = CVI_TRUE;
}
void gc2053_exit(VI_PIPE ViPipe)
{
gc2053_i2c_exit(ViPipe);
}
static void gc2053_linear_1080p30_init(VI_PIPE ViPipe)
{
/****system****/
gc2053_write_register(ViPipe, 0xfe, 0x80);
gc2053_write_register(ViPipe, 0xfe, 0x80);
gc2053_write_register(ViPipe, 0xfe, 0x80);
gc2053_write_register(ViPipe, 0xfe, 0x00);
gc2053_write_register(ViPipe, 0xf2, 0x00);
gc2053_write_register(ViPipe, 0xf3, 0x00);
gc2053_write_register(ViPipe, 0xf4, 0x36);
gc2053_write_register(ViPipe, 0xf5, 0xc0);
gc2053_write_register(ViPipe, 0xf6, 0x44);
gc2053_write_register(ViPipe, 0xf7, 0x01);
gc2053_write_register(ViPipe, 0xf8, 0x2c);
gc2053_write_register(ViPipe, 0xf9, 0x42);
gc2053_write_register(ViPipe, 0xfc, 0x8e);
/****CISCTL & ANALOG****/
gc2053_write_register(ViPipe, 0xfe, 0x00);
gc2053_write_register(ViPipe, 0x87, 0x18);
gc2053_write_register(ViPipe, 0xee, 0x30);
gc2053_write_register(ViPipe, 0xd0, 0xb7);
gc2053_write_register(ViPipe, 0x03, 0x04);
gc2053_write_register(ViPipe, 0x04, 0x60);
gc2053_write_register(ViPipe, 0x05, 0x04);
gc2053_write_register(ViPipe, 0x06, 0x4c);
gc2053_write_register(ViPipe, 0x07, 0x00);
gc2053_write_register(ViPipe, 0x08, 0x11);
gc2053_write_register(ViPipe, 0x09, 0x00);
gc2053_write_register(ViPipe, 0x0a, 0x02);
gc2053_write_register(ViPipe, 0x0b, 0x00);
gc2053_write_register(ViPipe, 0x0c, 0x02);
gc2053_write_register(ViPipe, 0x0d, 0x04);
gc2053_write_register(ViPipe, 0x0e, 0x40);
gc2053_write_register(ViPipe, 0x12, 0xe2);
gc2053_write_register(ViPipe, 0x13, 0x16);
gc2053_write_register(ViPipe, 0x19, 0x0a);
gc2053_write_register(ViPipe, 0x21, 0x1c);
gc2053_write_register(ViPipe, 0x28, 0x0a);
gc2053_write_register(ViPipe, 0x29, 0x24);
gc2053_write_register(ViPipe, 0x2b, 0x04);
gc2053_write_register(ViPipe, 0x32, 0xf8);
gc2053_write_register(ViPipe, 0x37, 0x03);
gc2053_write_register(ViPipe, 0x39, 0x15);
gc2053_write_register(ViPipe, 0x41, 0x04);
gc2053_write_register(ViPipe, 0x42, 0x65);
gc2053_write_register(ViPipe, 0x43, 0x07);
gc2053_write_register(ViPipe, 0x44, 0x40);
gc2053_write_register(ViPipe, 0x46, 0x0b);
gc2053_write_register(ViPipe, 0x4b, 0x20);
gc2053_write_register(ViPipe, 0x4e, 0x08);
gc2053_write_register(ViPipe, 0x55, 0x20);
gc2053_write_register(ViPipe, 0x66, 0x05);
gc2053_write_register(ViPipe, 0x67, 0x05);
gc2053_write_register(ViPipe, 0x77, 0x01);
gc2053_write_register(ViPipe, 0x78, 0x00);
gc2053_write_register(ViPipe, 0x7c, 0x93);
gc2053_write_register(ViPipe, 0x8c, 0x12);
gc2053_write_register(ViPipe, 0x8d, 0x92);
gc2053_write_register(ViPipe, 0x90, 0x00);
gc2053_write_register(ViPipe, 0x9d, 0x10);
gc2053_write_register(ViPipe, 0xce, 0x7c);
gc2053_write_register(ViPipe, 0xd2, 0x41);
gc2053_write_register(ViPipe, 0xd3, 0xdc);
gc2053_write_register(ViPipe, 0xe6, 0x50);
/*gain*/
gc2053_write_register(ViPipe, 0xb6, 0xc0);
gc2053_write_register(ViPipe, 0xb0, 0x70);
gc2053_write_register(ViPipe, 0xb1, 0x01);
gc2053_write_register(ViPipe, 0xb2, 0x00);
gc2053_write_register(ViPipe, 0xb3, 0x00);
gc2053_write_register(ViPipe, 0xb4, 0x00);
gc2053_write_register(ViPipe, 0xb8, 0x01);
gc2053_write_register(ViPipe, 0xb9, 0x00);
/*blk*/
gc2053_write_register(ViPipe, 0x26, 0x30);
gc2053_write_register(ViPipe, 0xfe, 0x01);
gc2053_write_register(ViPipe, 0x40, 0x23);
gc2053_write_register(ViPipe, 0x55, 0x07);
gc2053_write_register(ViPipe, 0x60, 0x40);
gc2053_write_register(ViPipe, 0xfe, 0x04);
gc2053_write_register(ViPipe, 0x14, 0x78);
gc2053_write_register(ViPipe, 0x15, 0x78);
gc2053_write_register(ViPipe, 0x16, 0x78);
gc2053_write_register(ViPipe, 0x17, 0x78);
/*window*/
gc2053_write_register(ViPipe, 0xfe, 0x01);
gc2053_write_register(ViPipe, 0x91, 0x00);
gc2053_write_register(ViPipe, 0x92, 0x00);
gc2053_write_register(ViPipe, 0x93, 0x00);
gc2053_write_register(ViPipe, 0x94, 0x03);
gc2053_write_register(ViPipe, 0x95, 0x04);
gc2053_write_register(ViPipe, 0x96, 0x38);
gc2053_write_register(ViPipe, 0x97, 0x07);
gc2053_write_register(ViPipe, 0x98, 0x80);
/*ISP*/
gc2053_write_register(ViPipe, 0xfe, 0x01);
gc2053_write_register(ViPipe, 0x01, 0x05);
gc2053_write_register(ViPipe, 0x02, 0x89);
gc2053_write_register(ViPipe, 0x04, 0x01);
gc2053_write_register(ViPipe, 0x07, 0xa6);
gc2053_write_register(ViPipe, 0x08, 0xa9);
gc2053_write_register(ViPipe, 0x09, 0xa8);
gc2053_write_register(ViPipe, 0x0a, 0xa7);
gc2053_write_register(ViPipe, 0x0b, 0xff);
gc2053_write_register(ViPipe, 0x0c, 0xff);
gc2053_write_register(ViPipe, 0x0f, 0x00);
gc2053_write_register(ViPipe, 0x50, 0x1c);
gc2053_write_register(ViPipe, 0x89, 0x03);
gc2053_write_register(ViPipe, 0xfe, 0x04);
gc2053_write_register(ViPipe, 0x28, 0x86);
gc2053_write_register(ViPipe, 0x29, 0x86);
gc2053_write_register(ViPipe, 0x2a, 0x86);
gc2053_write_register(ViPipe, 0x2b, 0x68);
gc2053_write_register(ViPipe, 0x2c, 0x68);
gc2053_write_register(ViPipe, 0x2d, 0x68);
gc2053_write_register(ViPipe, 0x2e, 0x68);
gc2053_write_register(ViPipe, 0x2f, 0x68);
gc2053_write_register(ViPipe, 0x30, 0x4f);
gc2053_write_register(ViPipe, 0x31, 0x68);
gc2053_write_register(ViPipe, 0x32, 0x67);
gc2053_write_register(ViPipe, 0x33, 0x66);
gc2053_write_register(ViPipe, 0x34, 0x66);
gc2053_write_register(ViPipe, 0x35, 0x66);
gc2053_write_register(ViPipe, 0x36, 0x66);
gc2053_write_register(ViPipe, 0x37, 0x66);
gc2053_write_register(ViPipe, 0x38, 0x62);
gc2053_write_register(ViPipe, 0x39, 0x62);
gc2053_write_register(ViPipe, 0x3a, 0x62);
gc2053_write_register(ViPipe, 0x3b, 0x62);
gc2053_write_register(ViPipe, 0x3c, 0x62);
gc2053_write_register(ViPipe, 0x3d, 0x62);
gc2053_write_register(ViPipe, 0x3e, 0x62);
gc2053_write_register(ViPipe, 0x3f, 0x62);
/****DVP & MIPI****/
gc2053_write_register(ViPipe, 0xfe, 0x01);
gc2053_write_register(ViPipe, 0x9a, 0x06);
gc2053_write_register(ViPipe, 0xfe, 0x00);
gc2053_write_register(ViPipe, 0x7b, 0x2a);
gc2053_write_register(ViPipe, 0x23, 0x2d);
gc2053_write_register(ViPipe, 0xfe, 0x03);
gc2053_write_register(ViPipe, 0x01, 0x27);
gc2053_write_register(ViPipe, 0x02, 0x56);
gc2053_write_register(ViPipe, 0x03, 0x8e);
gc2053_write_register(ViPipe, 0x12, 0x80);
gc2053_write_register(ViPipe, 0x13, 0x07);
gc2053_write_register(ViPipe, 0x15, 0x12);
gc2053_write_register(ViPipe, 0xfe, 0x00);
gc2053_write_register(ViPipe, 0x3e, 0x91);
gc2053_default_reg_init(ViPipe);
printf("ViPipe:%d,===GC2053 1080P 30fps 10bit LINE Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/gcore_gc2053_1L/Makefile Normal file
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@ -0,0 +1,36 @@
SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc2053_1l.a
TARGET_SO = $(MW_LIB)/libsns_gc2053_1l.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

969
middleware/v2/component/isp/sensor/cv180x/gcore_gc2053_1L/gc2053_1l_cmos.c Normal file
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@ -0,0 +1,969 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "gc2053_1l_cmos_ex.h"
#include "gc2053_1l_cmos_param.h"
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define GC2053_1L_ID 2053
#define GC2053_1L_I2C_ADDR_1 0x3f
#define GC2053_1L_I2C_ADDR_2 0x37
#define GC2053_1L_I2C_ADDR_IS_VALID(addr) ((addr) == GC2053_1L_I2C_ADDR_1 || (addr) == GC2053_1L_I2C_ADDR_2)
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_STATE_S *g_pastGc2053_1l[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define GC2053_1L_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc2053_1l[dev])
#define GC2053_1L_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc2053_1l[dev] = pstCtx)
#define GC2053_1L_SENSOR_RESET_CTX(dev) (g_pastGc2053_1l[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunGc2053_1l_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
GC2053_1L_STATE_S g_astGc2053_1l_State[VI_MAX_PIPE_NUM] = { {0} };
ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2053_1l_MirrorFip[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc2053_1l_GainMode[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc2053_1l_L2SMode[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
****************************************************************************/
static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = {
[0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE
};
static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Gc2053_1l Lines Range*****/
#define GC2053_1L_FULL_LINES_MAX (0x3fff)
/*****Gc2053_1l Register Address*****/
#define GC2053_1L_EXP_H_ADDR 0x03
#define GC2053_1L_EXP_L_ADDR 0x04
#define GC2053_1L_AGAIN_H_ADDR 0xb4
#define GC2053_1L_AGAIN_L_ADDR 0xb3
#define GC2053_1L_COL_AGAIN_H_ADDR 0xb8
#define GC2053_1L_COL_AGAIN_L_ADDR 0xb9
#define GC2053_1L_DGAIN_H_ADDR 0xb1
#define GC2053_1L_DGAIN_L_ADDR 0xb2
#define GC2053_1L_VTS_H_ADDR 0x41 //(frame length)
#define GC2053_1L_VTS_L_ADDR 0x42
#define GC2053_1L_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
const GC2053_1L_MODE_S *pstMode;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_stGc2053_1l_mode;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = GC2053_1L_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
#if 0
pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0;
pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0;
pstAeSnsDft->bAERouteExValid = CVI_FALSE;
pstAeSnsDft->stAERouteAttr.u32TotalNum = 0;
pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0;
#endif
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = 3985*16;
pstAeSnsDft->u32MinAgain = 1024;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = 10240;
pstAeSnsDft->u32MinDgain = 1024;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] :
pstMode->stExp.u16Def;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp.u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp.u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
case WDR_MODE_2To1_LINE:
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX = 0;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_stGc2053_1l_mode.u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_stGc2053_1l_mode.f32MaxFps;
f32MinFps = g_stGc2053_1l_mode.f32MinFps;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > GC2053_1L_FULL_LINES_MAX) ? GC2053_1L_FULL_LINES_MAX : u32VMAX;
pstSnsRegsInfo->astI2cData[LINEAR_VTS_H].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_L].u32Data = (u32VMAX & 0xFF);
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_H].u32Data = ((u32IntTime[0] & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_L].u32Data = (u32IntTime[0] & 0xFF);
return CVI_SUCCESS;
}
static CVI_U32 regValTable[25][4] = {
{0x00, 0x00, 0x01, 0x00},
{0x00, 0x10, 0x01, 0x0c},
{0x00, 0x20, 0x01, 0x1b},
{0x00, 0x30, 0x01, 0x2c},
{0x00, 0x40, 0x01, 0x3f},
{0x00, 0x50, 0x02, 0x16},
{0x00, 0x60, 0x02, 0x35},
{0x00, 0x70, 0x03, 0x16},
{0x00, 0x80, 0x04, 0x02},
{0x00, 0x90, 0x04, 0x31},
{0x00, 0xa0, 0x05, 0x32},
{0x00, 0xb0, 0x06, 0x35},
{0x00, 0xc0, 0x08, 0x04},
{0x00, 0x5a, 0x09, 0x19},
{0x00, 0x83, 0x0b, 0x0f},
{0x00, 0x93, 0x0d, 0x12},
{0x00, 0x84, 0x10, 0x00},
{0x00, 0x94, 0x12, 0x3a},
{0x01, 0x2c, 0x1a, 0x02},
{0x01, 0x3c, 0x1b, 0x20},
{0x00, 0x8c, 0x20, 0x0f},
{0x00, 0x9c, 0x26, 0x07},
{0x02, 0x64, 0x36, 0x21},
{0x02, 0x74, 0x37, 0x3a},
{0x00, 0xc6, 0x3d, 0x02},
/*
{0x00, 0xdc, 0x3f, 0x3f},
{0x02, 0x85, 0x3f, 0x3f},
{0x02, 0x95, 0x3f, 0x3f},
{0x00, 0xce, 0x3f, 0x3f},
*/
};
static CVI_U32 gain_table[25] = {
64*16, 76*16, 90*16, 108*16, 127*16, 148*16, 180*16, 216*16, 255*16, 300*16,
361*16, 422*16, 504*16, 593*16, 722*16, 850*16, 1008*16, 1182*16, 1408*16, 1689*16,
2021*16, 2391*16, 2850*16, 3369*16, 3985*16,/* 4805*16, 5768*16, 6806*16, 7723*16,*/
};
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
int i, total;
CVI_U32 pregain;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
total = sizeof(gain_table) / sizeof(CVI_U32);
if (*pu32AgainLin >= gain_table[total - 1]) {
*pu32AgainLin = *pu32AgainDb = gain_table[total - 1];
return CVI_SUCCESS;
}
for (i = 1; i < total; i++) {
if (*pu32AgainLin < gain_table[i])
break;
}
i--;
// find the pregain
pregain = *pu32AgainLin * 64 / gain_table[i];
// set the Db as the AE algo gain, we need this to do gain update
*pu32AgainDb = *pu32AgainLin;
// set the Lin as the closest sensor gain for AE algo reference
*pu32AgainLin = pregain * gain_table[i] / 64;
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
CVI_U32 pregain;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
// find the pregain
pregain = *pu32DgainLin * 64 / 1024;
// set the Db as the AE algo gain, we need this to do gain update
*pu32DgainDb = *pu32DgainLin;
// set the Lin as the closest sensor gain for AE algo reference
*pu32DgainLin = pregain * 16;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32Again;
CVI_U32 u32Dgain;
int i, total;
total = sizeof(gain_table) / sizeof(CVI_U32);
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* only surpport linear mode */
u32Again = pu32Again[0];
/* To kepp the linearity. we assume AE algo adjusts the dgain only when the again reachs the maximum value */
if (u32Again < (3985*16)) {
for (i = 1; i < total; i++) {
if (*pu32Again < gain_table[i])
break;
}
i--;
// find the pregain
u32Dgain = u32Again * 64 / gain_table[i];
u32Again = i;
} else {
u32Again = total - 1;
// find the pregain
u32Dgain = pu32Dgain[0] * 64 / 1024;
}
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_H].u32Data = regValTable[u32Again][0];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_L].u32Data = regValTable[u32Again][1];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_H].u32Data = regValTable[u32Again][2];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_L].u32Data = regValTable[u32Again][3];
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 6);
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0x3F) << 2;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
{
CVI_U32 u32IntTimeMaxTmp = 0;
CVI_U32 u32RatioTmp = 0x40;
CVI_U32 u32ShortTimeMinLimit = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(au32Ratio);
CMOS_CHECK_POINTER(au32IntTimeMax);
CMOS_CHECK_POINTER(au32IntTimeMin);
CMOS_CHECK_POINTER(pu32LFMaxIntTime);
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
UNUSED(ViPipe);
u32ShortTimeMinLimit = (WDR_MODE_2To1_LINE == pstSnsState->enWDRMode) ? 8 : 8;
/*
* Long exp + Short exp < VTS - 4
* max l2s distance = FL - boundary - active_h - 4
* max sexp = max l2s distance - (L2S offset + 1) * 2
*/
u32IntTimeMaxTmp = ((pstSnsState->au32FL[0] - 4) * 0x40) / DIV_0_TO_1(au32Ratio[0] + 0x40);
u32IntTimeMaxTmp = (g_astGc2053_1l_State[ViPipe].u32Sexp_MAX < u32IntTimeMaxTmp) ?
g_astGc2053_1l_State[ViPipe].u32Sexp_MAX : u32IntTimeMaxTmp;
u32IntTimeMaxTmp = (!u32IntTimeMaxTmp) ? 1 : u32IntTimeMaxTmp;
syslog(LOG_DEBUG, "Max inttime0 = %u\n", u32IntTimeMaxTmp);
if (u32IntTimeMaxTmp >= u32ShortTimeMinLimit) {
if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
au32IntTimeMax[0] = u32IntTimeMaxTmp;
au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6;
au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6;
au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6;
au32IntTimeMin[0] = u32ShortTimeMinLimit;
au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6;
au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6;
au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6;
} else {
}
} else {
if (u16ManRatioEnable) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Manaul ExpRatio is too large!\n");
return CVI_FAILURE;
}
u32IntTimeMaxTmp = u32ShortTimeMinLimit;
if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
u32RatioTmp = 0xFFF;
au32IntTimeMax[0] = u32IntTimeMaxTmp;
au32IntTimeMax[1] = au32IntTimeMax[0] * u32RatioTmp >> 6;
} else {
}
au32IntTimeMin[0] = au32IntTimeMax[0];
au32IntTimeMin[1] = au32IntTimeMax[1];
au32IntTimeMin[2] = au32IntTimeMax[2];
au32IntTimeMin[3] = au32IntTimeMax[3];
}
return CVI_SUCCESS;
}
/* Only used in LINE_WDR mode */
static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr)
{
CMOS_CHECK_POINTER(pstAeFSWDRAttr);
genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode;
gu32MaxTimeGetCnt[ViPipe] = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
memcpy(pstDef->stNoiseCalibration.CalibrationCoef,
&g_stIspNoiseCalibratio, sizeof(ISP_CMOS_NOISE_CALIBRATION_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
UNUSED(ViPipe);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const GC2053_1L_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_stGc2053_1l_mode;
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsState->bSyncInit = CVI_FALSE;
switch (u8Mode) {
case WDR_MODE_NONE:
pstSnsState->u8ImgMode = GC2053_1L_MODE_1920X1080P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_stGc2053_1l_mode.u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_NONE\n");
break;
case WDR_MODE_2To1_LINE:
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_FAILURE;
}
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunGc2053_1l_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = gc2053_1l_i2c_addr;
pstI2c_data[i].u32AddrByteNum = gc2053_1l_addr_byte;
pstI2c_data[i].u32DataByteNum = gc2053_1l_data_byte;
}
pstI2c_data[LINEAR_EXP_H].u32RegAddr = GC2053_1L_EXP_H_ADDR;
pstI2c_data[LINEAR_EXP_L].u32RegAddr = GC2053_1L_EXP_L_ADDR;
pstI2c_data[LINEAR_AGAIN_H].u32RegAddr = GC2053_1L_AGAIN_H_ADDR;
pstI2c_data[LINEAR_AGAIN_L].u32RegAddr = GC2053_1L_AGAIN_L_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_H].u32RegAddr = GC2053_1L_COL_AGAIN_H_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_L].u32RegAddr = GC2053_1L_COL_AGAIN_L_ADDR;
pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = GC2053_1L_DGAIN_H_ADDR;
pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = GC2053_1L_DGAIN_L_ADDR;
pstI2c_data[LINEAR_VTS_H].u32RegAddr = GC2053_1L_VTS_H_ADDR;
pstI2c_data[LINEAR_VTS_L].u32RegAddr = GC2053_1L_VTS_L_ADDR;
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
if ((i >= LINEAR_AGAIN_H) && (i <= LINEAR_DGAIN_L))
gainsUpdate = 1;
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_L].bUpdate = CVI_TRUE;
}
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 30) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (GC2053_1L_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = GC2053_1L_MODE_1920X1080P30;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps);
return CVI_FAILURE;
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeGc2053_1l_MirrorFip[ViPipe] != eSnsMirrorFlip) {
gc2053_1l_mirror_flip(ViPipe, eSnsMirrorFlip);
g_aeGc2053_1l_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = GC2053_1L_MODE_1920X1080P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_stGc2053_1l_mode.u32VtsDef;
pstSnsState->au32FL[0] = g_stGc2053_1l_mode.u32VtsDef;
pstSnsState->au32FL[1] = g_stGc2053_1l_mode.u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_1L_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &gc2053_1l_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_stGc2053_1l_mode.stImg.stSnsSize.u32Width;
pstRxAttr->img_size.height = g_stGc2053_1l_mode.stImg.stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc2053_1l_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = gc2053_1l_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = gc2053_1l_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (GC2053_1L_I2C_ADDR_IS_VALID(s32I2cAddr))
gc2053_1l_i2c_addr = s32I2cAddr;
}
static CVI_S32 gc2053_1l_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunGc2053_1l_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC2053_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
GC2053_1L_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC2053_1L_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
GC2053_1L_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = GC2053_1L_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC2053_1L_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, GC2053_1L_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, GC2053_1L_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Gc2053_1l_GainMode[ViPipe] = pstInitAttr->enGainMode;
g_au16Gc2053_1l_L2SMode[ViPipe] = pstInitAttr->enL2SMode;
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return gc2053_1l_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsGc2053_1l_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = gc2053_1l_standby,
.pfnRestart = gc2053_1l_restart,
.pfnWriteReg = gc2053_1l_write_register,
.pfnReadReg = gc2053_1l_read_register,
.pfnSetBusInfo = gc2053_1l_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = sensor_probe,
};

88
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#ifndef __GC2053_1L_CMOS_EX_H_
#define __GC2053_1L_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#ifndef UNUSED
#define UNUSED(x) ((void)(x))
#endif
enum gc2053_1l_linear_regs_e {
LINEAR_EXP_H = 0,//03
LINEAR_EXP_L, //04
LINEAR_AGAIN_H, //b4
LINEAR_AGAIN_L, //b3
LINEAR_COL_AGAIN_H, //b8
LINEAR_COL_AGAIN_L, //b9
LINEAR_DGAIN_H, //b1
LINEAR_DGAIN_L, //b2
LINEAR_VTS_H, //0x41 (frame length)
LINEAR_VTS_L,//0x42
LINEAR_REGS_NUM
};
typedef enum _GC2053_1L_MODE_E {
GC2053_1L_MODE_1920X1080P30 = 0,
GC2053_1L_MODE_NUM
} GC2053_1L_SLAVE_MODE_E;
typedef struct _GC2053_1L_STATE_S {
CVI_U32 u32Sexp_MAX;
} GC2053_1L_STATE_S;
typedef struct _GC2053_1L_MODE_S {
ISP_WDR_SIZE_S stImg;
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp;
SNS_ATTR_LARGE_S stAgain;
SNS_ATTR_LARGE_S stDgain;
char name[64];
} GC2053_1L_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc2053_1l[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc2053_1l_BusInfo[];
extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2053_1l_MirrorFip[VI_MAX_PIPE_NUM];
extern CVI_U8 gc2053_1l_i2c_addr;
extern const CVI_U32 gc2053_1l_addr_byte;
extern const CVI_U32 gc2053_1l_data_byte;
extern void gc2053_1l_init(VI_PIPE ViPipe);
extern void gc2053_1l_exit(VI_PIPE ViPipe);
extern void gc2053_1l_standby(VI_PIPE ViPipe);
extern void gc2053_1l_restart(VI_PIPE ViPipe);
extern int gc2053_1l_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc2053_1l_read_register(VI_PIPE ViPipe, int addr);
extern void gc2053_1l_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int gc2053_1l_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2053_1L_CMOS_EX_H_ */

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#ifndef __GC2053_1L_CMOS_PARAM_H_
#define __GC2053_1L_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2053_1l_cmos_ex.h"
static const GC2053_1L_MODE_S g_stGc2053_1l_mode = {
.name = "1920X1080P30",
.stImg = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
.f32MaxFps = 30,
.f32MinFps = 2.07, /* 1125 * 30 / 0x3FFF */
.u32HtsDef = 2200,
.u32VtsDef = 1125,
.stExp = {
.u16Min = 1,
.u16Max = 0x3fff,
.u16Def = 0x2000,
.u16Step = 1,
},
.stAgain = {
.u32Min = 64,
.u32Max = 62977,
.u32Def = 64,
.u32Step = 1,
},
.stDgain = {
.u32Min = 64*16,
.u32Max = 7073*16,
.u32Def = 581*16,
.u32Step = 10*16,
},
};
static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = {
{ //iso 100
{0.05999477580189704895, 0.13019448518753051758}, //B: slope, intercept
{0.06732148677110671997, -1.36387133598327636719}, //Gb: slope, intercept
{0.06651904433965682983, -1.10093510150909423828}, //Gr: slope, intercept
{0.06406146287918090820, 0.33316791057586669922}, //R: slope, intercept
},
{ //iso 200
{0.06256803125143051147, 4.54908418655395507813}, //B: slope, intercept
{0.06911934912204742432, 2.79023528099060058594}, //Gb: slope, intercept
{0.06846688687801361084, 2.88726186752319335938}, //Gr: slope, intercept
{0.06652788817882537842, 4.40276956558227539063}, //R: slope, intercept
},
{ //iso 400
{0.06841833144426345825, 11.72280883789062500000}, //B: slope, intercept
{0.07257881015539169312, 10.86985683441162109375}, //Gb: slope, intercept
{0.07174283266067504883, 11.20646286010742187500}, //Gr: slope, intercept
{0.07294593751430511475, 11.17350578308105468750}, //R: slope, intercept
},
{ //iso 800
{0.07805790752172470093, 20.62956619262695312500}, //B: slope, intercept
{0.07694032043218612671, 22.20356750488281250000}, //Gb: slope, intercept
{0.07647507637739181519, 22.50957298278808593750}, //Gr: slope, intercept
{0.08402533829212188721, 19.11953735351562500000}, //R: slope, intercept
},
{ //iso 1600
{0.09468275308609008789, 34.07563018798828125000}, //B: slope, intercept
{0.08710632473230361938, 39.15500259399414062500}, //Gb: slope, intercept
{0.08662072569131851196, 39.37175750732421875000}, //Gr: slope, intercept
{0.10222808271646499634, 31.34789276123046875000}, //R: slope, intercept
},
{ //iso 3200
{0.12651191651821136475, 49.56183242797851562500}, //B: slope, intercept
{0.10816962271928787231, 59.42719650268554687500}, //Gb: slope, intercept
{0.10751257836818695068, 59.90552902221679687500}, //Gr: slope, intercept
{0.13802853226661682129, 45.09576034545898437500}, //R: slope, intercept
},
{ //iso 6400
{0.17422541975975036621, 70.04063415527343750000}, //B: slope, intercept
{0.14234761893749237061, 85.51583862304687500000}, //Gb: slope, intercept
{0.14159946143627166748, 86.23278045654296875000}, //Gr: slope, intercept
{0.19450971484184265137, 62.65447235107421875000}, //R: slope, intercept
},
{ //iso 12800
{0.24947367608547210693, 108.30633544921875000000}, //B: slope, intercept
{0.19751225411891937256, 130.88159179687500000000}, //Gb: slope, intercept
{0.19614629447460174561, 132.49082946777343750000}, //Gr: slope, intercept
{0.28106108307838439941, 97.15969085693359375000}, //R: slope, intercept
},
{ //iso 25600
{0.35420843958854675293, 137.06745910644531250000}, //B: slope, intercept
{0.27778801321983337402, 168.72366333007812500000}, //Gb: slope, intercept
{0.27540388703346252441, 170.54939270019531250000}, //Gr: slope, intercept
{0.39949953556060791016, 123.29409790039062500000}, //R: slope, intercept
},
{ //iso 51200
{0.45704349875450134277, 179.20147705078125000000}, //B: slope, intercept
{0.32142028212547302246, 246.71363830566406250000}, //Gb: slope, intercept
{0.31958609819412231445, 246.82630920410156250000}, //Gr: slope, intercept
{0.51058447360992431641, 161.86299133300781250000}, //R: slope, intercept
},
{ //iso 102400
{0.61760461330413818359, 222.90534973144531250000}, //B: slope, intercept
{0.42568457126617431641, 319.29257202148437500000}, //Gb: slope, intercept
{0.41750904917716979980, 324.93432617187500000000}, //Gr: slope, intercept
{0.67956107854843139648, 203.78948974609375000000}, //R: slope, intercept
},
{ //iso 204800
{0.63289469480514526367, 216.99952697753906250000}, //B: slope, intercept
{0.44890350103378295898, 306.80810546875000000000}, //Gb: slope, intercept
{0.44229975342750549316, 310.13763427734375000000}, //Gr: slope, intercept
{0.69596910476684570313, 196.70443725585937500000}, //R: slope, intercept
},
{ //iso 409600
{0.71106964349746704102, 187.98352050781250000000}, //B: slope, intercept
{0.55859673023223876953, 246.22378540039062500000}, //Gb: slope, intercept
{0.55284017324447631836, 249.86463928222656250000}, //Gr: slope, intercept
{0.77318203449249267578, 168.85035705566406250000}, //R: slope, intercept
},
{ //iso 819200
{0.70888006687164306641, 188.44216918945312500000}, //B: slope, intercept
{0.56110274791717529297, 245.46603393554687500000}, //Gb: slope, intercept
{0.55100852251052856445, 250.33049011230468750000}, //Gr: slope, intercept
{0.76897650957107543945, 169.31251525878906250000}, //R: slope, intercept
},
{ //iso 1638400
{0.70520979166030883789, 188.93899536132812500000}, //B: slope, intercept
{0.56178557872772216797, 245.21235656738281250000}, //Gb: slope, intercept
{0.55338454246520996094, 249.57423400878906250000}, //Gr: slope, intercept
{0.77306479215621948242, 168.86497497558593750000}, //R: slope, intercept
},
{ //iso 3276800
{0.71255809068679809570, 187.86839294433593750000}, //B: slope, intercept
{0.56056070327758789063, 245.57748413085937500000}, //Gb: slope, intercept
{0.55358195304870605469, 249.62020874023437500000}, //Gr: slope, intercept
{0.77431541681289672852, 168.74313354492187500000}, //R: slope, intercept
},
} };
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {257, 257, 257, 257, 0, 0, 0
#ifdef ARCH_CV182X
, 0, 1093, 1093, 1093, 1093
#endif
},
.stAuto = {
{257, 257, 257, 257, 259, 259, 260, 267, 278, 298, 366, 383, 366, 373, 372, 372 },
{257, 257, 257, 257, 258, 259, 261, 266, 274, 297, 379, 377, 372, 365, 373, 374 },
{257, 257, 257, 257, 258, 259, 261, 266, 275, 296, 376, 388, 366, 374, 376, 372 },
{257, 257, 257, 257, 258, 259, 260, 264, 274, 294, 362, 363, 365, 361, 353, 367 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1093, 1093, 1093, 1093, 1093, 1093, 1093, 1095,
1099, 1104, 1125, 1130, 1125, 1127, 1126, 1126},
{1093, 1093, 1093, 1093, 1093, 1093, 1094, 1095,
1097, 1104, 1128, 1128, 1126, 1124, 1127, 1127},
{1093, 1093, 1093, 1093, 1093, 1093, 1094, 1095,
1098, 1104, 1128, 1131, 1125, 1127, 1128, 1126},
{1093, 1093, 1093, 1093, 1093, 1093, 1093, 1095,
1097, 1103, 1123, 1124, 1124, 1123, 1121, 1125},
#endif
},
},
};
struct combo_dev_attr_s gc2053_1l_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {3, 4, -1, -1, -1},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
.dphy = {
.enable = 1,
.hs_settle = 31,
},
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.devno = 1,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2053_1L_CMOS_PARAM_H_ */

398
middleware/v2/component/isp/sensor/cv180x/gcore_gc2053_1L/gc2053_1l_sensor_ctl.c Normal file
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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2053_1l_cmos_ex.h"
#define GC2053_1L_CHIP_ID_ADDR_H 0xf0
#define GC2053_1L_CHIP_ID_ADDR_L 0xf1
#define GC2053_1L_CHIP_ID 0x2053
static void gc2053_1l_linear_1080p30_init(VI_PIPE ViPipe);
CVI_U8 gc2053_1l_i2c_addr = 0x3f;//0x7e
const CVI_U32 gc2053_1l_addr_byte = 1;
const CVI_U32 gc2053_1l_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc2053_1l_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc2053_1l_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc2053_1l_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc2053_1l_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc2053_1l_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (gc2053_1l_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, gc2053_1l_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, gc2053_1l_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (gc2053_1l_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int gc2053_1l_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc2053_1l_addr_byte == 1) {
buf[idx] = addr & 0xff;
idx++;
}
if (gc2053_1l_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc2053_1l_addr_byte + gc2053_1l_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
ret = read(g_fd[ViPipe], buf, gc2053_1l_addr_byte + gc2053_1l_data_byte);
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void gc2053_1l_standby(VI_PIPE ViPipe)
{
gc2053_1l_write_register(ViPipe, 0x3e, 0x00);
gc2053_1l_write_register(ViPipe, 0xf7, 0x00);
gc2053_1l_write_register(ViPipe, 0xfc, 0x01);
gc2053_1l_write_register(ViPipe, 0xf9, 0x83);
printf("gc2053_1l_standby\n");
}
void gc2053_1l_restart(VI_PIPE ViPipe)
{
gc2053_1l_write_register(ViPipe, 0xf9, 0x82);
delay_ms(2);
gc2053_1l_write_register(ViPipe, 0xf7, 0x01);
gc2053_1l_write_register(ViPipe, 0xfc, 0x8e);
gc2053_1l_write_register(ViPipe, 0x3e, 0x90);
printf("gc2053_1l_restart\n");
}
void gc2053_1l_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastGc2053_1l[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
gc2053_1l_write_register(ViPipe,
g_pastGc2053_1l[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastGc2053_1l[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
void gc2053_1l_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 value = 0;
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
value = 0x01;
break;
case ISP_SNS_FLIP:
value = 0x02;
break;
case ISP_SNS_MIRROR_FLIP:
value = 0x03;
break;
default:
return;
}
gc2053_1l_write_register(ViPipe, 0xfe, 0x00);
gc2053_1l_write_register(ViPipe, 0x17, value);
}
int gc2053_1l_probe(VI_PIPE ViPipe)
{
int nVal;
int nVal2;
usleep(50);
if (gc2053_1l_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = gc2053_1l_read_register(ViPipe, GC2053_1L_CHIP_ID_ADDR_H);
nVal2 = gc2053_1l_read_register(ViPipe, GC2053_1L_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC2053_1L_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void gc2053_1l_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode = g_pastGc2053_1l[ViPipe]->enWDRMode;
gc2053_1l_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n");
} else {
gc2053_1l_linear_1080p30_init(ViPipe);
}
g_pastGc2053_1l[ViPipe]->bInit = CVI_TRUE;
}
void gc2053_1l_exit(VI_PIPE ViPipe)
{
gc2053_1l_i2c_exit(ViPipe);
}
static void gc2053_1l_linear_1080p30_init(VI_PIPE ViPipe)
{
/****system****/
gc2053_1l_write_register(ViPipe, 0xfe, 0x80);
gc2053_1l_write_register(ViPipe, 0xfe, 0x80);
gc2053_1l_write_register(ViPipe, 0xfe, 0x80);
gc2053_1l_write_register(ViPipe, 0xfe, 0x00);
gc2053_1l_write_register(ViPipe, 0xf2, 0x00);
gc2053_1l_write_register(ViPipe, 0xf3, 0x00);
gc2053_1l_write_register(ViPipe, 0xf4, 0x36);
gc2053_1l_write_register(ViPipe, 0xf5, 0xc0);
gc2053_1l_write_register(ViPipe, 0xf6, 0x82);
gc2053_1l_write_register(ViPipe, 0xf7, 0x01);
gc2053_1l_write_register(ViPipe, 0xf8, 0x20);
gc2053_1l_write_register(ViPipe, 0xf9, 0x82);
gc2053_1l_write_register(ViPipe, 0xfc, 0x8e);
/****CISCTL & ANALOG****/
gc2053_1l_write_register(ViPipe, 0xfe, 0x00);
gc2053_1l_write_register(ViPipe, 0x87, 0x18);
gc2053_1l_write_register(ViPipe, 0xee, 0x30);
gc2053_1l_write_register(ViPipe, 0xd0, 0xb7);
gc2053_1l_write_register(ViPipe, 0x03, 0x04);
gc2053_1l_write_register(ViPipe, 0x04, 0x10);
gc2053_1l_write_register(ViPipe, 0x05, 0x05);//05
gc2053_1l_write_register(ViPipe, 0x06, 0x00);//60//[11:0]hb
gc2053_1l_write_register(ViPipe, 0x07, 0x00);
gc2053_1l_write_register(ViPipe, 0x08, 0x19);
gc2053_1l_write_register(ViPipe, 0x09, 0x00);
gc2053_1l_write_register(ViPipe, 0x0a, 0x02); //cisctl row start
gc2053_1l_write_register(ViPipe, 0x0b, 0x00);
gc2053_1l_write_register(ViPipe, 0x0c, 0x02); //cisctl col start
gc2053_1l_write_register(ViPipe, 0x0d, 0x04);
gc2053_1l_write_register(ViPipe, 0x0e, 0x40);
gc2053_1l_write_register(ViPipe, 0x12, 0xe2);
gc2053_1l_write_register(ViPipe, 0x13, 0x16);
gc2053_1l_write_register(ViPipe, 0x19, 0x0a);
gc2053_1l_write_register(ViPipe, 0x21, 0x1c);
gc2053_1l_write_register(ViPipe, 0x28, 0x0a);
gc2053_1l_write_register(ViPipe, 0x29, 0x24);
gc2053_1l_write_register(ViPipe, 0x2b, 0x04);
gc2053_1l_write_register(ViPipe, 0x32, 0xf8);
gc2053_1l_write_register(ViPipe, 0x37, 0x03);
gc2053_1l_write_register(ViPipe, 0x39, 0x15);
gc2053_1l_write_register(ViPipe, 0x41, 0x04);
gc2053_1l_write_register(ViPipe, 0x42, 0x65);
gc2053_1l_write_register(ViPipe, 0x43, 0x07);
gc2053_1l_write_register(ViPipe, 0x44, 0x40);
gc2053_1l_write_register(ViPipe, 0x46, 0x0b);
gc2053_1l_write_register(ViPipe, 0x4b, 0x20);
gc2053_1l_write_register(ViPipe, 0x4e, 0x08);
gc2053_1l_write_register(ViPipe, 0x55, 0x20);
gc2053_1l_write_register(ViPipe, 0x66, 0x05);
gc2053_1l_write_register(ViPipe, 0x67, 0x05);
gc2053_1l_write_register(ViPipe, 0x77, 0x01);
gc2053_1l_write_register(ViPipe, 0x78, 0x00);
gc2053_1l_write_register(ViPipe, 0x7c, 0x93);
gc2053_1l_write_register(ViPipe, 0x8c, 0x12);
gc2053_1l_write_register(ViPipe, 0x8d, 0x92);
gc2053_1l_write_register(ViPipe, 0x90, 0x00);
gc2053_1l_write_register(ViPipe, 0x9d, 0x10);
gc2053_1l_write_register(ViPipe, 0xce, 0x7c);
gc2053_1l_write_register(ViPipe, 0xd2, 0x41);
gc2053_1l_write_register(ViPipe, 0xd3, 0xdc);
gc2053_1l_write_register(ViPipe, 0xda, 0x05);
gc2053_1l_write_register(ViPipe, 0xdb, 0x00);
gc2053_1l_write_register(ViPipe, 0xe6, 0x50);
/*gain*/
gc2053_1l_write_register(ViPipe, 0xb6, 0xc0);
gc2053_1l_write_register(ViPipe, 0xb0, 0x70);
gc2053_1l_write_register(ViPipe, 0xb1, 0x01);
gc2053_1l_write_register(ViPipe, 0xb2, 0x00);
gc2053_1l_write_register(ViPipe, 0xb3, 0x00);
gc2053_1l_write_register(ViPipe, 0xb4, 0x00);
gc2053_1l_write_register(ViPipe, 0xb8, 0x01);
gc2053_1l_write_register(ViPipe, 0xb9, 0x00);
/*blk*/
gc2053_1l_write_register(ViPipe, 0x26, 0x30);
gc2053_1l_write_register(ViPipe, 0xfe, 0x01);
gc2053_1l_write_register(ViPipe, 0x40, 0x23);
gc2053_1l_write_register(ViPipe, 0x55, 0x07);
gc2053_1l_write_register(ViPipe, 0x60, 0x40); //[7:0]WB_offset
gc2053_1l_write_register(ViPipe, 0xfe, 0x04);
gc2053_1l_write_register(ViPipe, 0x14, 0x78);
gc2053_1l_write_register(ViPipe, 0x15, 0x78);
gc2053_1l_write_register(ViPipe, 0x16, 0x78);
gc2053_1l_write_register(ViPipe, 0x17, 0x78);
/*window*/
gc2053_1l_write_register(ViPipe, 0xfe, 0x01);
gc2053_1l_write_register(ViPipe, 0x92, 0x00); //win y1
gc2053_1l_write_register(ViPipe, 0x94, 0x03); //win x1
gc2053_1l_write_register(ViPipe, 0x95, 0x04);
gc2053_1l_write_register(ViPipe, 0x96, 0x38); //[10:0]out_height
gc2053_1l_write_register(ViPipe, 0x97, 0x07);
gc2053_1l_write_register(ViPipe, 0x98, 0x80); //[11:0]out_width
/*ISP*/
gc2053_1l_write_register(ViPipe, 0xfe, 0x01);
gc2053_1l_write_register(ViPipe, 0x01, 0x05);
gc2053_1l_write_register(ViPipe, 0x02, 0x89);
gc2053_1l_write_register(ViPipe, 0x04, 0x01); //[0]DD_en
gc2053_1l_write_register(ViPipe, 0x07, 0xa6);
gc2053_1l_write_register(ViPipe, 0x08, 0xa9);
gc2053_1l_write_register(ViPipe, 0x09, 0xa8);
gc2053_1l_write_register(ViPipe, 0x0a, 0xa7);
gc2053_1l_write_register(ViPipe, 0x0b, 0xff);
gc2053_1l_write_register(ViPipe, 0x0c, 0xff);
gc2053_1l_write_register(ViPipe, 0x0f, 0x00);
gc2053_1l_write_register(ViPipe, 0x50, 0x1c);
gc2053_1l_write_register(ViPipe, 0x89, 0x03);
gc2053_1l_write_register(ViPipe, 0xfe, 0x04);
gc2053_1l_write_register(ViPipe, 0x28, 0x86);//84
gc2053_1l_write_register(ViPipe, 0x29, 0x86);//84
gc2053_1l_write_register(ViPipe, 0x2a, 0x86);//84
gc2053_1l_write_register(ViPipe, 0x2b, 0x68);//84
gc2053_1l_write_register(ViPipe, 0x2c, 0x68);//84
gc2053_1l_write_register(ViPipe, 0x2d, 0x68);//84
gc2053_1l_write_register(ViPipe, 0x2e, 0x68);//83
gc2053_1l_write_register(ViPipe, 0x2f, 0x68);//82
gc2053_1l_write_register(ViPipe, 0x30, 0x4f);//82
gc2053_1l_write_register(ViPipe, 0x31, 0x68);//82
gc2053_1l_write_register(ViPipe, 0x32, 0x67);//82
gc2053_1l_write_register(ViPipe, 0x33, 0x66);//82
gc2053_1l_write_register(ViPipe, 0x34, 0x66);//82
gc2053_1l_write_register(ViPipe, 0x35, 0x66);//82
gc2053_1l_write_register(ViPipe, 0x36, 0x66);//64
gc2053_1l_write_register(ViPipe, 0x37, 0x66);//68
gc2053_1l_write_register(ViPipe, 0x38, 0x62);
gc2053_1l_write_register(ViPipe, 0x39, 0x62);
gc2053_1l_write_register(ViPipe, 0x3a, 0x62);
gc2053_1l_write_register(ViPipe, 0x3b, 0x62);
gc2053_1l_write_register(ViPipe, 0x3c, 0x62);
gc2053_1l_write_register(ViPipe, 0x3d, 0x62);
gc2053_1l_write_register(ViPipe, 0x3e, 0x62);
gc2053_1l_write_register(ViPipe, 0x3f, 0x62);
/****DVP & MIPI****/
gc2053_1l_write_register(ViPipe, 0xfe, 0x01);
gc2053_1l_write_register(ViPipe, 0x9a, 0x06);
gc2053_1l_write_register(ViPipe, 0xfe, 0x00);
gc2053_1l_write_register(ViPipe, 0x7b, 0x2a);
gc2053_1l_write_register(ViPipe, 0x23, 0x2d);
gc2053_1l_write_register(ViPipe, 0xfe, 0x03);
gc2053_1l_write_register(ViPipe, 0x01, 0x27);
gc2053_1l_write_register(ViPipe, 0x02, 0x56);
gc2053_1l_write_register(ViPipe, 0x03, 0xb6);
gc2053_1l_write_register(ViPipe, 0x12, 0x80);
gc2053_1l_write_register(ViPipe, 0x13, 0x07);
gc2053_1l_write_register(ViPipe, 0x15, 0x12);
gc2053_1l_write_register(ViPipe, 0x29, 0x16);// hs_prepare
gc2053_1l_write_register(ViPipe, 0x36, 0x03);// clk lp drv
gc2053_1l_write_register(ViPipe, 0x37, 0x0f);// clk lp drv
gc2053_1l_write_register(ViPipe, 0xfe, 0x00);
gc2053_1l_write_register(ViPipe, 0x3e, 0x90);
gc2053_1l_default_reg_init(ViPipe);
printf("ViPipe:%d,===GC2053_1L 1080P 30fps 10bit LINE Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/gcore_gc2053_slave/Makefile Normal file
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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc2053_slave.a
TARGET_SO = $(MW_LIB)/libsns_gc2053_slave.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

883
middleware/v2/component/isp/sensor/cv180x/gcore_gc2053_slave/gc2053_slave_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "gc2053_slave_cmos_ex.h"
#include "gc2053_slave_cmos_param.h"
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define GC2053_SLAVE_ID 2053
#define GC2053_SLAVE_I2C_ADDR_1 0x3f
#define GC2053_SLAVE_I2C_ADDR_2 0x37
#define GC2053_SLAVE_I2C_ADDR_IS_VALID(addr) ((addr) == GC2053_SLAVE_I2C_ADDR_1 || (addr) == GC2053_SLAVE_I2C_ADDR_2)
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_STATE_S *g_pastGc2053_Slave[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define GC2053_SLAVE_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc2053_Slave[dev])
#define GC2053_SLAVE_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc2053_Slave[dev] = pstCtx)
#define GC2053_SLAVE_SENSOR_RESET_CTX(dev) (g_pastGc2053_Slave[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunGc2053_Slave_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 3},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
GC2053_SLAVE_STATE_S g_astGc2053_Slave_State[VI_MAX_PIPE_NUM] = { {0} };
ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2053_Slave_MirrorFip[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc2053_Slave_GainMode[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc2053_Slave_L2SMode[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
****************************************************************************/
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Gc2053_Slave Lines Range*****/
#define GC2053_SLAVE_FULL_LINES_MAX (0x3fff)
/*****Gc2053_Slave Register Address*****/
#define GC2053_SLAVE_EXP_H_ADDR 0x03
#define GC2053_SLAVE_EXP_L_ADDR 0x04
#define GC2053_SLAVE_AGAIN_H_ADDR 0xb4
#define GC2053_SLAVE_AGAIN_L_ADDR 0xb3
#define GC2053_SLAVE_COL_AGAIN_H_ADDR 0xb8
#define GC2053_SLAVE_COL_AGAIN_L_ADDR 0xb9
#define GC2053_SLAVE_DGAIN_H_ADDR 0xb1
#define GC2053_SLAVE_DGAIN_L_ADDR 0xb2
#define GC2053_SLAVE_VTS_H_ADDR 0x41 //(frame length)
#define GC2053_SLAVE_VTS_L_ADDR 0x42
#define GC2053_SLAVE_RES_IS_1080P(w, h) ((w) == 1920 && (h) == 1080)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
const GC2053_SLAVE_MODE_S *pstMode;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_stGc2053_Slave_mode;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = GC2053_SLAVE_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
#if 0
pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0;
pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0;
pstAeSnsDft->bAERouteExValid = CVI_FALSE;
pstAeSnsDft->stAERouteAttr.u32TotalNum = 0;
pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0;
#endif
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = 3985*16;
pstAeSnsDft->u32MinAgain = 1024;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = 10240;
pstAeSnsDft->u32MinDgain = 1024;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] :
pstMode->stExp.u16Def;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp.u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp.u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
case WDR_MODE_2To1_LINE:
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX = 0;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_stGc2053_Slave_mode.u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_stGc2053_Slave_mode.f32MaxFps;
f32MinFps = g_stGc2053_Slave_mode.f32MinFps;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > GC2053_SLAVE_FULL_LINES_MAX) ? GC2053_SLAVE_FULL_LINES_MAX : u32VMAX;
pstSnsRegsInfo->astI2cData[LINEAR_VTS_H].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_L].u32Data = (u32VMAX & 0xFF);
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_H].u32Data = ((u32IntTime[0] & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_L].u32Data = (u32IntTime[0] & 0xFF);
return CVI_SUCCESS;
}
static CVI_U32 regValTable[25][4] = {
{0x00, 0x00, 0x01, 0x00},
{0x00, 0x10, 0x01, 0x0c},
{0x00, 0x20, 0x01, 0x1b},
{0x00, 0x30, 0x01, 0x2c},
{0x00, 0x40, 0x01, 0x3f},
{0x00, 0x50, 0x02, 0x16},
{0x00, 0x60, 0x02, 0x35},
{0x00, 0x70, 0x03, 0x16},
{0x00, 0x80, 0x04, 0x02},
{0x00, 0x90, 0x04, 0x31},
{0x00, 0xa0, 0x05, 0x32},
{0x00, 0xb0, 0x06, 0x35},
{0x00, 0xc0, 0x08, 0x04},
{0x00, 0x5a, 0x09, 0x19},
{0x00, 0x83, 0x0b, 0x0f},
{0x00, 0x93, 0x0d, 0x12},
{0x00, 0x84, 0x10, 0x00},
{0x00, 0x94, 0x12, 0x3a},
{0x01, 0x2c, 0x1a, 0x02},
{0x01, 0x3c, 0x1b, 0x20},
{0x00, 0x8c, 0x20, 0x0f},
{0x00, 0x9c, 0x26, 0x07},
{0x02, 0x64, 0x36, 0x21},
{0x02, 0x74, 0x37, 0x3a},
{0x00, 0xc6, 0x3d, 0x02},
};
static CVI_U32 gain_table[25] = {
64*16, 76*16, 90*16, 108*16, 127*16, 148*16, 180*16, 216*16, 255*16, 300*16,
361*16, 422*16, 504*16, 593*16, 722*16, 850*16, 1008*16, 1182*16, 1408*16, 1689*16,
2021*16, 2391*16, 2850*16, 3369*16, 3985*16,/* 4805*16, 5768*16, 6806*16, 7723*16,*/
};
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
int i, total;
CVI_U32 pregain;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
total = sizeof(gain_table) / sizeof(CVI_U32);
if (*pu32AgainLin >= gain_table[total - 1]) {
*pu32AgainLin = *pu32AgainDb = gain_table[total - 1];
return CVI_SUCCESS;
}
for (i = 1; i < total; i++) {
if (*pu32AgainLin < gain_table[i])
break;
}
i--;
// find the pregain
pregain = *pu32AgainLin * 64 / gain_table[i];
// set the Db as the AE algo gain, we need this to do gain update
*pu32AgainDb = *pu32AgainLin;
// set the Lin as the closest sensor gain for AE algo reference
*pu32AgainLin = pregain * gain_table[i] / 64;
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
CVI_U32 pregain;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
// find the pregain
pregain = *pu32DgainLin * 64 / 1024;
// set the Db as the AE algo gain, we need this to do gain update
*pu32DgainDb = *pu32DgainLin;
// set the Lin as the closest sensor gain for AE algo reference
*pu32DgainLin = pregain * 16;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32Again;
CVI_U32 u32Dgain;
int i, total;
total = sizeof(gain_table) / sizeof(CVI_U32);
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* only surpport linear mode */
u32Again = pu32Again[0];
/* To kepp the linearity. we assume AE algo adjusts the dgain only when the again reachs the maximum value */
if (u32Again < (3985*16)) {
for (i = 1; i < total; i++) {
if (*pu32Again < gain_table[i])
break;
}
i--;
// find the pregain
u32Dgain = u32Again * 64 / gain_table[i];
u32Again = i;
} else {
u32Again = total - 1;
// find the pregain
u32Dgain = pu32Dgain[0] * 64 / 1024;
}
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_H].u32Data = regValTable[u32Again][0];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_L].u32Data = regValTable[u32Again][1];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_H].u32Data = regValTable[u32Again][2];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_L].u32Data = regValTable[u32Again][3];
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 6);
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0x3F) << 2;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
//pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
//pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
memcpy(pstDef->stNoiseCalibration.CalibrationCoef,
&g_stIspNoiseCalibratio, sizeof(ISP_CMOS_NOISE_CALIBRATION_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
UNUSED(ViPipe);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const GC2053_SLAVE_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_stGc2053_Slave_mode;
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsState->bSyncInit = CVI_FALSE;
switch (u8Mode) {
case WDR_MODE_NONE:
pstSnsState->u8ImgMode = GC2053_SLAVE_MODE_1920X1080P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_stGc2053_Slave_mode.u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_NONE\n");
break;
case WDR_MODE_2To1_LINE:
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_FAILURE;
}
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunGc2053_Slave_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = gc2053_slave_i2c_addr;
pstI2c_data[i].u32AddrByteNum = gc2053_slave_addr_byte;
pstI2c_data[i].u32DataByteNum = gc2053_slave_data_byte;
}
pstI2c_data[LINEAR_EXP_H].u32RegAddr = GC2053_SLAVE_EXP_H_ADDR;
pstI2c_data[LINEAR_EXP_L].u32RegAddr = GC2053_SLAVE_EXP_L_ADDR;
pstI2c_data[LINEAR_AGAIN_H].u32RegAddr = GC2053_SLAVE_AGAIN_H_ADDR;
pstI2c_data[LINEAR_AGAIN_L].u32RegAddr = GC2053_SLAVE_AGAIN_L_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_H].u32RegAddr = GC2053_SLAVE_COL_AGAIN_H_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_L].u32RegAddr = GC2053_SLAVE_COL_AGAIN_L_ADDR;
pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = GC2053_SLAVE_DGAIN_H_ADDR;
pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = GC2053_SLAVE_DGAIN_L_ADDR;
pstI2c_data[LINEAR_VTS_H].u32RegAddr = GC2053_SLAVE_VTS_H_ADDR;
pstI2c_data[LINEAR_VTS_L].u32RegAddr = GC2053_SLAVE_VTS_L_ADDR;
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
if ((i >= LINEAR_AGAIN_H) && (i <= LINEAR_DGAIN_L))
gainsUpdate = 1;
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_L].bUpdate = CVI_TRUE;
}
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 30) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (GC2053_SLAVE_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = GC2053_SLAVE_MODE_1920X1080P30;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps);
return CVI_FAILURE;
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeGc2053_Slave_MirrorFip[ViPipe] != eSnsMirrorFlip) {
gc2053_slave_mirror_flip(ViPipe, eSnsMirrorFlip);
g_aeGc2053_Slave_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = GC2053_SLAVE_MODE_1920X1080P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_stGc2053_Slave_mode.u32VtsDef;
pstSnsState->au32FL[0] = g_stGc2053_Slave_mode.u32VtsDef;
pstSnsState->au32FL[1] = g_stGc2053_Slave_mode.u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &gc2053_slave_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_stGc2053_Slave_mode.stImg.stSnsSize.u32Width;
pstRxAttr->img_size.height = g_stGc2053_Slave_mode.stImg.stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc2053_slave_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = gc2053_slave_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = gc2053_slave_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (GC2053_SLAVE_I2C_ADDR_IS_VALID(s32I2cAddr))
gc2053_slave_i2c_addr = s32I2cAddr;
}
static CVI_S32 gc2053_slave_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunGc2053_Slave_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
GC2053_SLAVE_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC2053_SLAVE_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
GC2053_SLAVE_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = GC2053_SLAVE_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC2053_SLAVE_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, GC2053_SLAVE_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, GC2053_SLAVE_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Gc2053_Slave_GainMode[ViPipe] = pstInitAttr->enGainMode;
g_au16Gc2053_Slave_L2SMode[ViPipe] = pstInitAttr->enL2SMode;
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return gc2053_slave_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsGc2053_Slave_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = gc2053_slave_standby,
.pfnRestart = gc2053_slave_restart,
.pfnWriteReg = gc2053_slave_write_register,
.pfnReadReg = gc2053_slave_read_register,
.pfnSetBusInfo = gc2053_slave_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = sensor_probe,
};

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middleware/v2/component/isp/sensor/cv180x/gcore_gc2053_slave/gc2053_slave_cmos_ex.h Normal file
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#ifndef __GC2053_SLAVE_CMOS_EX_H_
#define __GC2053_SLAVE_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#ifndef UNUSED
#define UNUSED(x) ((void)(x))
#endif
enum gc2053_slave_linear_regs_e {
LINEAR_EXP_H = 0,//03
LINEAR_EXP_L, //04
LINEAR_AGAIN_H, //b4
LINEAR_AGAIN_L, //b3
LINEAR_COL_AGAIN_H, //b8
LINEAR_COL_AGAIN_L, //b9
LINEAR_DGAIN_H, //b1
LINEAR_DGAIN_L, //b2
LINEAR_VTS_H, //0x41 (frame length)
LINEAR_VTS_L,//0x42
LINEAR_REGS_NUM
};
typedef enum _GC2053_SLAVE_MODE_E {
GC2053_SLAVE_MODE_1920X1080P30 = 0,
GC2053_SLAVE_MODE_NUM
} GC2053_SLAVE_MODE_E;
typedef struct _GC2053_SLAVE_STATE_S {
CVI_U32 u32Sexp_MAX;
} GC2053_SLAVE_STATE_S;
typedef struct _GC2053_SLAVE_MODE_S {
ISP_WDR_SIZE_S stImg;
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp;
SNS_ATTR_LARGE_S stAgain;
SNS_ATTR_LARGE_S stDgain;
char name[64];
} GC2053_SLAVE_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc2053_Slave[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc2053_Slave_BusInfo[];
extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2053_Slave_MirrorFip[VI_MAX_PIPE_NUM];
extern CVI_U8 gc2053_slave_i2c_addr;
extern const CVI_U32 gc2053_slave_addr_byte;
extern const CVI_U32 gc2053_slave_data_byte;
extern void gc2053_slave_init(VI_PIPE ViPipe);
extern void gc2053_slave_exit(VI_PIPE ViPipe);
extern void gc2053_slave_standby(VI_PIPE ViPipe);
extern void gc2053_slave_restart(VI_PIPE ViPipe);
extern int gc2053_slave_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc2053_slave_read_register(VI_PIPE ViPipe, int addr);
extern void gc2053_slave_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int gc2053_slave_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2053_SLAVE_CMOS_EX_H_ */

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middleware/v2/component/isp/sensor/cv180x/gcore_gc2053_slave/gc2053_slave_cmos_param.h Normal file
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#ifndef __GC2053_CMOS_PARAM_H_
#define __GC2053_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2053_slave_cmos_ex.h"
static const GC2053_SLAVE_MODE_S g_stGc2053_Slave_mode = {
.name = "1920X1080P30",
.stImg = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
.f32MaxFps = 30,
.f32MinFps = 2.07, /* 1125 * 30 / 0x3FFF */
.u32HtsDef = 2200,
.u32VtsDef = 1125,
.stExp = {
.u16Min = 1,
.u16Max = 0x3fff,
.u16Def = 0x2000,
.u16Step = 1,
},
.stAgain = {
.u32Min = 64,
.u32Max = 62977,
.u32Def = 64,
.u32Step = 1,
},
.stDgain = {
.u32Min = 64*16,
.u32Max = 7073*16,
.u32Def = 581*16,
.u32Step = 10*16,
},
};
static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = {
{ //iso 100
{0.05999477580189704895, 0.13019448518753051758}, //B: slope, intercept
{0.06732148677110671997, -1.36387133598327636719}, //Gb: slope, intercept
{0.06651904433965682983, -1.10093510150909423828}, //Gr: slope, intercept
{0.06406146287918090820, 0.33316791057586669922}, //R: slope, intercept
},
{ //iso 200
{0.06256803125143051147, 4.54908418655395507813}, //B: slope, intercept
{0.06911934912204742432, 2.79023528099060058594}, //Gb: slope, intercept
{0.06846688687801361084, 2.88726186752319335938}, //Gr: slope, intercept
{0.06652788817882537842, 4.40276956558227539063}, //R: slope, intercept
},
{ //iso 400
{0.06841833144426345825, 11.72280883789062500000}, //B: slope, intercept
{0.07257881015539169312, 10.86985683441162109375}, //Gb: slope, intercept
{0.07174283266067504883, 11.20646286010742187500}, //Gr: slope, intercept
{0.07294593751430511475, 11.17350578308105468750}, //R: slope, intercept
},
{ //iso 800
{0.07805790752172470093, 20.62956619262695312500}, //B: slope, intercept
{0.07694032043218612671, 22.20356750488281250000}, //Gb: slope, intercept
{0.07647507637739181519, 22.50957298278808593750}, //Gr: slope, intercept
{0.08402533829212188721, 19.11953735351562500000}, //R: slope, intercept
},
{ //iso 1600
{0.09468275308609008789, 34.07563018798828125000}, //B: slope, intercept
{0.08710632473230361938, 39.15500259399414062500}, //Gb: slope, intercept
{0.08662072569131851196, 39.37175750732421875000}, //Gr: slope, intercept
{0.10222808271646499634, 31.34789276123046875000}, //R: slope, intercept
},
{ //iso 3200
{0.12651191651821136475, 49.56183242797851562500}, //B: slope, intercept
{0.10816962271928787231, 59.42719650268554687500}, //Gb: slope, intercept
{0.10751257836818695068, 59.90552902221679687500}, //Gr: slope, intercept
{0.13802853226661682129, 45.09576034545898437500}, //R: slope, intercept
},
{ //iso 6400
{0.17422541975975036621, 70.04063415527343750000}, //B: slope, intercept
{0.14234761893749237061, 85.51583862304687500000}, //Gb: slope, intercept
{0.14159946143627166748, 86.23278045654296875000}, //Gr: slope, intercept
{0.19450971484184265137, 62.65447235107421875000}, //R: slope, intercept
},
{ //iso 12800
{0.24947367608547210693, 108.30633544921875000000}, //B: slope, intercept
{0.19751225411891937256, 130.88159179687500000000}, //Gb: slope, intercept
{0.19614629447460174561, 132.49082946777343750000}, //Gr: slope, intercept
{0.28106108307838439941, 97.15969085693359375000}, //R: slope, intercept
},
{ //iso 25600
{0.35420843958854675293, 137.06745910644531250000}, //B: slope, intercept
{0.27778801321983337402, 168.72366333007812500000}, //Gb: slope, intercept
{0.27540388703346252441, 170.54939270019531250000}, //Gr: slope, intercept
{0.39949953556060791016, 123.29409790039062500000}, //R: slope, intercept
},
{ //iso 51200
{0.45704349875450134277, 179.20147705078125000000}, //B: slope, intercept
{0.32142028212547302246, 246.71363830566406250000}, //Gb: slope, intercept
{0.31958609819412231445, 246.82630920410156250000}, //Gr: slope, intercept
{0.51058447360992431641, 161.86299133300781250000}, //R: slope, intercept
},
{ //iso 102400
{0.61760461330413818359, 222.90534973144531250000}, //B: slope, intercept
{0.42568457126617431641, 319.29257202148437500000}, //Gb: slope, intercept
{0.41750904917716979980, 324.93432617187500000000}, //Gr: slope, intercept
{0.67956107854843139648, 203.78948974609375000000}, //R: slope, intercept
},
{ //iso 204800
{0.63289469480514526367, 216.99952697753906250000}, //B: slope, intercept
{0.44890350103378295898, 306.80810546875000000000}, //Gb: slope, intercept
{0.44229975342750549316, 310.13763427734375000000}, //Gr: slope, intercept
{0.69596910476684570313, 196.70443725585937500000}, //R: slope, intercept
},
{ //iso 409600
{0.71106964349746704102, 187.98352050781250000000}, //B: slope, intercept
{0.55859673023223876953, 246.22378540039062500000}, //Gb: slope, intercept
{0.55284017324447631836, 249.86463928222656250000}, //Gr: slope, intercept
{0.77318203449249267578, 168.85035705566406250000}, //R: slope, intercept
},
{ //iso 819200
{0.70888006687164306641, 188.44216918945312500000}, //B: slope, intercept
{0.56110274791717529297, 245.46603393554687500000}, //Gb: slope, intercept
{0.55100852251052856445, 250.33049011230468750000}, //Gr: slope, intercept
{0.76897650957107543945, 169.31251525878906250000}, //R: slope, intercept
},
{ //iso 1638400
{0.70520979166030883789, 188.93899536132812500000}, //B: slope, intercept
{0.56178557872772216797, 245.21235656738281250000}, //Gb: slope, intercept
{0.55338454246520996094, 249.57423400878906250000}, //Gr: slope, intercept
{0.77306479215621948242, 168.86497497558593750000}, //R: slope, intercept
},
{ //iso 3276800
{0.71255809068679809570, 187.86839294433593750000}, //B: slope, intercept
{0.56056070327758789063, 245.57748413085937500000}, //Gb: slope, intercept
{0.55358195304870605469, 249.62020874023437500000}, //Gr: slope, intercept
{0.77431541681289672852, 168.74313354492187500000}, //R: slope, intercept
},
} };
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {257, 257, 257, 257, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1093, 1093, 1093, 1093
#endif
},
.stAuto = {
{257, 257, 257, 257, 259, 259, 260, 267, 278, 298, 366, 383, 366, 373, 372, 372 },
{257, 257, 257, 257, 258, 259, 261, 266, 274, 297, 379, 377, 372, 365, 373, 374 },
{257, 257, 257, 257, 258, 259, 261, 266, 275, 296, 376, 388, 366, 374, 376, 372 },
{257, 257, 257, 257, 258, 259, 260, 264, 274, 294, 362, 363, 365, 361, 353, 367 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1093, 1093, 1093, 1093, 1093, 1093, 1093, 1095,
1099, 1104, 1125, 1130, 1125, 1127, 1126, 1126},
{1093, 1093, 1093, 1093, 1093, 1093, 1094, 1095,
1097, 1104, 1128, 1128, 1126, 1124, 1127, 1127},
{1093, 1093, 1093, 1093, 1093, 1093, 1094, 1095,
1098, 1104, 1128, 1131, 1125, 1127, 1128, 1126},
{1093, 1093, 1093, 1093, 1093, 1093, 1093, 1095,
1097, 1103, 1123, 1124, 1124, 1123, 1121, 1125},
#endif
},
},
};
struct combo_dev_attr_s gc2053_slave_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {0, 4, 2, -1, -1},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.devno = 1,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2053_SLAVE_CMOS_PARAM_H_ */

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middleware/v2/component/isp/sensor/cv180x/gcore_gc2053_slave/gc2053_slave_sensor_ctl.c Normal file
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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2053_slave_cmos_ex.h"
#define GC2053_SLAVE_CHIP_ID_ADDR_H 0xf0
#define GC2053_SLAVE_CHIP_ID_ADDR_L 0xf1
#define GC2053_SLAVE_CHIP_ID 0x2053
static void gc2053_slave_linear_1080p30_init(VI_PIPE ViPipe);
CVI_U8 gc2053_slave_i2c_addr = 0x37;//0x6e
const CVI_U32 gc2053_slave_addr_byte = 1;
const CVI_U32 gc2053_slave_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc2053_slave_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc2053_Slave_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc2053_slave_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc2053_slave_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc2053_slave_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (gc2053_slave_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, gc2053_slave_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, gc2053_slave_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (gc2053_slave_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int gc2053_slave_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc2053_slave_addr_byte == 1) {
buf[idx] = addr & 0xff;
idx++;
}
if (gc2053_slave_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc2053_slave_addr_byte + gc2053_slave_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
//syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void gc2053_slave_standby(VI_PIPE ViPipe)
{
gc2053_slave_write_register(ViPipe, 0x3e, 0x00);
gc2053_slave_write_register(ViPipe, 0xf7, 0x00);
gc2053_slave_write_register(ViPipe, 0xfc, 0x01);
gc2053_slave_write_register(ViPipe, 0xf9, 0x83);
printf("gc2053_standby\n");
}
void gc2053_slave_restart(VI_PIPE ViPipe)
{
gc2053_slave_write_register(ViPipe, 0xf9, 0x82);
delay_ms(2);
gc2053_slave_write_register(ViPipe, 0xf7, 0x01);
gc2053_slave_write_register(ViPipe, 0xfc, 0x8e);
gc2053_slave_write_register(ViPipe, 0x3e, 0x91);
printf("gc2053_restart\n");
}
void gc2053_slave_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastGc2053_Slave[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
gc2053_slave_write_register(ViPipe,
g_pastGc2053_Slave[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastGc2053_Slave[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
void gc2053_slave_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 value = 0;
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
value = 0x01;
break;
case ISP_SNS_FLIP:
value = 0x02;
break;
case ISP_SNS_MIRROR_FLIP:
value = 0x03;
break;
default:
return;
}
gc2053_slave_write_register(ViPipe, 0xfe, 0x00);
gc2053_slave_write_register(ViPipe, 0x17, value);
}
int gc2053_slave_probe(VI_PIPE ViPipe)
{
int nVal;
int nVal2;
usleep(50);
if (gc2053_slave_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = gc2053_slave_read_register(ViPipe, GC2053_SLAVE_CHIP_ID_ADDR_H);
nVal2 = gc2053_slave_read_register(ViPipe, GC2053_SLAVE_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC2053_SLAVE_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void gc2053_slave_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode = g_pastGc2053_Slave[ViPipe]->enWDRMode;
gc2053_slave_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "not surpport this WDR_MODE_E!\n");
} else {
gc2053_slave_linear_1080p30_init(ViPipe);
}
g_pastGc2053_Slave[ViPipe]->bInit = CVI_TRUE;
}
void gc2053_slave_exit(VI_PIPE ViPipe)
{
gc2053_slave_i2c_exit(ViPipe);
}
static void gc2053_slave_linear_1080p30_init(VI_PIPE ViPipe)
{
/****system****/
gc2053_slave_write_register(ViPipe, 0xfe, 0x80);
gc2053_slave_write_register(ViPipe, 0xfe, 0x80);
gc2053_slave_write_register(ViPipe, 0xfe, 0x80);
gc2053_slave_write_register(ViPipe, 0xfe, 0x00);
gc2053_slave_write_register(ViPipe, 0xf2, 0x00);
gc2053_slave_write_register(ViPipe, 0xf3, 0x00);
gc2053_slave_write_register(ViPipe, 0xf4, 0x36);
gc2053_slave_write_register(ViPipe, 0xf5, 0xc0);
gc2053_slave_write_register(ViPipe, 0xf6, 0x44);
gc2053_slave_write_register(ViPipe, 0xf7, 0x01);
gc2053_slave_write_register(ViPipe, 0xf8, 0x2c);
gc2053_slave_write_register(ViPipe, 0xf9, 0x42);
gc2053_slave_write_register(ViPipe, 0xfc, 0x8e);
/****CISCTL & ANALOG****/
gc2053_slave_write_register(ViPipe, 0xfe, 0x00);
gc2053_slave_write_register(ViPipe, 0x87, 0x18);
gc2053_slave_write_register(ViPipe, 0xee, 0x30);
gc2053_slave_write_register(ViPipe, 0xd0, 0xb7);
gc2053_slave_write_register(ViPipe, 0x03, 0x04);
gc2053_slave_write_register(ViPipe, 0x04, 0x60);
gc2053_slave_write_register(ViPipe, 0x05, 0x04);
gc2053_slave_write_register(ViPipe, 0x06, 0x4c);
gc2053_slave_write_register(ViPipe, 0x07, 0x00);
gc2053_slave_write_register(ViPipe, 0x08, 0x11);
gc2053_slave_write_register(ViPipe, 0x09, 0x00);
gc2053_slave_write_register(ViPipe, 0x0a, 0x02);
gc2053_slave_write_register(ViPipe, 0x0b, 0x00);
gc2053_slave_write_register(ViPipe, 0x0c, 0x02);
gc2053_slave_write_register(ViPipe, 0x0d, 0x04);
gc2053_slave_write_register(ViPipe, 0x0e, 0x40);
gc2053_slave_write_register(ViPipe, 0x12, 0xe2);
gc2053_slave_write_register(ViPipe, 0x13, 0x16);
gc2053_slave_write_register(ViPipe, 0x19, 0x0a);
gc2053_slave_write_register(ViPipe, 0x21, 0x1c);
gc2053_slave_write_register(ViPipe, 0x28, 0x0a);
gc2053_slave_write_register(ViPipe, 0x29, 0x24);
gc2053_slave_write_register(ViPipe, 0x2b, 0x04);
gc2053_slave_write_register(ViPipe, 0x32, 0xf8);
gc2053_slave_write_register(ViPipe, 0x37, 0x03);
gc2053_slave_write_register(ViPipe, 0x39, 0x15);
gc2053_slave_write_register(ViPipe, 0x41, 0x04);
gc2053_slave_write_register(ViPipe, 0x42, 0x65);
gc2053_slave_write_register(ViPipe, 0x43, 0x07);
gc2053_slave_write_register(ViPipe, 0x44, 0x40);
gc2053_slave_write_register(ViPipe, 0x46, 0x0b);
gc2053_slave_write_register(ViPipe, 0x4b, 0x20);
gc2053_slave_write_register(ViPipe, 0x4e, 0x08);
gc2053_slave_write_register(ViPipe, 0x55, 0x20);
gc2053_slave_write_register(ViPipe, 0x66, 0x05);
gc2053_slave_write_register(ViPipe, 0x67, 0x05);
gc2053_slave_write_register(ViPipe, 0x77, 0x01);
gc2053_slave_write_register(ViPipe, 0x78, 0x00);
gc2053_slave_write_register(ViPipe, 0x7c, 0x93);
gc2053_slave_write_register(ViPipe, 0x8c, 0x12);
gc2053_slave_write_register(ViPipe, 0x8d, 0x92);
gc2053_slave_write_register(ViPipe, 0x90, 0x00);
gc2053_slave_write_register(ViPipe, 0x9d, 0x10);
gc2053_slave_write_register(ViPipe, 0xce, 0x7c);
gc2053_slave_write_register(ViPipe, 0xd2, 0x41);
gc2053_slave_write_register(ViPipe, 0xd3, 0xdc);
gc2053_slave_write_register(ViPipe, 0xe6, 0x50);
/*gain*/
gc2053_slave_write_register(ViPipe, 0xb6, 0xc0);
gc2053_slave_write_register(ViPipe, 0xb0, 0x70);
gc2053_slave_write_register(ViPipe, 0xb1, 0x01);
gc2053_slave_write_register(ViPipe, 0xb2, 0x00);
gc2053_slave_write_register(ViPipe, 0xb3, 0x00);
gc2053_slave_write_register(ViPipe, 0xb4, 0x00);
gc2053_slave_write_register(ViPipe, 0xb8, 0x01);
gc2053_slave_write_register(ViPipe, 0xb9, 0x00);
/*blk*/
gc2053_slave_write_register(ViPipe, 0x26, 0x30);
gc2053_slave_write_register(ViPipe, 0xfe, 0x01);
gc2053_slave_write_register(ViPipe, 0x40, 0x23);
gc2053_slave_write_register(ViPipe, 0x55, 0x07);
gc2053_slave_write_register(ViPipe, 0x60, 0x40);
gc2053_slave_write_register(ViPipe, 0xfe, 0x04);
gc2053_slave_write_register(ViPipe, 0x14, 0x78);
gc2053_slave_write_register(ViPipe, 0x15, 0x78);
gc2053_slave_write_register(ViPipe, 0x16, 0x78);
gc2053_slave_write_register(ViPipe, 0x17, 0x78);
/*window*/
gc2053_slave_write_register(ViPipe, 0xfe, 0x01);
gc2053_slave_write_register(ViPipe, 0x91, 0x00);
gc2053_slave_write_register(ViPipe, 0x92, 0x00);
gc2053_slave_write_register(ViPipe, 0x93, 0x00);
gc2053_slave_write_register(ViPipe, 0x94, 0x03);
gc2053_slave_write_register(ViPipe, 0x95, 0x04);
gc2053_slave_write_register(ViPipe, 0x96, 0x38);
gc2053_slave_write_register(ViPipe, 0x97, 0x07);
gc2053_slave_write_register(ViPipe, 0x98, 0x80);
/*ISP*/
gc2053_slave_write_register(ViPipe, 0xfe, 0x01);
gc2053_slave_write_register(ViPipe, 0x01, 0x05);
gc2053_slave_write_register(ViPipe, 0x02, 0x89);
gc2053_slave_write_register(ViPipe, 0x04, 0x01);
gc2053_slave_write_register(ViPipe, 0x07, 0xa6);
gc2053_slave_write_register(ViPipe, 0x08, 0xa9);
gc2053_slave_write_register(ViPipe, 0x09, 0xa8);
gc2053_slave_write_register(ViPipe, 0x0a, 0xa7);
gc2053_slave_write_register(ViPipe, 0x0b, 0xff);
gc2053_slave_write_register(ViPipe, 0x0c, 0xff);
gc2053_slave_write_register(ViPipe, 0x0f, 0x00);
gc2053_slave_write_register(ViPipe, 0x50, 0x1c);
gc2053_slave_write_register(ViPipe, 0x89, 0x03);
gc2053_slave_write_register(ViPipe, 0xfe, 0x04);
gc2053_slave_write_register(ViPipe, 0x28, 0x86);
gc2053_slave_write_register(ViPipe, 0x29, 0x86);
gc2053_slave_write_register(ViPipe, 0x2a, 0x86);
gc2053_slave_write_register(ViPipe, 0x2b, 0x68);
gc2053_slave_write_register(ViPipe, 0x2c, 0x68);
gc2053_slave_write_register(ViPipe, 0x2d, 0x68);
gc2053_slave_write_register(ViPipe, 0x2e, 0x68);
gc2053_slave_write_register(ViPipe, 0x2f, 0x68);
gc2053_slave_write_register(ViPipe, 0x30, 0x4f);
gc2053_slave_write_register(ViPipe, 0x31, 0x68);
gc2053_slave_write_register(ViPipe, 0x32, 0x67);
gc2053_slave_write_register(ViPipe, 0x33, 0x66);
gc2053_slave_write_register(ViPipe, 0x34, 0x66);
gc2053_slave_write_register(ViPipe, 0x35, 0x66);
gc2053_slave_write_register(ViPipe, 0x36, 0x66);
gc2053_slave_write_register(ViPipe, 0x37, 0x66);
gc2053_slave_write_register(ViPipe, 0x38, 0x62);
gc2053_slave_write_register(ViPipe, 0x39, 0x62);
gc2053_slave_write_register(ViPipe, 0x3a, 0x62);
gc2053_slave_write_register(ViPipe, 0x3b, 0x62);
gc2053_slave_write_register(ViPipe, 0x3c, 0x62);
gc2053_slave_write_register(ViPipe, 0x3d, 0x62);
gc2053_slave_write_register(ViPipe, 0x3e, 0x62);
gc2053_slave_write_register(ViPipe, 0x3f, 0x62);
/****DVP & MIPI****/
gc2053_slave_write_register(ViPipe, 0xfe, 0x01);
gc2053_slave_write_register(ViPipe, 0x9a, 0x06);
gc2053_slave_write_register(ViPipe, 0xfe, 0x00);
gc2053_slave_write_register(ViPipe, 0x7b, 0x2a);
gc2053_slave_write_register(ViPipe, 0x23, 0x2d);
gc2053_slave_write_register(ViPipe, 0xfe, 0x03);
gc2053_slave_write_register(ViPipe, 0x01, 0x27);
gc2053_slave_write_register(ViPipe, 0x02, 0x56);
gc2053_slave_write_register(ViPipe, 0x03, 0x8e);
gc2053_slave_write_register(ViPipe, 0x12, 0x80);
gc2053_slave_write_register(ViPipe, 0x13, 0x07);
gc2053_slave_write_register(ViPipe, 0x15, 0x12);
gc2053_slave_write_register(ViPipe, 0xfe, 0x00);
gc2053_slave_write_register(ViPipe, 0x3e, 0x91);
gc2053_slave_default_reg_init(ViPipe);
printf("ViPipe:%d,===GC2053 1080P 30fps 10bit LINE Init OK!===\n", ViPipe);
}

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc2093.a
TARGET_SO = $(MW_LIB)/libsns_gc2093.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

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#ifndef __GC2093_CMOS_EX_H_
#define __GC2093_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#ifndef UNUSED
#define UNUSED(x) ((void)(x))
#endif
enum gc2093_linear_regs_e {
LINEAR_EXP_H = 0, //03
LINEAR_EXP_L, //04
LINEAR_AGAIN_L, //b3
LINEAR_COL_AGAIN_H, //b8
LINEAR_COL_AGAIN_L, //b9
LINEAR_AGAIN_MAG1, //0x155
LINEAR_AGAIN_HOLD, //0x031d
LINEAR_AGAIN_MAG2, //0xc2
LINEAR_AGAIN_MAG3, //0xcf
LINEAR_AGAIN_MAG4, //0xd9
LINEAR_AGAIN_REL, //0x031d
LINEAR_DGAIN_H, //b1
LINEAR_DGAIN_L, //b2
LINEAR_VTS_H, //0x41 (frame length)
LINEAR_VTS_L, //0x42
LINEAR_REGS_NUM
};
enum gc2093_wdr_regs_e {
WDR_SEXP_H = 0, //01
WDR_SEXP_L, //02
WDR_LEXP_H, //03
WDR_LEXP_L, //04
WDR_AGAIN_L, //b3
WDR_COL_AGAIN_H, //b8
WDR_COL_AGAIN_L, //b9
WDR_AGAIN_MAG1, //0x155
WDR_AGAIN_HOLD, //0x031d
WDR_AGAIN_MAG2, //0xc2
WDR_AGAIN_MAG3, //0xcf
WDR_AGAIN_MAG4, //0xd9
WDR_AGAIN_REL, //0x031d
WDR_DGAIN_H, //b1
WDR_DGAIN_L, //b2
WDR_VTS_H, //0x41 (frame length)
WDR_VTS_L, //0x42
WDR_REGS_NUM
};
typedef enum _GC2093_MODE_E {
GC2093_MODE_1920X1080P30 = 0,
GC2093_MODE_LINEAR_NUM,
GC2093_MODE_1920X1080P30_WDR = GC2093_MODE_LINEAR_NUM,
GC2093_MODE_NUM
} GC2093_MODE_E;
typedef struct _GC2093_STATE_S {
CVI_U32 u32Sexp_MAX;
} GC2093_STATE_S;
typedef struct _GC2093_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
char name[64];
} GC2093_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc2093[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc2093_BusInfo[];
extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2093_MirrorFip[VI_MAX_PIPE_NUM];
extern const CVI_U8 gc2093_i2c_addr;
extern const CVI_U32 gc2093_addr_byte;
extern const CVI_U32 gc2093_data_byte;
extern void gc2093_init(VI_PIPE ViPipe);
extern void gc2093_exit(VI_PIPE ViPipe);
extern void gc2093_standby(VI_PIPE ViPipe);
extern void gc2093_restart(VI_PIPE ViPipe);
extern int gc2093_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc2093_read_register(VI_PIPE ViPipe, int addr);
extern void gc2093_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int gc2093_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2093_CMOS_EX_H_ */

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#ifndef __GC2093_CMOS_PARAM_H_
#define __GC2093_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2093_cmos_ex.h"
static const GC2093_MODE_S g_astGc2093_mode[GC2093_MODE_NUM] = {
[GC2093_MODE_1920X1080P30] = {
.name = "1920X1080P30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
.f32MaxFps = 30,
.f32MinFps = 2.07, /* 1125 * 30 / 0x3FFF */
.u32HtsDef = 2200,
.u32VtsDef = 1125,
.stExp[0] = {
.u16Min = 1,
.u16Max = 0x3fff,
.u16Def = 0x2000,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 64,
.u32Max = 62977,
.u32Def = 64,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 64*16,
.u32Max = 7073*16,
.u32Def = 581*16,
.u32Step = 10*16,
},
},
[GC2093_MODE_1920X1080P30_WDR] = {
.name = "1920X1080P30_WDR",
.astImg[0] = {
/* sef */
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
.astImg[1] = {
/* lef */
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
.f32MaxFps = 30,
.f32MinFps = 2.29, /* 1250 * 30 / 0x3FFF */
.u32HtsDef = 2200,
.u32VtsDef = 1250,
.stAgain[0] = {
.u32Min = 64,
.u32Max = 62977,
.u32Def = 64,
.u32Step = 1,
},
.stAgain[1] = {
.u32Min = 64,
.u32Max = 62977,
.u32Def = 64,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 64*16,
.u32Max = 7073*16,
.u32Def = 581*16,
.u32Step = 10*16,
},
.stDgain[1] = {
.u32Min = 64*16,
.u32Max = 7073*16,
.u32Def = 581*16,
.u32Step = 10*16,
},
},
};
static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = {
{ //iso 100
{0.05999477580189704895, 0.13019448518753051758}, //B: slope, intercept
{0.06732148677110671997, -1.36387133598327636719}, //Gb: slope, intercept
{0.06651904433965682983, -1.10093510150909423828}, //Gr: slope, intercept
{0.06406146287918090820, 0.33316791057586669922}, //R: slope, intercept
},
{ //iso 200
{0.06256803125143051147, 4.54908418655395507813}, //B: slope, intercept
{0.06911934912204742432, 2.79023528099060058594}, //Gb: slope, intercept
{0.06846688687801361084, 2.88726186752319335938}, //Gr: slope, intercept
{0.06652788817882537842, 4.40276956558227539063}, //R: slope, intercept
},
{ //iso 400
{0.06841833144426345825, 11.72280883789062500000}, //B: slope, intercept
{0.07257881015539169312, 10.86985683441162109375}, //Gb: slope, intercept
{0.07174283266067504883, 11.20646286010742187500}, //Gr: slope, intercept
{0.07294593751430511475, 11.17350578308105468750}, //R: slope, intercept
},
{ //iso 800
{0.07805790752172470093, 20.62956619262695312500}, //B: slope, intercept
{0.07694032043218612671, 22.20356750488281250000}, //Gb: slope, intercept
{0.07647507637739181519, 22.50957298278808593750}, //Gr: slope, intercept
{0.08402533829212188721, 19.11953735351562500000}, //R: slope, intercept
},
{ //iso 1600
{0.09468275308609008789, 34.07563018798828125000}, //B: slope, intercept
{0.08710632473230361938, 39.15500259399414062500}, //Gb: slope, intercept
{0.08662072569131851196, 39.37175750732421875000}, //Gr: slope, intercept
{0.10222808271646499634, 31.34789276123046875000}, //R: slope, intercept
},
{ //iso 3200
{0.12651191651821136475, 49.56183242797851562500}, //B: slope, intercept
{0.10816962271928787231, 59.42719650268554687500}, //Gb: slope, intercept
{0.10751257836818695068, 59.90552902221679687500}, //Gr: slope, intercept
{0.13802853226661682129, 45.09576034545898437500}, //R: slope, intercept
},
{ //iso 6400
{0.17422541975975036621, 70.04063415527343750000}, //B: slope, intercept
{0.14234761893749237061, 85.51583862304687500000}, //Gb: slope, intercept
{0.14159946143627166748, 86.23278045654296875000}, //Gr: slope, intercept
{0.19450971484184265137, 62.65447235107421875000}, //R: slope, intercept
},
{ //iso 12800
{0.24947367608547210693, 108.30633544921875000000}, //B: slope, intercept
{0.19751225411891937256, 130.88159179687500000000}, //Gb: slope, intercept
{0.19614629447460174561, 132.49082946777343750000}, //Gr: slope, intercept
{0.28106108307838439941, 97.15969085693359375000}, //R: slope, intercept
},
{ //iso 25600
{0.35420843958854675293, 137.06745910644531250000}, //B: slope, intercept
{0.27778801321983337402, 168.72366333007812500000}, //Gb: slope, intercept
{0.27540388703346252441, 170.54939270019531250000}, //Gr: slope, intercept
{0.39949953556060791016, 123.29409790039062500000}, //R: slope, intercept
},
{ //iso 51200
{0.45704349875450134277, 179.20147705078125000000}, //B: slope, intercept
{0.32142028212547302246, 246.71363830566406250000}, //Gb: slope, intercept
{0.31958609819412231445, 246.82630920410156250000}, //Gr: slope, intercept
{0.51058447360992431641, 161.86299133300781250000}, //R: slope, intercept
},
{ //iso 102400
{0.61760461330413818359, 222.90534973144531250000}, //B: slope, intercept
{0.42568457126617431641, 319.29257202148437500000}, //Gb: slope, intercept
{0.41750904917716979980, 324.93432617187500000000}, //Gr: slope, intercept
{0.67956107854843139648, 203.78948974609375000000}, //R: slope, intercept
},
{ //iso 204800
{0.63289469480514526367, 216.99952697753906250000}, //B: slope, intercept
{0.44890350103378295898, 306.80810546875000000000}, //Gb: slope, intercept
{0.44229975342750549316, 310.13763427734375000000}, //Gr: slope, intercept
{0.69596910476684570313, 196.70443725585937500000}, //R: slope, intercept
},
{ //iso 409600
{0.71106964349746704102, 187.98352050781250000000}, //B: slope, intercept
{0.55859673023223876953, 246.22378540039062500000}, //Gb: slope, intercept
{0.55284017324447631836, 249.86463928222656250000}, //Gr: slope, intercept
{0.77318203449249267578, 168.85035705566406250000}, //R: slope, intercept
},
{ //iso 819200
{0.70888006687164306641, 188.44216918945312500000}, //B: slope, intercept
{0.56110274791717529297, 245.46603393554687500000}, //Gb: slope, intercept
{0.55100852251052856445, 250.33049011230468750000}, //Gr: slope, intercept
{0.76897650957107543945, 169.31251525878906250000}, //R: slope, intercept
},
{ //iso 1638400
{0.70520979166030883789, 188.93899536132812500000}, //B: slope, intercept
{0.56178557872772216797, 245.21235656738281250000}, //Gb: slope, intercept
{0.55338454246520996094, 249.57423400878906250000}, //Gr: slope, intercept
{0.77306479215621948242, 168.86497497558593750000}, //R: slope, intercept
},
{ //iso 3276800
{0.71255809068679809570, 187.86839294433593750000}, //B: slope, intercept
{0.56056070327758789063, 245.57748413085937500000}, //Gb: slope, intercept
{0.55358195304870605469, 249.62020874023437500000}, //Gr: slope, intercept
{0.77431541681289672852, 168.74313354492187500000}, //R: slope, intercept
},
} };
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {256, 256, 256, 256, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1092, 1092, 1092, 1092
#endif
},
.stAuto = {
{256, 257, 257, 257, 259, 259, 260, 267, 278, 298, 366, 383, 366, 373, 372, 372 },
{256, 257, 257, 257, 258, 259, 261, 266, 274, 297, 379, 377, 372, 365, 373, 374 },
{256, 257, 257, 257, 258, 259, 261, 266, 275, 296, 376, 388, 366, 374, 376, 372 },
{256, 257, 257, 257, 258, 259, 260, 264, 274, 294, 362, 363, 365, 361, 353, 367 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1092, 1093, 1093, 1093, 1093, 1093, 1093, 1095, 1099, 1104, 1125, 1130, 1125, 1127,
1126, 1126},
{1092, 1093, 1093, 1093, 1093, 1093, 1094, 1095, 1097, 1104, 1128, 1128, 1126, 1124,
1127, 1127},
{1092, 1093, 1093, 1093, 1093, 1093, 1094, 1095, 1098, 1104, 1128, 1131, 1125, 1127,
1128, 1126},
{1092, 1093, 1093, 1093, 1093, 1093, 1093, 1095, 1097, 1103, 1123, 1124, 1124, 1123,
1121, 1125},
#endif
},
},
};
struct combo_dev_attr_s gc2093_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {1, 0, 2, -1, -1},
.pn_swap = {1, 1, 1, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_VC,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2093_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2093_cmos_ex.h"
static void gc2093_linear_1080p30_init(VI_PIPE ViPipe);
static void gc2093_wdr_1080p30_init(VI_PIPE ViPipe);
const CVI_U8 gc2093_i2c_addr = 0x37;//0x6e
const CVI_U32 gc2093_addr_byte = 2;
const CVI_U32 gc2093_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc2093_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc2093_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc2093_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc2093_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc2093_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (gc2093_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, gc2093_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, gc2093_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (gc2093_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int gc2093_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc2093_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (gc2093_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc2093_addr_byte + gc2093_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
ret = read(g_fd[ViPipe], buf, gc2093_addr_byte + gc2093_data_byte);
//syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void gc2093_standby(VI_PIPE ViPipe)
{
gc2093_write_register(ViPipe, 0x003e, 0x00);
gc2093_write_register(ViPipe, 0x03f7, 0x00);
gc2093_write_register(ViPipe, 0x03fc, 0x01);
gc2093_write_register(ViPipe, 0x03f9, 0x41);
printf("gc2093_standby\n");
}
void gc2093_restart(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode;
CVI_U8 u8ImgMode;
enWDRMode = g_pastGc2093[ViPipe]->enWDRMode;
u8ImgMode = g_pastGc2093[ViPipe]->u8ImgMode;
if (enWDRMode == WDR_MODE_2To1_LINE) {
if (u8ImgMode == GC2093_MODE_1920X1080P30_WDR) {
gc2093_write_register(ViPipe, 0x03f9, 0x40);
usleep(1);
gc2093_write_register(ViPipe, 0x03f7, 0x01);
gc2093_write_register(ViPipe, 0x03fc, 0x8e);
gc2093_write_register(ViPipe, 0x003e, 0x91);
}
} else {
gc2093_write_register(ViPipe, 0x03f9, 0x42);
usleep(1);
gc2093_write_register(ViPipe, 0x03f7, 0x11);
gc2093_write_register(ViPipe, 0x03fc, 0x8e);
gc2093_write_register(ViPipe, 0x003e, 0x91);
}
printf("gc2093_restart\n");
}
void gc2093_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastGc2093[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
gc2093_write_register(ViPipe,
g_pastGc2093[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastGc2093[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
#define GC2093_CHIP_ID_ADDR_H 0x03f0
#define GC2093_CHIP_ID_ADDR_L 0x03f1
#define GC2093_CHIP_ID 0x2093
void gc2093_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 value = 0;
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
value = 0x01;
break;
case ISP_SNS_FLIP:
value = 0x02;
break;
case ISP_SNS_MIRROR_FLIP:
value = 0x03;
break;
default:
return;
}
gc2093_write_register(ViPipe, 0xfe, 0x00);
gc2093_write_register(ViPipe, 0x17, value);
}
int gc2093_probe(VI_PIPE ViPipe)
{
int nVal;
int nVal2;
usleep(50);
if (gc2093_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = gc2093_read_register(ViPipe, GC2093_CHIP_ID_ADDR_H);
nVal2 = gc2093_read_register(ViPipe, GC2093_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC2093_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void gc2093_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode;
CVI_U8 u8ImgMode;
enWDRMode = g_pastGc2093[ViPipe]->enWDRMode;
u8ImgMode = g_pastGc2093[ViPipe]->u8ImgMode;
gc2093_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
if (u8ImgMode == GC2093_MODE_1920X1080P30_WDR) {
gc2093_wdr_1080p30_init(ViPipe);
}
} else {
gc2093_linear_1080p30_init(ViPipe);
}
g_pastGc2093[ViPipe]->bInit = CVI_TRUE;
}
void gc2093_exit(VI_PIPE ViPipe)
{
gc2093_i2c_exit(ViPipe);
}
static void gc2093_linear_1080p30_init(VI_PIPE ViPipe)
{
delay_ms(10);
/****system****/
gc2093_write_register(ViPipe, 0x03fe, 0xf0);
gc2093_write_register(ViPipe, 0x03fe, 0xf0);
gc2093_write_register(ViPipe, 0x03fe, 0xf0);
gc2093_write_register(ViPipe, 0x03fe, 0x00);
gc2093_write_register(ViPipe, 0x03f2, 0x00);
gc2093_write_register(ViPipe, 0x03f3, 0x00);
gc2093_write_register(ViPipe, 0x03f4, 0x36);
gc2093_write_register(ViPipe, 0x03f5, 0xc0);
gc2093_write_register(ViPipe, 0x03f6, 0x0B);
gc2093_write_register(ViPipe, 0x03f7, 0x11);
gc2093_write_register(ViPipe, 0x03f8, 0x2A);
gc2093_write_register(ViPipe, 0x03f9, 0x42);
gc2093_write_register(ViPipe, 0x03fc, 0x8e);
/****CISCTL & ANALOG*/
gc2093_write_register(ViPipe, 0x0087, 0x18);
gc2093_write_register(ViPipe, 0x00ee, 0x30);
gc2093_write_register(ViPipe, 0x00d0, 0xbf);
gc2093_write_register(ViPipe, 0x01a0, 0x00);
gc2093_write_register(ViPipe, 0x01a4, 0x40);
gc2093_write_register(ViPipe, 0x01a5, 0x40);
gc2093_write_register(ViPipe, 0x01a6, 0x40);
gc2093_write_register(ViPipe, 0x01af, 0x09);
gc2093_write_register(ViPipe, 0x0003, 0x04);
gc2093_write_register(ViPipe, 0x0004, 0x65);
gc2093_write_register(ViPipe, 0x0005, 0x05);
gc2093_write_register(ViPipe, 0x0006, 0x78);
gc2093_write_register(ViPipe, 0x0007, 0x00);
gc2093_write_register(ViPipe, 0x0008, 0x11);
gc2093_write_register(ViPipe, 0x0009, 0x00);
gc2093_write_register(ViPipe, 0x000a, 0x02);
gc2093_write_register(ViPipe, 0x000b, 0x00);
gc2093_write_register(ViPipe, 0x000c, 0x04);
gc2093_write_register(ViPipe, 0x000d, 0x04);
gc2093_write_register(ViPipe, 0x000e, 0x40);
gc2093_write_register(ViPipe, 0x000f, 0x07);
gc2093_write_register(ViPipe, 0x0010, 0x8c);
gc2093_write_register(ViPipe, 0x0013, 0x15);
gc2093_write_register(ViPipe, 0x0019, 0x0c);
gc2093_write_register(ViPipe, 0x0041, 0x04);
gc2093_write_register(ViPipe, 0x0042, 0x65);
gc2093_write_register(ViPipe, 0x0053, 0x60);
gc2093_write_register(ViPipe, 0x008d, 0x92);
gc2093_write_register(ViPipe, 0x0090, 0x00);
gc2093_write_register(ViPipe, 0x00c7, 0xe1);
gc2093_write_register(ViPipe, 0x001b, 0x73);
gc2093_write_register(ViPipe, 0x0028, 0x0d);
gc2093_write_register(ViPipe, 0x0029, 0x40);
gc2093_write_register(ViPipe, 0x002b, 0x04);
gc2093_write_register(ViPipe, 0x002e, 0x23);
gc2093_write_register(ViPipe, 0x0037, 0x03);
gc2093_write_register(ViPipe, 0x0043, 0x04);
gc2093_write_register(ViPipe, 0x0044, 0x30);
gc2093_write_register(ViPipe, 0x004a, 0x01);
gc2093_write_register(ViPipe, 0x004b, 0x28);
gc2093_write_register(ViPipe, 0x0055, 0x30);
gc2093_write_register(ViPipe, 0x0066, 0x3f);
gc2093_write_register(ViPipe, 0x0068, 0x3f);
gc2093_write_register(ViPipe, 0x006b, 0x44);
gc2093_write_register(ViPipe, 0x0077, 0x00);
gc2093_write_register(ViPipe, 0x0078, 0x20);
gc2093_write_register(ViPipe, 0x007c, 0xa1);
gc2093_write_register(ViPipe, 0x00ce, 0x7c);
gc2093_write_register(ViPipe, 0x00d3, 0xd4);
gc2093_write_register(ViPipe, 0x00e6, 0x50);
/*gain*/
gc2093_write_register(ViPipe, 0x00b6, 0xc0);
gc2093_write_register(ViPipe, 0x00b0, 0x68);
gc2093_write_register(ViPipe, 0x00b3, 0x00);
gc2093_write_register(ViPipe, 0x00b8, 0x01);
gc2093_write_register(ViPipe, 0x00b9, 0x00);
gc2093_write_register(ViPipe, 0x00b1, 0x01);
gc2093_write_register(ViPipe, 0x00b2, 0x00);
/*isp*/
gc2093_write_register(ViPipe, 0x0101, 0x0c);
gc2093_write_register(ViPipe, 0x0102, 0x89);
gc2093_write_register(ViPipe, 0x0104, 0x01);
gc2093_write_register(ViPipe, 0x0107, 0xa6);
gc2093_write_register(ViPipe, 0x0108, 0xa9);
gc2093_write_register(ViPipe, 0x0109, 0xa8);
gc2093_write_register(ViPipe, 0x010a, 0xa7);
gc2093_write_register(ViPipe, 0x010b, 0xff);
gc2093_write_register(ViPipe, 0x010c, 0xff);
gc2093_write_register(ViPipe, 0x010f, 0x00);
gc2093_write_register(ViPipe, 0x0158, 0x00);
gc2093_write_register(ViPipe, 0x0428, 0x86);
gc2093_write_register(ViPipe, 0x0429, 0x86);
gc2093_write_register(ViPipe, 0x042a, 0x86);
gc2093_write_register(ViPipe, 0x042b, 0x68);
gc2093_write_register(ViPipe, 0x042c, 0x68);
gc2093_write_register(ViPipe, 0x042d, 0x68);
gc2093_write_register(ViPipe, 0x042e, 0x68);
gc2093_write_register(ViPipe, 0x042f, 0x68);
gc2093_write_register(ViPipe, 0x0430, 0x4f);
gc2093_write_register(ViPipe, 0x0431, 0x68);
gc2093_write_register(ViPipe, 0x0432, 0x67);
gc2093_write_register(ViPipe, 0x0433, 0x66);
gc2093_write_register(ViPipe, 0x0434, 0x66);
gc2093_write_register(ViPipe, 0x0435, 0x66);
gc2093_write_register(ViPipe, 0x0436, 0x66);
gc2093_write_register(ViPipe, 0x0437, 0x66);
gc2093_write_register(ViPipe, 0x0438, 0x62);
gc2093_write_register(ViPipe, 0x0439, 0x62);
gc2093_write_register(ViPipe, 0x043a, 0x62);
gc2093_write_register(ViPipe, 0x043b, 0x62);
gc2093_write_register(ViPipe, 0x043c, 0x62);
gc2093_write_register(ViPipe, 0x043d, 0x62);
gc2093_write_register(ViPipe, 0x043e, 0x62);
gc2093_write_register(ViPipe, 0x043f, 0x62);
/*dark sun*/
gc2093_write_register(ViPipe, 0x0123, 0x08);
gc2093_write_register(ViPipe, 0x0123, 0x00);
gc2093_write_register(ViPipe, 0x0120, 0x01);
gc2093_write_register(ViPipe, 0x0121, 0x04);
gc2093_write_register(ViPipe, 0x0122, 0x65);
gc2093_write_register(ViPipe, 0x0124, 0x03);
gc2093_write_register(ViPipe, 0x0125, 0xff);
gc2093_write_register(ViPipe, 0x001a, 0x8c);
gc2093_write_register(ViPipe, 0x00c6, 0xe0);
/*blk*/
gc2093_write_register(ViPipe, 0x0026, 0x30);
gc2093_write_register(ViPipe, 0x0142, 0x00);
gc2093_write_register(ViPipe, 0x0149, 0x1e);
gc2093_write_register(ViPipe, 0x014a, 0x0f);
gc2093_write_register(ViPipe, 0x014b, 0x00);
gc2093_write_register(ViPipe, 0x0155, 0x07);
gc2093_write_register(ViPipe, 0x0414, 0x78);
gc2093_write_register(ViPipe, 0x0415, 0x78);
gc2093_write_register(ViPipe, 0x0416, 0x78);
gc2093_write_register(ViPipe, 0x0417, 0x78);
gc2093_write_register(ViPipe, 0x04e0, 0x18);
/*window*/
gc2093_write_register(ViPipe, 0x0192, 0x02);
gc2093_write_register(ViPipe, 0x0194, 0x03);
gc2093_write_register(ViPipe, 0x0195, 0x04);
gc2093_write_register(ViPipe, 0x0196, 0x38);
gc2093_write_register(ViPipe, 0x0197, 0x07);
gc2093_write_register(ViPipe, 0x0198, 0x80);
/****DVP & MIPI****/
gc2093_write_register(ViPipe, 0x019a, 0x06);
gc2093_write_register(ViPipe, 0x007b, 0x2a);
gc2093_write_register(ViPipe, 0x0023, 0x2d);
gc2093_write_register(ViPipe, 0x0201, 0x27);
gc2093_write_register(ViPipe, 0x0202, 0x56);
gc2093_write_register(ViPipe, 0x0203, 0xb6);
gc2093_write_register(ViPipe, 0x0212, 0x80);
gc2093_write_register(ViPipe, 0x0213, 0x07);
gc2093_write_register(ViPipe, 0x0215, 0x10);
gc2093_write_register(ViPipe, 0x003e, 0x91);
gc2093_default_reg_init(ViPipe);
delay_ms(80);
printf("ViPipe:%d,===GC2093 1080P 30fps 10bit LINE Init OK!===\n", ViPipe);
}
static void gc2093_wdr_1080p30_init(VI_PIPE ViPipe)
{
delay_ms(10);
/****system**/
gc2093_write_register(ViPipe, 0x03fe, 0xf0);
gc2093_write_register(ViPipe, 0x03fe, 0xf0);
gc2093_write_register(ViPipe, 0x03fe, 0xf0);
gc2093_write_register(ViPipe, 0x03fe, 0x00);
gc2093_write_register(ViPipe, 0x03f2, 0x00);
gc2093_write_register(ViPipe, 0x03f3, 0x00);
gc2093_write_register(ViPipe, 0x03f4, 0x36);
gc2093_write_register(ViPipe, 0x03f5, 0xc0);
gc2093_write_register(ViPipe, 0x03f6, 0x0B);
gc2093_write_register(ViPipe, 0x03f7, 0x01);
gc2093_write_register(ViPipe, 0x03f8, 0x58);
gc2093_write_register(ViPipe, 0x03f9, 0x40);
gc2093_write_register(ViPipe, 0x03fc, 0x8e);
/****CISCTL**/
gc2093_write_register(ViPipe, 0x0087, 0x18);
gc2093_write_register(ViPipe, 0x00ee, 0x30);
gc2093_write_register(ViPipe, 0x00d0, 0xbf);
gc2093_write_register(ViPipe, 0x01a0, 0x00);
gc2093_write_register(ViPipe, 0x01a4, 0x40);
gc2093_write_register(ViPipe, 0x01a5, 0x40);
gc2093_write_register(ViPipe, 0x01a6, 0x40);
gc2093_write_register(ViPipe, 0x01af, 0x09);
gc2093_write_register(ViPipe, 0x0001, 0x00);
gc2093_write_register(ViPipe, 0x0002, 0x02);
gc2093_write_register(ViPipe, 0x0003, 0x04);
gc2093_write_register(ViPipe, 0x0004, 0x02);
gc2093_write_register(ViPipe, 0x0005, 0x02);
gc2093_write_register(ViPipe, 0x0006, 0x94);
gc2093_write_register(ViPipe, 0x0007, 0x00);
gc2093_write_register(ViPipe, 0x0008, 0x11);
gc2093_write_register(ViPipe, 0x0009, 0x00);
gc2093_write_register(ViPipe, 0x000a, 0x02);
gc2093_write_register(ViPipe, 0x000b, 0x00);
gc2093_write_register(ViPipe, 0x000c, 0x04);
gc2093_write_register(ViPipe, 0x000d, 0x04);
gc2093_write_register(ViPipe, 0x000e, 0x40);
gc2093_write_register(ViPipe, 0x000f, 0x07);
gc2093_write_register(ViPipe, 0x0010, 0x8c);
gc2093_write_register(ViPipe, 0x0013, 0x15);
gc2093_write_register(ViPipe, 0x0019, 0x0c);
gc2093_write_register(ViPipe, 0x0041, 0x04);
gc2093_write_register(ViPipe, 0x0042, 0xE2);
gc2093_write_register(ViPipe, 0x0053, 0x60);
gc2093_write_register(ViPipe, 0x008d, 0x92);
gc2093_write_register(ViPipe, 0x0090, 0x00);
gc2093_write_register(ViPipe, 0x00c7, 0xe1);
gc2093_write_register(ViPipe, 0x001b, 0x73);
gc2093_write_register(ViPipe, 0x0028, 0x0d);
gc2093_write_register(ViPipe, 0x0029, 0x24);
gc2093_write_register(ViPipe, 0x002b, 0x04);
gc2093_write_register(ViPipe, 0x002e, 0x23);
gc2093_write_register(ViPipe, 0x0037, 0x03);
gc2093_write_register(ViPipe, 0x0043, 0x04);
gc2093_write_register(ViPipe, 0x0044, 0x28);
gc2093_write_register(ViPipe, 0x004a, 0x01);
gc2093_write_register(ViPipe, 0x004b, 0x20);
gc2093_write_register(ViPipe, 0x0055, 0x28);
gc2093_write_register(ViPipe, 0x0066, 0x3f);
gc2093_write_register(ViPipe, 0x0068, 0x3f);
gc2093_write_register(ViPipe, 0x006b, 0x44);
gc2093_write_register(ViPipe, 0x0077, 0x00);
gc2093_write_register(ViPipe, 0x0078, 0x20);
gc2093_write_register(ViPipe, 0x007c, 0xa1);
gc2093_write_register(ViPipe, 0x00ce, 0x7c);
gc2093_write_register(ViPipe, 0x00d3, 0xd4);
gc2093_write_register(ViPipe, 0x00e6, 0x50);
/*gain*/
gc2093_write_register(ViPipe, 0x00b6, 0xc0);
gc2093_write_register(ViPipe, 0x00b0, 0x68);
/*isp*/
gc2093_write_register(ViPipe, 0x0101, 0x0c);
gc2093_write_register(ViPipe, 0x0102, 0x89);
gc2093_write_register(ViPipe, 0x0104, 0x01);
gc2093_write_register(ViPipe, 0x010e, 0x01);
gc2093_write_register(ViPipe, 0x010f, 0x00);
gc2093_write_register(ViPipe, 0x0158, 0x00);
/*dark sun*/
gc2093_write_register(ViPipe, 0x0123, 0x08);
gc2093_write_register(ViPipe, 0x0123, 0x00);
gc2093_write_register(ViPipe, 0x0120, 0x01);
gc2093_write_register(ViPipe, 0x0121, 0x04);
gc2093_write_register(ViPipe, 0x0122, 0xd8);
gc2093_write_register(ViPipe, 0x0124, 0x03);
gc2093_write_register(ViPipe, 0x0125, 0xff);
gc2093_write_register(ViPipe, 0x001a, 0x8c);
gc2093_write_register(ViPipe, 0x00c6, 0xe0);
/*blk*/
gc2093_write_register(ViPipe, 0x0026, 0x30);
gc2093_write_register(ViPipe, 0x0142, 0x00);
gc2093_write_register(ViPipe, 0x0149, 0x1e);
gc2093_write_register(ViPipe, 0x014a, 0x0f);
gc2093_write_register(ViPipe, 0x014b, 0x00);
gc2093_write_register(ViPipe, 0x0155, 0x07);
gc2093_write_register(ViPipe, 0x0414, 0x78);
gc2093_write_register(ViPipe, 0x0415, 0x78);
gc2093_write_register(ViPipe, 0x0416, 0x78);
gc2093_write_register(ViPipe, 0x0417, 0x78);
gc2093_write_register(ViPipe, 0x0454, 0x78);
gc2093_write_register(ViPipe, 0x0455, 0x78);
gc2093_write_register(ViPipe, 0x0456, 0x78);
gc2093_write_register(ViPipe, 0x0457, 0x78);
gc2093_write_register(ViPipe, 0x04e0, 0x18);
/*window*/
gc2093_write_register(ViPipe, 0x0192, 0x02);
gc2093_write_register(ViPipe, 0x0194, 0x03);
gc2093_write_register(ViPipe, 0x0195, 0x04);
gc2093_write_register(ViPipe, 0x0196, 0x38);
gc2093_write_register(ViPipe, 0x0197, 0x07);
gc2093_write_register(ViPipe, 0x0198, 0x80);
/****DVP**/
gc2093_write_register(ViPipe, 0x019a, 0x06);
gc2093_write_register(ViPipe, 0x007b, 0x2a);
gc2093_write_register(ViPipe, 0x0023, 0x2d);
gc2093_write_register(ViPipe, 0x0201, 0x27);
gc2093_write_register(ViPipe, 0x0202, 0x56);
gc2093_write_register(ViPipe, 0x0203, 0xb6);
gc2093_write_register(ViPipe, 0x0212, 0x80);
gc2093_write_register(ViPipe, 0x0213, 0x07);
gc2093_write_register(ViPipe, 0x0215, 0x10);
gc2093_write_register(ViPipe, 0x003e, 0x91);
/****HDR EN**/
gc2093_write_register(ViPipe, 0x0027, 0x71);
gc2093_write_register(ViPipe, 0x0215, 0x92);
gc2093_write_register(ViPipe, 0x024d, 0x01);
gc2093_default_reg_init(ViPipe);
delay_ms(80);
printf("ViPipe:%d,===GC2093 1080P 30fps 10bit LINE WDR2TO1 OK!===\n", ViPipe);
}

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc2145.a
TARGET_SO = $(MW_LIB)/libsns_gc2145.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "gc2145_cmos_ex.h"
#include "gc2145_cmos_param.h"
#define GC2145_ID 0x2145
#define GC2145_I2C_ADDR_1 0x3f
#define GC2145_I2C_ADDR_2 0x37
#define GC2145_I2C_ADDR_IS_VALID(addr) ((addr) == GC2145_I2C_ADDR_1 || (addr) == GC2145_I2C_ADDR_2)
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_STATE_S *g_pastGc2145[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define GC2145_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc2145[dev])
#define GC2145_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc2145[dev] = pstCtx)
#define GC2145_SENSOR_RESET_CTX(dev) (g_pastGc2145[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunGc2145_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
/****************************************************************************
* local variables and functions *
****************************************************************************/
#define GC2145_RES_IS_1200P(w, h) ((w) == 1600 && (h) == 1200)
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const GC2145_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2145_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astGc2145_mode;
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
GC2145_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstCfg0 = &pstSnsState->astSyncInfo[0];
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
GC2145_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 12) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (GC2145_RES_IS_1200P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = GC2145_MODE_1600X1200P12;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps);
return CVI_FAILURE;
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2145_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = GC2145_MODE_1600X1200P12;
pstSnsState->enWDRMode = WDR_MODE_NONE;
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC2145_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &gc2145_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_astGc2145_mode.stImg.stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astGc2145_mode.stImg.stSnsSize.u32Height;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc2145_rx_attr;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = gc2145_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = gc2145_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (GC2145_I2C_ADDR_IS_VALID(s32I2cAddr))
gc2145_i2c_addr = s32I2cAddr;
}
static CVI_S32 gc2145_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunGc2145_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC2145_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
GC2145_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC2145_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
GC2145_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
(void) pstAeLib;
(void) pstAwbLib;
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = GC2145_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
(void) pstAeLib;
(void) pstAwbLib;
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC2145_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return gc2145_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsGc2145_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = CVI_NULL,
.pfnRestart = CVI_NULL,
.pfnWriteReg = gc2145_write_register,
.pfnReadReg = gc2145_read_register,
.pfnSetBusInfo = gc2145_set_bus_info,
.pfnSetInit = CVI_NULL,
.pfnMirrorFlip = CVI_NULL,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = CVI_NULL,
.pfnSnsProbe = sensor_probe,
};

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#ifndef __GC2145_CMOS_EX_H_
#define __GC2145_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
typedef enum _GC2145_MODE_E {
GC2145_MODE_1600X1200P12 = 0,
GC2145_MODE_NUM
} GC2145_SLAVE_MODE_E;
typedef struct _GC2145_MODE_S {
ISP_WDR_SIZE_S stImg;
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp;
SNS_ATTR_LARGE_S stAgain;
SNS_ATTR_LARGE_S stDgain;
char name[64];
} GC2145_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc2145[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc2145_BusInfo[];
extern CVI_U8 gc2145_i2c_addr;
extern const CVI_U32 gc2145_addr_byte;
extern const CVI_U32 gc2145_data_byte;
extern void gc2145_init(VI_PIPE ViPipe);
extern void gc2145_exit(VI_PIPE ViPipe);
extern void gc2145_standby(VI_PIPE ViPipe);
extern void gc2145_restart(VI_PIPE ViPipe);
extern int gc2145_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc2145_read_register(VI_PIPE ViPipe, int addr);
extern void gc2145_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int gc2145_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2145_CMOS_EX_H_ */

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#ifndef __GC2145_CMOS_PARAM_H_
#define __GC2145_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2145_cmos_ex.h"
static const GC2145_MODE_S g_astGc2145_mode = {
.name = "1600X1200P12",
.stImg = {
.stSnsSize = {
.u32Width = 1600,
.u32Height = 1200,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1600,
.u32Height = 1200,
},
.stMaxSize = {
.u32Width = 1600,
.u32Height = 1200,
},
},
};
struct combo_dev_attr_s gc2145_rx_attr = {
.input_mode = INPUT_MODE_BT601,
.mac_clk = RX_MAC_CLK_400M,
.ttl_attr = {
.vi = TTL_VI_SRC_VI1,
.ttl_fmt = TTL_VSDE_11B,
.raw_data_type = RAW_DATA_8BIT,
.func = {
8, -1, -1, 7,
2, 3, 4, 5,
6, 9, 10, 1,
-1, -1, -1, -1,
-1, -1, -1, -1,
},
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_24M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC2145_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc2145_cmos_ex.h"
static void gc2145_linear_1200p12_init(VI_PIPE ViPipe);
CVI_U8 gc2145_i2c_addr = 0x3C;//0x78
const CVI_U32 gc2145_addr_byte = 1;
const CVI_U32 gc2145_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc2145_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc2145_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc2145_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc2145_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc2145_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (gc2145_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, gc2145_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, gc2145_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (gc2145_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int gc2145_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc2145_addr_byte == 1) {
buf[idx] = addr & 0xff;
idx++;
}
if (gc2145_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc2145_addr_byte + gc2145_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
//syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
#define GC2145_CHIP_ID_ADDR_H 0xf0
#define GC2145_CHIP_ID_ADDR_L 0xf1
#define GC2145_CHIP_ID 0x2145
int gc2145_probe(VI_PIPE ViPipe)
{
int nVal;
int nVal2;
usleep(50);
if (gc2145_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = gc2145_read_register(ViPipe, GC2145_CHIP_ID_ADDR_H);
nVal2 = gc2145_read_register(ViPipe, GC2145_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC2145_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void gc2145_init(VI_PIPE ViPipe)
{
gc2145_i2c_init(ViPipe);
gc2145_linear_1200p12_init(ViPipe);
g_pastGc2145[ViPipe]->bInit = CVI_TRUE;
}
void gc2145_exit(VI_PIPE ViPipe)
{
gc2145_i2c_exit(ViPipe);
}
static void gc2145_linear_1200p12_init(VI_PIPE ViPipe)
{
gc2145_write_register(ViPipe, 0xfe, 0xf0);
gc2145_write_register(ViPipe, 0xfe, 0xf0);
gc2145_write_register(ViPipe, 0xfe, 0xf0);
gc2145_write_register(ViPipe, 0xfc, 0x06);
gc2145_write_register(ViPipe, 0xf6, 0x00);
gc2145_write_register(ViPipe, 0xf7, 0x1d);
gc2145_write_register(ViPipe, 0xf8, 0x84);
gc2145_write_register(ViPipe, 0xfa, 0x00);
gc2145_write_register(ViPipe, 0xf9, 0xfe);
gc2145_write_register(ViPipe, 0xf2, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0x03, 0x04);
gc2145_write_register(ViPipe, 0x04, 0xe2);
gc2145_write_register(ViPipe, 0x09, 0x00);
gc2145_write_register(ViPipe, 0x0a, 0x00);
gc2145_write_register(ViPipe, 0x0b, 0x00);
gc2145_write_register(ViPipe, 0x0c, 0x00);
gc2145_write_register(ViPipe, 0x0d, 0x04);
gc2145_write_register(ViPipe, 0x0e, 0xc0);
gc2145_write_register(ViPipe, 0x0f, 0x06);
gc2145_write_register(ViPipe, 0x10, 0x52);
gc2145_write_register(ViPipe, 0x12, 0x2e);
gc2145_write_register(ViPipe, 0x17, 0x14);
gc2145_write_register(ViPipe, 0x18, 0x22);
gc2145_write_register(ViPipe, 0x19, 0x0e);
gc2145_write_register(ViPipe, 0x1a, 0x01);
gc2145_write_register(ViPipe, 0x1b, 0x4b);
gc2145_write_register(ViPipe, 0x1c, 0x07);
gc2145_write_register(ViPipe, 0x1d, 0x10);
gc2145_write_register(ViPipe, 0x1e, 0x88);
gc2145_write_register(ViPipe, 0x1f, 0x78);
gc2145_write_register(ViPipe, 0x20, 0x03);
gc2145_write_register(ViPipe, 0x21, 0x40);
gc2145_write_register(ViPipe, 0x22, 0xa0);
gc2145_write_register(ViPipe, 0x24, 0x16);
gc2145_write_register(ViPipe, 0x25, 0x01);
gc2145_write_register(ViPipe, 0x26, 0x10);
gc2145_write_register(ViPipe, 0x2d, 0x60);
gc2145_write_register(ViPipe, 0x30, 0x01);
gc2145_write_register(ViPipe, 0x31, 0x90);
gc2145_write_register(ViPipe, 0x33, 0x06);
gc2145_write_register(ViPipe, 0x34, 0x01);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0x80, 0x7f);
gc2145_write_register(ViPipe, 0x81, 0x26);
gc2145_write_register(ViPipe, 0x82, 0xfa);
gc2145_write_register(ViPipe, 0x83, 0x00);
gc2145_write_register(ViPipe, 0x84, 0x00);
gc2145_write_register(ViPipe, 0x86, 0x02);
gc2145_write_register(ViPipe, 0x88, 0x03);
gc2145_write_register(ViPipe, 0x89, 0x03);
gc2145_write_register(ViPipe, 0x85, 0x08);
gc2145_write_register(ViPipe, 0x8a, 0x00);
gc2145_write_register(ViPipe, 0x8b, 0x00);
gc2145_write_register(ViPipe, 0xb0, 0x55);
gc2145_write_register(ViPipe, 0xc3, 0x00);
gc2145_write_register(ViPipe, 0xc4, 0x80);
gc2145_write_register(ViPipe, 0xc5, 0x90);
gc2145_write_register(ViPipe, 0xc6, 0x3b);
gc2145_write_register(ViPipe, 0xc7, 0x46);
gc2145_write_register(ViPipe, 0xec, 0x06);
gc2145_write_register(ViPipe, 0xed, 0x04);
gc2145_write_register(ViPipe, 0xee, 0x60);
gc2145_write_register(ViPipe, 0xef, 0x90);
gc2145_write_register(ViPipe, 0xb6, 0x01);
gc2145_write_register(ViPipe, 0x90, 0x01);
gc2145_write_register(ViPipe, 0x91, 0x00);
gc2145_write_register(ViPipe, 0x92, 0x00);
gc2145_write_register(ViPipe, 0x93, 0x00);
gc2145_write_register(ViPipe, 0x94, 0x00);
gc2145_write_register(ViPipe, 0x95, 0x04);
gc2145_write_register(ViPipe, 0x96, 0xb0);
gc2145_write_register(ViPipe, 0x97, 0x06);
gc2145_write_register(ViPipe, 0x98, 0x40);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0x40, 0x42);
gc2145_write_register(ViPipe, 0x41, 0x00);
gc2145_write_register(ViPipe, 0x43, 0x5b);
gc2145_write_register(ViPipe, 0x5e, 0x00);
gc2145_write_register(ViPipe, 0x5f, 0x00);
gc2145_write_register(ViPipe, 0x60, 0x00);
gc2145_write_register(ViPipe, 0x61, 0x00);
gc2145_write_register(ViPipe, 0x62, 0x00);
gc2145_write_register(ViPipe, 0x63, 0x00);
gc2145_write_register(ViPipe, 0x64, 0x00);
gc2145_write_register(ViPipe, 0x65, 0x00);
gc2145_write_register(ViPipe, 0x66, 0x20);
gc2145_write_register(ViPipe, 0x67, 0x20);
gc2145_write_register(ViPipe, 0x68, 0x20);
gc2145_write_register(ViPipe, 0x69, 0x20);
gc2145_write_register(ViPipe, 0x76, 0x00);
gc2145_write_register(ViPipe, 0x6a, 0x08);
gc2145_write_register(ViPipe, 0x6b, 0x08);
gc2145_write_register(ViPipe, 0x6c, 0x08);
gc2145_write_register(ViPipe, 0x6d, 0x08);
gc2145_write_register(ViPipe, 0x6e, 0x08);
gc2145_write_register(ViPipe, 0x6f, 0x08);
gc2145_write_register(ViPipe, 0x70, 0x08);
gc2145_write_register(ViPipe, 0x71, 0x08);
gc2145_write_register(ViPipe, 0x76, 0x00);
gc2145_write_register(ViPipe, 0x72, 0xf0);
gc2145_write_register(ViPipe, 0x7e, 0x3c);
gc2145_write_register(ViPipe, 0x7f, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0x48, 0x15);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x01, 0x04);
gc2145_write_register(ViPipe, 0x02, 0xc0);
gc2145_write_register(ViPipe, 0x03, 0x04);
gc2145_write_register(ViPipe, 0x04, 0x90);
gc2145_write_register(ViPipe, 0x05, 0x30);
gc2145_write_register(ViPipe, 0x06, 0x90);
gc2145_write_register(ViPipe, 0x07, 0x30);
gc2145_write_register(ViPipe, 0x08, 0x80);
gc2145_write_register(ViPipe, 0x09, 0x00);
gc2145_write_register(ViPipe, 0x0a, 0x82);
gc2145_write_register(ViPipe, 0x0b, 0x11);
gc2145_write_register(ViPipe, 0x0c, 0x10);
gc2145_write_register(ViPipe, 0x11, 0x10);
gc2145_write_register(ViPipe, 0x13, 0x7b);
gc2145_write_register(ViPipe, 0x17, 0x00);
gc2145_write_register(ViPipe, 0x1c, 0x11);
gc2145_write_register(ViPipe, 0x1e, 0x61);
gc2145_write_register(ViPipe, 0x1f, 0x35);
gc2145_write_register(ViPipe, 0x20, 0x40);
gc2145_write_register(ViPipe, 0x22, 0x40);
gc2145_write_register(ViPipe, 0x23, 0x20);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0x0f, 0x04);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x12, 0x35);
gc2145_write_register(ViPipe, 0x15, 0xb0);
gc2145_write_register(ViPipe, 0x10, 0x31);
gc2145_write_register(ViPipe, 0x3e, 0x28);
gc2145_write_register(ViPipe, 0x3f, 0xb0);
gc2145_write_register(ViPipe, 0x40, 0x90);
gc2145_write_register(ViPipe, 0x41, 0x0f);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0x90, 0x6c);
gc2145_write_register(ViPipe, 0x91, 0x03);
gc2145_write_register(ViPipe, 0x92, 0xcb);
gc2145_write_register(ViPipe, 0x94, 0x33);
gc2145_write_register(ViPipe, 0x95, 0x84);
gc2145_write_register(ViPipe, 0x97, 0x65);
gc2145_write_register(ViPipe, 0xa2, 0x11);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0x80, 0xc1);
gc2145_write_register(ViPipe, 0x81, 0x08);
gc2145_write_register(ViPipe, 0x82, 0x05);
gc2145_write_register(ViPipe, 0x83, 0x08);
gc2145_write_register(ViPipe, 0x84, 0x0a);
gc2145_write_register(ViPipe, 0x86, 0xf0);
gc2145_write_register(ViPipe, 0x87, 0x50);
gc2145_write_register(ViPipe, 0x88, 0x15);
gc2145_write_register(ViPipe, 0x89, 0xb0);
gc2145_write_register(ViPipe, 0x8a, 0x30);
gc2145_write_register(ViPipe, 0x8b, 0x10);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x21, 0x04);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0xa3, 0x50);
gc2145_write_register(ViPipe, 0xa4, 0x20);
gc2145_write_register(ViPipe, 0xa5, 0x40);
gc2145_write_register(ViPipe, 0xa6, 0x80);
gc2145_write_register(ViPipe, 0xab, 0x40);
gc2145_write_register(ViPipe, 0xae, 0x0c);
gc2145_write_register(ViPipe, 0xb3, 0x46);
gc2145_write_register(ViPipe, 0xb4, 0x64);
gc2145_write_register(ViPipe, 0xb6, 0x38);
gc2145_write_register(ViPipe, 0xb7, 0x01);
gc2145_write_register(ViPipe, 0xb9, 0x2b);
gc2145_write_register(ViPipe, 0x3c, 0x04);
gc2145_write_register(ViPipe, 0x3d, 0x15);
gc2145_write_register(ViPipe, 0x4b, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x20);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0x10, 0x09);
gc2145_write_register(ViPipe, 0x11, 0x0d);
gc2145_write_register(ViPipe, 0x12, 0x13);
gc2145_write_register(ViPipe, 0x13, 0x19);
gc2145_write_register(ViPipe, 0x14, 0x27);
gc2145_write_register(ViPipe, 0x15, 0x37);
gc2145_write_register(ViPipe, 0x16, 0x45);
gc2145_write_register(ViPipe, 0x17, 0x53);
gc2145_write_register(ViPipe, 0x18, 0x69);
gc2145_write_register(ViPipe, 0x19, 0x7d);
gc2145_write_register(ViPipe, 0x1a, 0x8f);
gc2145_write_register(ViPipe, 0x1b, 0x9d);
gc2145_write_register(ViPipe, 0x1c, 0xa9);
gc2145_write_register(ViPipe, 0x1d, 0xbd);
gc2145_write_register(ViPipe, 0x1e, 0xcd);
gc2145_write_register(ViPipe, 0x1f, 0xd9);
gc2145_write_register(ViPipe, 0x20, 0xe3);
gc2145_write_register(ViPipe, 0x21, 0xea);
gc2145_write_register(ViPipe, 0x22, 0xef);
gc2145_write_register(ViPipe, 0x23, 0xf5);
gc2145_write_register(ViPipe, 0x24, 0xf9);
gc2145_write_register(ViPipe, 0x25, 0xff);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xc6, 0x20);
gc2145_write_register(ViPipe, 0xc7, 0x2b);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0x26, 0x0f);
gc2145_write_register(ViPipe, 0x27, 0x14);
gc2145_write_register(ViPipe, 0x28, 0x19);
gc2145_write_register(ViPipe, 0x29, 0x1e);
gc2145_write_register(ViPipe, 0x2a, 0x27);
gc2145_write_register(ViPipe, 0x2b, 0x33);
gc2145_write_register(ViPipe, 0x2c, 0x3b);
gc2145_write_register(ViPipe, 0x2d, 0x45);
gc2145_write_register(ViPipe, 0x2e, 0x59);
gc2145_write_register(ViPipe, 0x2f, 0x69);
gc2145_write_register(ViPipe, 0x30, 0x7c);
gc2145_write_register(ViPipe, 0x31, 0x89);
gc2145_write_register(ViPipe, 0x32, 0x98);
gc2145_write_register(ViPipe, 0x33, 0xae);
gc2145_write_register(ViPipe, 0x34, 0xc0);
gc2145_write_register(ViPipe, 0x35, 0xcf);
gc2145_write_register(ViPipe, 0x36, 0xda);
gc2145_write_register(ViPipe, 0x37, 0xe2);
gc2145_write_register(ViPipe, 0x38, 0xe9);
gc2145_write_register(ViPipe, 0x39, 0xf3);
gc2145_write_register(ViPipe, 0x3a, 0xf9);
gc2145_write_register(ViPipe, 0x3b, 0xff);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0xd1, 0x32);
gc2145_write_register(ViPipe, 0xd2, 0x32);
gc2145_write_register(ViPipe, 0xd3, 0x40);
gc2145_write_register(ViPipe, 0xd6, 0xf0);
gc2145_write_register(ViPipe, 0xd7, 0x10);
gc2145_write_register(ViPipe, 0xd8, 0xda);
gc2145_write_register(ViPipe, 0xdd, 0x14);
gc2145_write_register(ViPipe, 0xde, 0x86);
gc2145_write_register(ViPipe, 0xed, 0x80);
gc2145_write_register(ViPipe, 0xee, 0x00);
gc2145_write_register(ViPipe, 0xef, 0x3f);
gc2145_write_register(ViPipe, 0xd8, 0xd8);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x9f, 0x40);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0xc2, 0x14);
gc2145_write_register(ViPipe, 0xc3, 0x0d);
gc2145_write_register(ViPipe, 0xc4, 0x0c);
gc2145_write_register(ViPipe, 0xc8, 0x15);
gc2145_write_register(ViPipe, 0xc9, 0x0d);
gc2145_write_register(ViPipe, 0xca, 0x0a);
gc2145_write_register(ViPipe, 0xbc, 0x24);
gc2145_write_register(ViPipe, 0xbd, 0x10);
gc2145_write_register(ViPipe, 0xbe, 0x0b);
gc2145_write_register(ViPipe, 0xb6, 0x25);
gc2145_write_register(ViPipe, 0xb7, 0x16);
gc2145_write_register(ViPipe, 0xb8, 0x15);
gc2145_write_register(ViPipe, 0xc5, 0x00);
gc2145_write_register(ViPipe, 0xc6, 0x00);
gc2145_write_register(ViPipe, 0xc7, 0x00);
gc2145_write_register(ViPipe, 0xcb, 0x00);
gc2145_write_register(ViPipe, 0xcc, 0x00);
gc2145_write_register(ViPipe, 0xcd, 0x00);
gc2145_write_register(ViPipe, 0xbf, 0x07);
gc2145_write_register(ViPipe, 0xc0, 0x00);
gc2145_write_register(ViPipe, 0xc1, 0x00);
gc2145_write_register(ViPipe, 0xb9, 0x00);
gc2145_write_register(ViPipe, 0xba, 0x00);
gc2145_write_register(ViPipe, 0xbb, 0x00);
gc2145_write_register(ViPipe, 0xaa, 0x01);
gc2145_write_register(ViPipe, 0xab, 0x01);
gc2145_write_register(ViPipe, 0xac, 0x00);
gc2145_write_register(ViPipe, 0xad, 0x05);
gc2145_write_register(ViPipe, 0xae, 0x06);
gc2145_write_register(ViPipe, 0xaf, 0x0e);
gc2145_write_register(ViPipe, 0xb0, 0x0b);
gc2145_write_register(ViPipe, 0xb1, 0x07);
gc2145_write_register(ViPipe, 0xb2, 0x06);
gc2145_write_register(ViPipe, 0xb3, 0x17);
gc2145_write_register(ViPipe, 0xb4, 0x0e);
gc2145_write_register(ViPipe, 0xb5, 0x0e);
gc2145_write_register(ViPipe, 0xd0, 0x09);
gc2145_write_register(ViPipe, 0xd1, 0x00);
gc2145_write_register(ViPipe, 0xd2, 0x00);
gc2145_write_register(ViPipe, 0xd6, 0x08);
gc2145_write_register(ViPipe, 0xd7, 0x00);
gc2145_write_register(ViPipe, 0xd8, 0x00);
gc2145_write_register(ViPipe, 0xd9, 0x00);
gc2145_write_register(ViPipe, 0xda, 0x00);
gc2145_write_register(ViPipe, 0xdb, 0x00);
gc2145_write_register(ViPipe, 0xd3, 0x0a);
gc2145_write_register(ViPipe, 0xd4, 0x00);
gc2145_write_register(ViPipe, 0xd5, 0x00);
gc2145_write_register(ViPipe, 0xa4, 0x00);
gc2145_write_register(ViPipe, 0xa5, 0x00);
gc2145_write_register(ViPipe, 0xa6, 0x77);
gc2145_write_register(ViPipe, 0xa7, 0x77);
gc2145_write_register(ViPipe, 0xa8, 0x77);
gc2145_write_register(ViPipe, 0xa9, 0x77);
gc2145_write_register(ViPipe, 0xa1, 0x80);
gc2145_write_register(ViPipe, 0xa2, 0x80);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0xdf, 0x0d);
gc2145_write_register(ViPipe, 0xdc, 0x25);
gc2145_write_register(ViPipe, 0xdd, 0x30);
gc2145_write_register(ViPipe, 0xe0, 0x77);
gc2145_write_register(ViPipe, 0xe1, 0x80);
gc2145_write_register(ViPipe, 0xe2, 0x77);
gc2145_write_register(ViPipe, 0xe3, 0x90);
gc2145_write_register(ViPipe, 0xe6, 0x90);
gc2145_write_register(ViPipe, 0xe7, 0xa0);
gc2145_write_register(ViPipe, 0xe8, 0x90);
gc2145_write_register(ViPipe, 0xe9, 0xa0);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x4f, 0x00);
gc2145_write_register(ViPipe, 0x4f, 0x00);
gc2145_write_register(ViPipe, 0x4b, 0x01);
gc2145_write_register(ViPipe, 0x4f, 0x00);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x71);
gc2145_write_register(ViPipe, 0x4e, 0x01);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x91);
gc2145_write_register(ViPipe, 0x4e, 0x01);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x70);
gc2145_write_register(ViPipe, 0x4e, 0x01);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x90);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xb0);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x8f);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x6f);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xaf);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xd0);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xf0);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xcf);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xef);
gc2145_write_register(ViPipe, 0x4e, 0x02);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x6e);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x8e);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xae);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xce);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x4d);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x6d);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x8d);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xad);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xcd);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x4c);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x6c);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x8c);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xac);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xcc);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xcb);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x4b);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x6b);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x8b);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xab);
gc2145_write_register(ViPipe, 0x4e, 0x03);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x8a);
gc2145_write_register(ViPipe, 0x4e, 0x04);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xaa);
gc2145_write_register(ViPipe, 0x4e, 0x04);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xca);
gc2145_write_register(ViPipe, 0x4e, 0x04);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xca);
gc2145_write_register(ViPipe, 0x4e, 0x04);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xc9);
gc2145_write_register(ViPipe, 0x4e, 0x04);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x8a);
gc2145_write_register(ViPipe, 0x4e, 0x04);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0x89);
gc2145_write_register(ViPipe, 0x4e, 0x04);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xa9);
gc2145_write_register(ViPipe, 0x4e, 0x04);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x0b);
gc2145_write_register(ViPipe, 0x4e, 0x05);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x0a);
gc2145_write_register(ViPipe, 0x4e, 0x05);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xeb);
gc2145_write_register(ViPipe, 0x4e, 0x05);
gc2145_write_register(ViPipe, 0x4c, 0x01);
gc2145_write_register(ViPipe, 0x4d, 0xea);
gc2145_write_register(ViPipe, 0x4e, 0x05);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x09);
gc2145_write_register(ViPipe, 0x4e, 0x05);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x29);
gc2145_write_register(ViPipe, 0x4e, 0x05);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x2a);
gc2145_write_register(ViPipe, 0x4e, 0x05);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x4a);
gc2145_write_register(ViPipe, 0x4e, 0x05);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x8a);
gc2145_write_register(ViPipe, 0x4e, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x49);
gc2145_write_register(ViPipe, 0x4e, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x69);
gc2145_write_register(ViPipe, 0x4e, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x89);
gc2145_write_register(ViPipe, 0x4e, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xa9);
gc2145_write_register(ViPipe, 0x4e, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x48);
gc2145_write_register(ViPipe, 0x4e, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x68);
gc2145_write_register(ViPipe, 0x4e, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0x69);
gc2145_write_register(ViPipe, 0x4e, 0x06);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xca);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xc9);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xe9);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x03);
gc2145_write_register(ViPipe, 0x4d, 0x09);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xc8);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xe8);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xa7);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xc7);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x02);
gc2145_write_register(ViPipe, 0x4d, 0xe7);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4c, 0x03);
gc2145_write_register(ViPipe, 0x4d, 0x07);
gc2145_write_register(ViPipe, 0x4e, 0x07);
gc2145_write_register(ViPipe, 0x4f, 0x01);
gc2145_write_register(ViPipe, 0x50, 0x80);
gc2145_write_register(ViPipe, 0x51, 0xa8);
gc2145_write_register(ViPipe, 0x52, 0x47);
gc2145_write_register(ViPipe, 0x53, 0x38);
gc2145_write_register(ViPipe, 0x54, 0xc7);
gc2145_write_register(ViPipe, 0x56, 0x0e);
gc2145_write_register(ViPipe, 0x58, 0x08);
gc2145_write_register(ViPipe, 0x5b, 0x00);
gc2145_write_register(ViPipe, 0x5c, 0x74);
gc2145_write_register(ViPipe, 0x5d, 0x8b);
gc2145_write_register(ViPipe, 0x61, 0xdb);
gc2145_write_register(ViPipe, 0x62, 0xb8);
gc2145_write_register(ViPipe, 0x63, 0x86);
gc2145_write_register(ViPipe, 0x64, 0xc0);
gc2145_write_register(ViPipe, 0x65, 0x04);
gc2145_write_register(ViPipe, 0x67, 0xa8);
gc2145_write_register(ViPipe, 0x68, 0xb0);
gc2145_write_register(ViPipe, 0x69, 0x00);
gc2145_write_register(ViPipe, 0x6a, 0xa8);
gc2145_write_register(ViPipe, 0x6b, 0xb0);
gc2145_write_register(ViPipe, 0x6c, 0xaf);
gc2145_write_register(ViPipe, 0x6d, 0x8b);
gc2145_write_register(ViPipe, 0x6e, 0x50);
gc2145_write_register(ViPipe, 0x6f, 0x18);
gc2145_write_register(ViPipe, 0x73, 0xf0);
gc2145_write_register(ViPipe, 0x70, 0x0d);
gc2145_write_register(ViPipe, 0x71, 0x60);
gc2145_write_register(ViPipe, 0x72, 0x80);
gc2145_write_register(ViPipe, 0x74, 0x01);
gc2145_write_register(ViPipe, 0x75, 0x01);
gc2145_write_register(ViPipe, 0x7f, 0x0c);
gc2145_write_register(ViPipe, 0x76, 0x70);
gc2145_write_register(ViPipe, 0x77, 0x58);
gc2145_write_register(ViPipe, 0x78, 0xa0);
gc2145_write_register(ViPipe, 0x79, 0x5e);
gc2145_write_register(ViPipe, 0x7a, 0x54);
gc2145_write_register(ViPipe, 0x7b, 0x58);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0xc0, 0x01);
gc2145_write_register(ViPipe, 0xc1, 0x44);
gc2145_write_register(ViPipe, 0xc2, 0xfd);
gc2145_write_register(ViPipe, 0xc3, 0x04);
gc2145_write_register(ViPipe, 0xc4, 0xF0);
gc2145_write_register(ViPipe, 0xc5, 0x48);
gc2145_write_register(ViPipe, 0xc6, 0xfd);
gc2145_write_register(ViPipe, 0xc7, 0x46);
gc2145_write_register(ViPipe, 0xc8, 0xfd);
gc2145_write_register(ViPipe, 0xc9, 0x02);
gc2145_write_register(ViPipe, 0xca, 0xe0);
gc2145_write_register(ViPipe, 0xcb, 0x45);
gc2145_write_register(ViPipe, 0xcc, 0xec);
gc2145_write_register(ViPipe, 0xcd, 0x48);
gc2145_write_register(ViPipe, 0xce, 0xf0);
gc2145_write_register(ViPipe, 0xcf, 0xf0);
gc2145_write_register(ViPipe, 0xe3, 0x0c);
gc2145_write_register(ViPipe, 0xe4, 0x4b);
gc2145_write_register(ViPipe, 0xe5, 0xe0);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x9f, 0x40);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xf2, 0x0f);
gc2145_write_register(ViPipe, 0xfe, 0x02);
gc2145_write_register(ViPipe, 0x40, 0xbf);
gc2145_write_register(ViPipe, 0x46, 0xcf);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0x05, 0x01);
gc2145_write_register(ViPipe, 0x06, 0x56);
gc2145_write_register(ViPipe, 0x07, 0x00);
gc2145_write_register(ViPipe, 0x08, 0x32);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x25, 0x00);
gc2145_write_register(ViPipe, 0x26, 0xfa);
gc2145_write_register(ViPipe, 0x27, 0x04);
gc2145_write_register(ViPipe, 0x28, 0xe2);
gc2145_write_register(ViPipe, 0x29, 0x06);
gc2145_write_register(ViPipe, 0x2a, 0xd6);
gc2145_write_register(ViPipe, 0x2b, 0x07);
gc2145_write_register(ViPipe, 0x2c, 0xd0);
gc2145_write_register(ViPipe, 0x2d, 0x0b);
gc2145_write_register(ViPipe, 0x2e, 0xb8);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xfd, 0x00);
gc2145_write_register(ViPipe, 0xf8, 0x82);
gc2145_write_register(ViPipe, 0xfa, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0x90, 0x01);
gc2145_write_register(ViPipe, 0x91, 0x00);
gc2145_write_register(ViPipe, 0x92, 0x00);
gc2145_write_register(ViPipe, 0x93, 0x00);
gc2145_write_register(ViPipe, 0x94, 0x00);
gc2145_write_register(ViPipe, 0x95, 0x04);
gc2145_write_register(ViPipe, 0x96, 0xb0);
gc2145_write_register(ViPipe, 0x97, 0x06);
gc2145_write_register(ViPipe, 0x98, 0x40);
gc2145_write_register(ViPipe, 0x99, 0x11);
gc2145_write_register(ViPipe, 0x9a, 0x06);
gc2145_write_register(ViPipe, 0x9b, 0x00);
gc2145_write_register(ViPipe, 0x9c, 0x00);
gc2145_write_register(ViPipe, 0x9d, 0x00);
gc2145_write_register(ViPipe, 0x9e, 0x00);
gc2145_write_register(ViPipe, 0x9f, 0x00);
gc2145_write_register(ViPipe, 0xa0, 0x00);
gc2145_write_register(ViPipe, 0xa1, 0x00);
gc2145_write_register(ViPipe, 0xa2, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0xec, 0x06);
gc2145_write_register(ViPipe, 0xed, 0x04);
gc2145_write_register(ViPipe, 0xee, 0x60);
gc2145_write_register(ViPipe, 0xef, 0x90);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x74, 0x01);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x01, 0x04);
gc2145_write_register(ViPipe, 0x02, 0xc0);
gc2145_write_register(ViPipe, 0x03, 0x04);
gc2145_write_register(ViPipe, 0x04, 0x90);
gc2145_write_register(ViPipe, 0x05, 0x30);
gc2145_write_register(ViPipe, 0x06, 0x90);
gc2145_write_register(ViPipe, 0x07, 0x30);
gc2145_write_register(ViPipe, 0x08, 0x80);
gc2145_write_register(ViPipe, 0x0a, 0x82);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x21, 0x15);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0x20, 0x15);
gc2145_write_register(ViPipe, 0xfe, 0x00);
gc2145_write_register(ViPipe, 0x05, 0x01);
gc2145_write_register(ViPipe, 0x06, 0x2f);
gc2145_write_register(ViPipe, 0x07, 0x00);
gc2145_write_register(ViPipe, 0x08, 0x64);
gc2145_write_register(ViPipe, 0xfe, 0x01);
gc2145_write_register(ViPipe, 0x25, 0x00);
gc2145_write_register(ViPipe, 0x26, 0xa0);
gc2145_write_register(ViPipe, 0x27, 0x05);
gc2145_write_register(ViPipe, 0x28, 0x00);
gc2145_write_register(ViPipe, 0x29, 0x05);
gc2145_write_register(ViPipe, 0x2a, 0x00);
gc2145_write_register(ViPipe, 0x2b, 0x05);
gc2145_write_register(ViPipe, 0x2c, 0x00);
gc2145_write_register(ViPipe, 0x2d, 0x05);
gc2145_write_register(ViPipe, 0x2e, 0x00);
gc2145_write_register(ViPipe, 0xfe, 0x00);
delay_ms(100);
printf("ViPipe:%d,===GC2145 1200P 12fps YUV Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/gcore_gc4023/Makefile Normal file
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@ -0,0 +1,36 @@
SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc4023.a
TARGET_SO = $(MW_LIB)/libsns_gc4023.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

934
middleware/v2/component/isp/sensor/cv180x/gcore_gc4023/gc4023_cmos.c Normal file
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@ -0,0 +1,934 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "gc4023_cmos_ex.h"
#include "gc4023_cmos_param.h"
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#include "cvi_type.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#include <linux/cvi_type.h>
#endif
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define GC4023_ID 4023
#define GC4023_I2C_ADDR_1 0x21
#define GC4023_I2C_ADDR_2 0x29
#define GC4023_I2C_ADDR_IS_VALID(addr) ((addr) == GC4023_I2C_ADDR_1 || (addr) == GC4023_I2C_ADDR_2)
/****************************************************************************
* global variables *
***************************************************************************/
ISP_SNS_STATE_S *g_pastGc4023[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define GC4023_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc4023[dev])
#define GC4023_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc4023[dev] = pstCtx)
#define GC4023_SENSOR_RESET_CTX(dev) (g_pastGc4023[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunGc4023_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 3},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc4023_MirrorFip[VI_MAX_PIPE_NUM] = {ISP_SNS_NORMAL};
CVI_U16 g_au16Gc4023_GainMode[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
***************************************************************************/
static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = {
[0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE
};
static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Gc4023 Lines Range*****/
#define GC4023_FULL_LINES_MAX (0x3fff)
/*****Gc4023 Register Address*****/
#define GC4023_EXP_H_ADDR 0x0202 //bit[13:8]
#define GC4023_EXP_L_ADDR 0x0203
#define GC4023_AGAIN_H_ADDR 0x0615 //bit[11:8]
#define GC4023_AGAIN_L_ADDR 0x0614
#define GC4023_COL_AGAIN_H_ADDR 0x00b8 //bit[13:8]
#define GC4023_COL_AGAIN_L_ADDR 0x00b9
#define GC4023_AGAIN_MAG1_ADDR 0x0218
#define GC4023_AGAIN_MAG2_ADDR 0x1467
#define GC4023_AGAIN_MAG3_ADDR 0x1468
#define GC4023_VTS_H_ADDR 0x0340 //bit[13:8]
#define GC4023_VTS_L_ADDR 0x0341
#define GC4023_MIRROR_FLIP_ADDR 0x022c
#define GC4023_OTP_MIRROR_FLIP_ADDR 0x0a73
#define GC4023_RES_IS_1440P(w, h) ((w) <= 2560 && (h) <= 1440)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = GC4023_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = g_astGc4023_mode[GC4023_MODE_2560X1440P30].f32MaxFps;
pstAeSnsDft->f32MinFps = g_astGc4023_mode[GC4023_MODE_2560X1440P30].f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = 60880;
pstAeSnsDft->u32MinAgain = 1024;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = 1024;
pstAeSnsDft->u32MinDgain = 1024;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
g_au32InitExposure[ViPipe] : g_astGc4023_mode[GC4023_MODE_2560X1440P30].stExp[0].u16Def;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstAeSnsDft->u32MinIntTime = g_astGc4023_mode[GC4023_MODE_2560X1440P30].stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_astGc4023_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_astGc4023_mode[pstSnsState->u8ImgMode].f32MaxFps;
f32MinFps = g_astGc4023_mode[pstSnsState->u8ImgMode].f32MinFps;
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > GC4023_FULL_LINES_MAX) ? GC4023_FULL_LINES_MAX : u32VMAX;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_VTS_H].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_L].u32Data = (u32VMAX & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_H].u32Data = (u32IntTime[0] >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_L].u32Data = (u32IntTime[0] & 0xFF);
return CVI_SUCCESS;
}
static CVI_U32 regValTable[25][7] = {
/*[reg] 0x0614 0x0615 0x0218 0x1467 0x1468 0x00b8 0x00b9*/
{0x00, 0x00, 0x00, 0x0D, 0x15, 0x01, 0x00},
{0x80, 0x02, 0x00, 0x0D, 0x15, 0x01, 0x0B},
{0x01, 0x00, 0x00, 0x0D, 0x15, 0x01, 0x19},
{0x81, 0x02, 0x00, 0x0E, 0x16, 0x01, 0x2A},
{0x02, 0x00, 0x00, 0x0E, 0x16, 0x02, 0x00},
{0x82, 0x02, 0x00, 0x0F, 0x17, 0x02, 0x17},
{0x03, 0x00, 0x00, 0x10, 0x18, 0x02, 0x33},
{0x83, 0x02, 0x00, 0x11, 0x19, 0x03, 0x14},
{0x04, 0x00, 0x00, 0x12, 0x1a, 0x04, 0x00},
{0x80, 0x02, 0x20, 0x13, 0x1b, 0x04, 0x2F},
{0x01, 0x00, 0x20, 0x14, 0x1c, 0x05, 0x26},
{0x81, 0x02, 0x20, 0x15, 0x1d, 0x06, 0x28},
{0x02, 0x00, 0x20, 0x16, 0x1e, 0x08, 0x00},
{0x82, 0x02, 0x20, 0x16, 0x1e, 0x09, 0x1E},
{0x03, 0x00, 0x20, 0x18, 0x20, 0x0B, 0x0C},
{0x83, 0x02, 0x20, 0x18, 0x20, 0x0D, 0x11},
{0x04, 0x00, 0x20, 0x18, 0x20, 0x10, 0x00},
{0x84, 0x02, 0x20, 0x19, 0x21, 0x12, 0x3D},
{0x05, 0x00, 0x20, 0x19, 0x21, 0x16, 0x19},
{0x85, 0x02, 0x20, 0x1A, 0x22, 0x1A, 0x22},
{0xb5, 0x04, 0x20, 0x1B, 0x23, 0x20, 0x00},
{0x85, 0x05, 0x20, 0x1B, 0x23, 0x25, 0x3A},
{0x05, 0x08, 0x20, 0x1C, 0x24, 0x2C, 0x33},
{0x45, 0x09, 0x20, 0x1D, 0x25, 0x35, 0x05},
{0x55, 0x0a, 0x20, 0x1F, 0x27, 0x40, 0x00},
};
static CVI_U32 gain_table[25] = {
16*64,
16*76,
16*90,
16*107,
16*125,
16*148,
16*177,
16*211,
16*245,
16*301,
16*362,
16*439,
16*526,
16*634,
16*756,
16*891,
16*1026,
16*1205,
16*1408,
16*1655,
16*1962,
16*2106,
16*2733,
16*3222,
16*3805,
};
int total = sizeof(gain_table) / sizeof(CVI_U32);
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
int i;
UNUSED(ViPipe);
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
if (*pu32AgainLin >= gain_table[total - 1]) {
*pu32AgainDb = total - 1;
*pu32AgainLin = gain_table[total - 1];
return CVI_SUCCESS;
}
for (i = 0; i < total; i++) {
if (*pu32AgainLin < gain_table[i]) {
*pu32AgainDb = i - 1;
break;
}
}
*pu32AgainLin = gain_table[i - 1];
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
UNUSED(ViPipe);
*pu32DgainLin = 1024;
*pu32DgainDb = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32Again;
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* only surpport linear mode */
u32Again = pu32Again[0];
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_L].u32Data = regValTable[u32Again][0];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_H].u32Data = regValTable[u32Again][1];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_MAG1].u32Data = regValTable[u32Again][2];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_MAG2].u32Data = regValTable[u32Again][3];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_MAG3].u32Data = regValTable[u32Again][4];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_H].u32Data = regValTable[u32Again][5];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_L].u32Data = regValTable[u32Again][6];
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
{
UNUSED(ViPipe);
UNUSED(u16ManRatioEnable);
UNUSED(au32Ratio);
UNUSED(au32IntTimeMax);
UNUSED(au32IntTimeMin);
UNUSED(pu32LFMaxIntTime);
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode\n");
return CVI_SUCCESS;
}
/* Only used in LINE_WDR mode */
static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr)
{
CMOS_CHECK_POINTER(pstAeFSWDRAttr);
genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode;
gu32MaxTimeGetCnt[ViPipe] = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
memcpy(pstDef->stNoiseCalibration.CalibrationCoef,
&g_stIspNoiseCalibratio, sizeof(ISP_CMOS_NOISE_CALIBRATION_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
UNUSED(ViPipe);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const GC4023_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astGc4023_mode[pstSnsState->u8ImgMode];
if (pstSnsState->enWDRMode != WDR_MODE_NONE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
} else {
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
UNUSED(ViPipe);
UNUSED(u8Mode);
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunGc4023_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = gc4023_i2c_addr;
pstI2c_data[i].u32AddrByteNum = gc4023_addr_byte;
pstI2c_data[i].u32DataByteNum = gc4023_data_byte;
}
pstI2c_data[LINEAR_EXP_H].u32RegAddr = GC4023_EXP_H_ADDR;
pstI2c_data[LINEAR_EXP_L].u32RegAddr = GC4023_EXP_L_ADDR;
pstI2c_data[LINEAR_AGAIN_H].u32RegAddr = GC4023_AGAIN_H_ADDR;
pstI2c_data[LINEAR_AGAIN_L].u32RegAddr = GC4023_AGAIN_L_ADDR;
pstI2c_data[LINEAR_AGAIN_MAG1].u32RegAddr = GC4023_AGAIN_MAG1_ADDR;
pstI2c_data[LINEAR_AGAIN_MAG2].u32RegAddr = GC4023_AGAIN_MAG2_ADDR;
pstI2c_data[LINEAR_AGAIN_MAG3].u32RegAddr = GC4023_AGAIN_MAG3_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_H].u32RegAddr = GC4023_COL_AGAIN_H_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_L].u32RegAddr = GC4023_COL_AGAIN_L_ADDR;
pstI2c_data[LINEAR_VTS_H].u32RegAddr = GC4023_VTS_H_ADDR;
pstI2c_data[LINEAR_VTS_L].u32RegAddr = GC4023_VTS_L_ADDR;
pstI2c_data[LINEAR_MIRROR_FLIP].u32RegAddr = GC4023_MIRROR_FLIP_ADDR;
pstI2c_data[LINEAR_OTP_MIRROR_FLIP].u32RegAddr = GC4023_OTP_MIRROR_FLIP_ADDR;
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0, shutterUpdate = 0, vtsUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
//if ((i >= LINEAR_AGAIN_H) && (i <= LINEAR_DGAIN_L))
if ((i >= LINEAR_AGAIN_H) && (i <= LINEAR_COL_AGAIN_L))
gainsUpdate = 1;
if (i <= LINEAR_EXP_L)
shutterUpdate = 1;
if ((i >= LINEAR_VTS_H) && (i <= LINEAR_VTS_L))
vtsUpdate = 1;
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_MAG1].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_MAG2].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_MAG3].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_L].bUpdate = CVI_TRUE;
}
if (shutterUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_L].bUpdate = CVI_TRUE;
}
if (vtsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_L].bUpdate = CVI_TRUE;
}
/* check update isp crop or not */
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
pstCfg0->snsCfg.astI2cData[LINEAR_MIRROR_FLIP].bDropFrm = CVI_FALSE;
pstCfg0->snsCfg.astI2cData[LINEAR_OTP_MIRROR_FLIP].bDropFrm = CVI_FALSE;
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 30) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (GC4023_RES_IS_1440P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = GC4023_MODE_2560X1440P30;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps);
return CVI_FAILURE;
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U8 value, otp_value;
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeGc4023_MirrorFip[ViPipe] != eSnsMirrorFlip) {
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
value = 0;
otp_value = 0x60;
break;
case ISP_SNS_MIRROR:
value = 0x01;
otp_value = 0x61;
break;
case ISP_SNS_FLIP:
value = 0x02;
otp_value = 0x62;
break;
case ISP_SNS_MIRROR_FLIP:
value = 0x03;
otp_value = 0x63;
break;
default:
return;
}
pstSnsRegsInfo->astI2cData[LINEAR_MIRROR_FLIP].u32Data = value;
pstSnsRegsInfo->astI2cData[LINEAR_OTP_MIRROR_FLIP].u32Data = otp_value;
pstSnsRegsInfo->astI2cData[LINEAR_MIRROR_FLIP].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[LINEAR_MIRROR_FLIP].u8DropFrmNum = 1;
pstSnsRegsInfo->astI2cData[LINEAR_OTP_MIRROR_FLIP].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[LINEAR_OTP_MIRROR_FLIP].u8DropFrmNum = 1;
g_aeGc4023_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = GC4023_MODE_2560X1440P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astGc4023_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[0] = g_astGc4023_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[1] = g_astGc4023_mode[pstSnsState->u8ImgMode].u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC4023_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &gc4023_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_astGc4023_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astGc4023_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc4023_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = gc4023_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = gc4023_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (GC4023_I2C_ADDR_IS_VALID(s32I2cAddr))
gc4023_i2c_addr = s32I2cAddr;
}
static CVI_S32 gc4023_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunGc4023_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC4023_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
GC4023_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC4023_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
GC4023_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = GC4023_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC4023_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, GC4023_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, GC4023_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Gc4023_GainMode[ViPipe] = pstInitAttr->enGainMode;
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return gc4023_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsGc4023_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = gc4023_standby,
.pfnRestart = gc4023_restart,
.pfnWriteReg = gc4023_write_register,
.pfnReadReg = gc4023_read_register,
.pfnSetBusInfo = gc4023_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = sensor_probe,
};

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#ifndef __GC4023_CMOS_EX_H_
#define __GC4023_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#ifndef UNUSED
#define UNUSED(x) ((void)(x))
#endif
enum gc4023_linear_regs_e {
LINEAR_EXP_H,
LINEAR_EXP_L,
LINEAR_AGAIN_L,
LINEAR_AGAIN_H,
LINEAR_AGAIN_MAG1,
LINEAR_AGAIN_MAG2,
LINEAR_AGAIN_MAG3,
LINEAR_COL_AGAIN_H,
LINEAR_COL_AGAIN_L,
LINEAR_VTS_H,
LINEAR_VTS_L,
LINEAR_MIRROR_FLIP,
LINEAR_OTP_MIRROR_FLIP,
LINEAR_REGS_NUM
};
typedef enum _GC4023_MODE_E {
GC4023_MODE_2560X1440P30 = 0,
GC4023_MODE_LINEAR_NUM,
GC4023_MODE_NUM
} GC4023_MODE_E;
typedef struct _GC4023_STATE_S {
CVI_U32 u32Sexp_MAX;
} GC4023_STATE_S;
typedef struct _GC4023_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
char name[64];
} GC4023_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc4023[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc4023_BusInfo[];
extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc4023_MirrorFip[VI_MAX_PIPE_NUM];
extern CVI_U8 gc4023_i2c_addr;
extern const CVI_U32 gc4023_addr_byte;
extern const CVI_U32 gc4023_data_byte;
extern void gc4023_init(VI_PIPE ViPipe);
extern void gc4023_exit(VI_PIPE ViPipe);
extern void gc4023_standby(VI_PIPE ViPipe);
extern void gc4023_restart(VI_PIPE ViPipe);
extern int gc4023_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc4023_read_register(VI_PIPE ViPipe, int addr);
extern int gc4023_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC4023_CMOS_EX_H_ */

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#ifndef __GC4023_CMOS_PARAM_H_
#define __GC4023_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc4023_cmos_ex.h"
static const GC4023_MODE_S g_astGc4023_mode[GC4023_MODE_NUM] = {
[GC4023_MODE_2560X1440P30] = {
.name = "2560X1440P30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.f32MaxFps = 30,
.f32MinFps = 5.49, /* 1500 * 30 / 8191*/
.u32HtsDef = 2400,
.u32VtsDef = 1500,
.stExp[0] = {
.u16Min = 1,
.u16Max = 0x3fff,
.u16Def = 100,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 16*3805,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 1024,
.u32Def = 1024,
.u32Step = 1,
},
},
};
static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = {
{ //iso 100
{0.04006369039416313171, 5.73531675338745117188}, //B: slope, intercept
{0.03064448758959770203, 8.56994438171386718750}, //Gb: slope, intercept
{0.03068985790014266968, 8.82220363616943359375}, //Gr: slope, intercept
{0.03361049667000770569, 7.20687675476074218750}, //R: slope, intercept
},
{ //iso 200
{0.05054308474063873291, 7.91628408432006835938}, //B: slope, intercept
{0.03632996603846549988, 13.05291843414306640625}, //Gb: slope, intercept
{0.03697143867611885071, 12.49540805816650390625}, //Gr: slope, intercept
{0.04156460240483283997, 10.44298553466796875000}, //R: slope, intercept
},
{ //iso 400
{0.06805337965488433838, 11.55693244934082031250}, //B: slope, intercept
{0.04390667378902435303, 18.59673881530761718750}, //Gb: slope, intercept
{0.04630871489644050598, 17.90183258056640625000}, //Gr: slope, intercept
{0.05292420834302902222, 15.17318439483642578125}, //R: slope, intercept
},
{ //iso 800
{0.08635756373405456543, 17.79124641418457031250}, //B: slope, intercept
{0.05776864662766456604, 26.76541900634765625000}, //Gb: slope, intercept
{0.05839699879288673401, 26.44194030761718750000}, //Gr: slope, intercept
{0.06750740110874176025, 22.42554473876953125000}, //R: slope, intercept
},
{ //iso 1600
{0.12254384160041809082, 26.20610046386718750000}, //B: slope, intercept
{0.07916855812072753906, 39.39273834228515625000}, //Gb: slope, intercept
{0.07857896387577056885, 39.03499984741210937500}, //Gr: slope, intercept
{0.09273355454206466675, 33.09597778320312500000}, //R: slope, intercept
},
{ //iso 3200
{0.18002016842365264893, 34.86975860595703125000}, //B: slope, intercept
{0.10951708257198333740, 54.58878326416015625000}, //Gb: slope, intercept
{0.10485322028398513794, 57.16654205322265625000}, //Gr: slope, intercept
{0.13257601857185363770, 46.27093505859375000000}, //R: slope, intercept
},
{ //iso 6400
{0.24713687598705291748, 48.62341690063476562500}, //B: slope, intercept
{0.14974890649318695068, 77.06428527832031250000}, //Gb: slope, intercept
{0.14544390141963958740, 76.57913970947265625000}, //Gr: slope, intercept
{0.19056233763694763184, 62.13500213623046875000}, //R: slope, intercept
},
{ //iso 12800
{0.37728109955787658691, 58.15543365478515625000}, //B: slope, intercept
{0.20440576970577239990, 100.45700073242187500000}, //Gb: slope, intercept
{0.20059910416603088379, 102.35488891601562500000}, //Gr: slope, intercept
{0.27388775348663330078, 79.65499877929687500000}, //R: slope, intercept
},
{ //iso 25600
{0.36612421274185180664, 115.28938293457031250000}, //B: slope, intercept
{0.22633622586727142334, 164.58416748046875000000}, //Gb: slope, intercept
{0.21590474247932434082, 168.92042541503906250000}, //Gr: slope, intercept
{0.33193346858024597168, 127.92090606689453125000}, //R: slope, intercept
},
{ //iso 51200
{0.48242908716201782227, 147.39015197753906250000}, //B: slope, intercept
{0.28994381427764892578, 223.02711486816406250000}, //Gb: slope, intercept
{0.29200506210327148438, 220.64030456542968750000}, //Gr: slope, intercept
{0.42304891347885131836, 173.74638366699218750000}, //R: slope, intercept
},
{ //iso 102400
{0.62099909782409667969, 130.97862243652343750000}, //B: slope, intercept
{0.39534106850624084473, 219.74490356445312500000}, //Gb: slope, intercept
{0.39458695054054260254, 213.37374877929687500000}, //Gr: slope, intercept
{0.55690109729766845703, 158.37773132324218750000}, //R: slope, intercept
},
{ //iso 204800
{0.75350415706634521484, 77.81707000732421875000}, //B: slope, intercept
{0.52716732025146484375, 148.77879333496093750000}, //Gb: slope, intercept
{0.51073729991912841797, 153.86495971679687500000}, //Gr: slope, intercept
{0.68910604715347290039, 102.12422180175781250000}, //R: slope, intercept
},
{ //iso 409600
{0.90276730060577392578, 43.78258514404296875000}, //B: slope, intercept
{0.62851423025131225586, 119.41429138183593750000}, //Gb: slope, intercept
{0.64918899536132812500, 110.74241638183593750000}, //Gr: slope, intercept
{0.80880594253540039063, 68.89983367919921875000}, //R: slope, intercept
},
{ //iso 819200
{0.90276730060577392578, 43.78258514404296875000}, //B: slope, intercept
{0.62851423025131225586, 119.41429138183593750000}, //Gb: slope, intercept
{0.64918899536132812500, 110.74241638183593750000}, //Gr: slope, intercept
{0.80880594253540039063, 68.89983367919921875000}, //R: slope, intercept
},
{ //iso 1638400
{0.90276730060577392578, 43.78258514404296875000}, //B: slope, intercept
{0.62851423025131225586, 119.41429138183593750000}, //Gb: slope, intercept
{0.64918899536132812500, 110.74241638183593750000}, //Gr: slope, intercept
{0.80880594253540039063, 68.89983367919921875000}, //R: slope, intercept
},
{ //iso 3276800
{0.90276730060577392578, 43.78258514404296875000}, //B: slope, intercept
{0.62851423025131225586, 119.41429138183593750000}, //Gb: slope, intercept
{0.64918899536132812500, 110.74241638183593750000}, //Gr: slope, intercept
{0.80880594253540039063, 68.89983367919921875000}, //R: slope, intercept
},
} };
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {252, 252, 252, 252, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1091, 1091, 1091, 1091
#endif
},
.stAuto = {
{252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252 },
{252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252 },
{252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252 },
{252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252, 252 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091,
1091, 1091},
{1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091,
1091, 1091},
{1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091,
1091, 1091},
{1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091, 1091,
1091, 1091},
#endif
},
},
};
struct combo_dev_attr_s gc4023_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {2, 1, 3, -1, -1},
.pn_swap = {1, 1, 1, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC4023_CMOS_PARAM_H_ */

397
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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc4023_cmos_ex.h"
#define GC4023_CHIP_ID_ADDR_H 0x03f0
#define GC4023_CHIP_ID_ADDR_L 0x03f1
#define GC4023_CHIP_ID 0x4023
#define GC4023_MIRROR_NORMAL
#if defined(GC4023_MIRROR_NORMAL)
#define MIRROR 0x00
#define OTP_MIRROR 0x60
#elif defined(GC4023_MIRROR_H)
#define MIRROR 0x01
#define OTP_MIRROR 0x61
#elif defined(GC4023_MIRROR_V)
#define MIRROR 0x02
#define OTP_MIRROR 0x62
#elif defined(GC4023_MIRROR_HV)
#define MIRROR 0x03
#define OTP_MIRROR 0x63
#else
#define MIRROR 0x00
#define OTP_MIRROR 0x60
#endif
static void gc4023_linear_1440p30_init(VI_PIPE ViPipe);
CVI_U8 gc4023_i2c_addr = 0x29;
const CVI_U32 gc4023_addr_byte = 2;
const CVI_U32 gc4023_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc4023_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc4023_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc4023_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc4023_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc4023_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (gc4023_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, gc4023_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, gc4023_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (gc4023_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_INFO, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int gc4023_write_register(VI_PIPE ViPipe, int addr, int data)
{
int idx = 0;
int ret;
char buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc4023_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (gc4023_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc4023_addr_byte + gc4023_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
ret = read(g_fd[ViPipe], buf, gc4023_addr_byte + gc4023_data_byte);
syslog(LOG_INFO, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void gc4023_prog(VI_PIPE ViPipe, int *rom)
{
int i = 0;
while (1) {
int lookup = rom[i++];
int addr = (lookup >> 16) & 0xFFFF;
int data = lookup & 0xFFFF;
if (addr == 0xFFFE)
delay_ms(data);
else if (addr != 0xFFFF)
gc4023_write_register(ViPipe, addr, data);
}
}
void gc4023_standby(VI_PIPE ViPipe)
{
gc4023_write_register(ViPipe, 0x0100, 0x00);
gc4023_write_register(ViPipe, 0x0a34, 0x00);
gc4023_write_register(ViPipe, 0x061c, 0x10);
gc4023_write_register(ViPipe, 0x031c, 0x01);
gc4023_write_register(ViPipe, 0x0a38, 0x00);
}
void gc4023_restart(VI_PIPE ViPipe)
{
gc4023_write_register(ViPipe, 0x0a38, 0x01);
gc4023_write_register(ViPipe, 0x0a34, 0x40);
gc4023_write_register(ViPipe, 0x061c, 0x50);
gc4023_write_register(ViPipe, 0x031c, 0xce);
gc4023_write_register(ViPipe, 0x0100, 0x09);
}
void gc4023_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastGc4023[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
gc4023_write_register(ViPipe,
g_pastGc4023[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastGc4023[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
int gc4023_probe(VI_PIPE ViPipe)
{
int nVal;
int nVal2;
usleep(50);
if (gc4023_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = gc4023_read_register(ViPipe, GC4023_CHIP_ID_ADDR_H);
nVal2 = gc4023_read_register(ViPipe, GC4023_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC4023_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void gc4023_init(VI_PIPE ViPipe)
{
gc4023_i2c_init(ViPipe);
gc4023_linear_1440p30_init(ViPipe);
g_pastGc4023[ViPipe]->bInit = CVI_TRUE;
}
void gc4023_exit(VI_PIPE ViPipe)
{
gc4023_i2c_exit(ViPipe);
}
static void gc4023_linear_1440p30_init(VI_PIPE ViPipe)
{
usleep(10*1000);
gc4023_write_register(ViPipe, 0x03fe, 0xf0);
gc4023_write_register(ViPipe, 0x03fe, 0x00);
gc4023_write_register(ViPipe, 0x03fe, 0x10);
gc4023_write_register(ViPipe, 0x03fe, 0x00);
gc4023_write_register(ViPipe, 0x0a38, 0x00);
gc4023_write_register(ViPipe, 0x0a38, 0x01);
gc4023_write_register(ViPipe, 0x0a20, 0x07);
gc4023_write_register(ViPipe, 0x061c, 0x50);
gc4023_write_register(ViPipe, 0x061d, 0x22);
gc4023_write_register(ViPipe, 0x061e, 0x78);
gc4023_write_register(ViPipe, 0x061f, 0x06);
gc4023_write_register(ViPipe, 0x0a21, 0x10);
gc4023_write_register(ViPipe, 0x0a34, 0x40);
gc4023_write_register(ViPipe, 0x0a35, 0x01);
gc4023_write_register(ViPipe, 0x0a36, 0x4e);
gc4023_write_register(ViPipe, 0x0a37, 0x06);
gc4023_write_register(ViPipe, 0x0314, 0x50);
gc4023_write_register(ViPipe, 0x0315, 0x00);
gc4023_write_register(ViPipe, 0x031c, 0xce);
gc4023_write_register(ViPipe, 0x0219, 0x47);
gc4023_write_register(ViPipe, 0x0342, 0x04);
gc4023_write_register(ViPipe, 0x0343, 0xb0);
gc4023_write_register(ViPipe, 0x0259, 0x05);
gc4023_write_register(ViPipe, 0x025a, 0xa0);
gc4023_write_register(ViPipe, 0x0340, 0x05);
gc4023_write_register(ViPipe, 0x0341, 0xdc);
gc4023_write_register(ViPipe, 0x0347, 0x02);
gc4023_write_register(ViPipe, 0x0348, 0x0a);
gc4023_write_register(ViPipe, 0x0349, 0x08);
gc4023_write_register(ViPipe, 0x034a, 0x05);
gc4023_write_register(ViPipe, 0x034b, 0xa8);
gc4023_write_register(ViPipe, 0x0094, 0x0a);
gc4023_write_register(ViPipe, 0x0095, 0x00);
gc4023_write_register(ViPipe, 0x0096, 0x05);
gc4023_write_register(ViPipe, 0x0097, 0xa0);
gc4023_write_register(ViPipe, 0x0099, 0x04);
gc4023_write_register(ViPipe, 0x009b, 0x04);
gc4023_write_register(ViPipe, 0x060c, 0x01);
gc4023_write_register(ViPipe, 0x060e, 0x08);
gc4023_write_register(ViPipe, 0x060f, 0x05);
gc4023_write_register(ViPipe, 0x070c, 0x01);
gc4023_write_register(ViPipe, 0x070e, 0x08);
gc4023_write_register(ViPipe, 0x070f, 0x05);
gc4023_write_register(ViPipe, 0x0909, 0x03);
gc4023_write_register(ViPipe, 0x0902, 0x04);
gc4023_write_register(ViPipe, 0x0904, 0x0b);
gc4023_write_register(ViPipe, 0x0907, 0x54);
gc4023_write_register(ViPipe, 0x0908, 0x06);
gc4023_write_register(ViPipe, 0x0903, 0x9d);
gc4023_write_register(ViPipe, 0x072a, 0x18);
gc4023_write_register(ViPipe, 0x0724, 0x0a);
gc4023_write_register(ViPipe, 0x0727, 0x0a);
gc4023_write_register(ViPipe, 0x072a, 0x1c);
gc4023_write_register(ViPipe, 0x072b, 0x0a);
gc4023_write_register(ViPipe, 0x1466, 0x10);
gc4023_write_register(ViPipe, 0x1468, 0x0b);
gc4023_write_register(ViPipe, 0x1467, 0x13);
gc4023_write_register(ViPipe, 0x1469, 0x80);
gc4023_write_register(ViPipe, 0x146a, 0xe8);
gc4023_write_register(ViPipe, 0x0707, 0x07);
gc4023_write_register(ViPipe, 0x0737, 0x0f);
gc4023_write_register(ViPipe, 0x0704, 0x01);
gc4023_write_register(ViPipe, 0x0706, 0x03);
gc4023_write_register(ViPipe, 0x0716, 0x03);
gc4023_write_register(ViPipe, 0x0708, 0xc8);
gc4023_write_register(ViPipe, 0x0718, 0xc8);
gc4023_write_register(ViPipe, 0x061a, 0x00);
gc4023_write_register(ViPipe, 0x1430, 0x80);
gc4023_write_register(ViPipe, 0x1407, 0x10);
gc4023_write_register(ViPipe, 0x1408, 0x16);
gc4023_write_register(ViPipe, 0x1409, 0x03);
gc4023_write_register(ViPipe, 0x146d, 0x0e);
gc4023_write_register(ViPipe, 0x146e, 0x42);
gc4023_write_register(ViPipe, 0x146f, 0x43);
gc4023_write_register(ViPipe, 0x1470, 0x3c);
gc4023_write_register(ViPipe, 0x1471, 0x3d);
gc4023_write_register(ViPipe, 0x1472, 0x3a);
gc4023_write_register(ViPipe, 0x1473, 0x3a);
gc4023_write_register(ViPipe, 0x1474, 0x40);
gc4023_write_register(ViPipe, 0x1475, 0x46);
gc4023_write_register(ViPipe, 0x1420, 0x14);
gc4023_write_register(ViPipe, 0x1464, 0x15);
gc4023_write_register(ViPipe, 0x146c, 0x40);
gc4023_write_register(ViPipe, 0x146d, 0x40);
gc4023_write_register(ViPipe, 0x1423, 0x08);
gc4023_write_register(ViPipe, 0x1428, 0x10);
gc4023_write_register(ViPipe, 0x1462, 0x18);
gc4023_write_register(ViPipe, 0x02ce, 0x04);
gc4023_write_register(ViPipe, 0x143a, 0x0f);
gc4023_write_register(ViPipe, 0x142b, 0x88);
gc4023_write_register(ViPipe, 0x0245, 0xc9);
gc4023_write_register(ViPipe, 0x023a, 0x08);
gc4023_write_register(ViPipe, 0x02cd, 0x99);
gc4023_write_register(ViPipe, 0x0612, 0x02);
gc4023_write_register(ViPipe, 0x0613, 0xc7);
gc4023_write_register(ViPipe, 0x0243, 0x03);
gc4023_write_register(ViPipe, 0x021b, 0x09);
gc4023_write_register(ViPipe, 0x0089, 0x03);
gc4023_write_register(ViPipe, 0x0040, 0xa3);
gc4023_write_register(ViPipe, 0x0075, 0x64);
gc4023_write_register(ViPipe, 0x0004, 0x0f);
gc4023_write_register(ViPipe, 0x0002, 0xab);
gc4023_write_register(ViPipe, 0x0053, 0x0a);
gc4023_write_register(ViPipe, 0x0205, 0x0c);
gc4023_write_register(ViPipe, 0x0202, 0x06);
gc4023_write_register(ViPipe, 0x0203, 0x27);
gc4023_write_register(ViPipe, 0x0614, 0x00);
gc4023_write_register(ViPipe, 0x0615, 0x00);
gc4023_write_register(ViPipe, 0x0181, 0x0c);
gc4023_write_register(ViPipe, 0x0182, 0x05);
gc4023_write_register(ViPipe, 0x0185, 0x01);
gc4023_write_register(ViPipe, 0x0180, 0x46);
gc4023_write_register(ViPipe, 0x0100, 0x08);
gc4023_write_register(ViPipe, 0x0106, 0x38);
gc4023_write_register(ViPipe, 0x010d, 0x80);
gc4023_write_register(ViPipe, 0x010e, 0x0c);
gc4023_write_register(ViPipe, 0x0113, 0x02);
gc4023_write_register(ViPipe, 0x0114, 0x01);
gc4023_write_register(ViPipe, 0x0115, 0x10);
gc4023_write_register(ViPipe, 0x022c, MIRROR);
gc4023_write_register(ViPipe, 0x0100, 0x09);
gc4023_write_register(ViPipe, 0x0a67, 0x80);
gc4023_write_register(ViPipe, 0x0a54, 0x0e);
gc4023_write_register(ViPipe, 0x0a65, 0x10);
gc4023_write_register(ViPipe, 0x0a98, 0x10);
gc4023_write_register(ViPipe, 0x05be, 0x00);
gc4023_write_register(ViPipe, 0x05a9, 0x01);
gc4023_write_register(ViPipe, 0x0029, 0x08);
gc4023_write_register(ViPipe, 0x002b, 0xa8);
gc4023_write_register(ViPipe, 0x0a83, 0xe0);
gc4023_write_register(ViPipe, 0x0a72, 0x02);
gc4023_write_register(ViPipe, 0x0a73, OTP_MIRROR);
gc4023_write_register(ViPipe, 0x0a75, 0x41);
gc4023_write_register(ViPipe, 0x0a70, 0x03);
gc4023_write_register(ViPipe, 0x0a5a, 0x80);
usleep(20*1000);
gc4023_write_register(ViPipe, 0x05be, 0x01);
gc4023_write_register(ViPipe, 0x0a70, 0x00);
gc4023_write_register(ViPipe, 0x0080, 0x02);
gc4023_write_register(ViPipe, 0x0a67, 0x00);
gc4023_default_reg_init(ViPipe);
usleep(10*1000);
printf("ViPipe:%d,===GC4023 1440P 30fps 10bit LINEAR Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/gcore_gc4653/Makefile Normal file
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@ -0,0 +1,36 @@
SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_gc4653.a
TARGET_SO = $(MW_LIB)/libsns_gc4653.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

960
middleware/v2/component/isp/sensor/cv180x/gcore_gc4653/gc4653_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "gc4653_cmos_ex.h"
#include "gc4653_cmos_param.h"
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define GC4653_ID 4653
#define GC4653_I2C_ADDR_1 0x10
#define GC4653_I2C_ADDR_2 0x29
#define GC4653_I2C_ADDR_IS_VALID(addr) ((addr) == GC4653_I2C_ADDR_1 || (addr) == GC4653_I2C_ADDR_2)
/****************************************************************************
* global variables *
***************************************************************************/
ISP_SNS_STATE_S *g_pastGc4653[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define GC4653_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc4653[dev])
#define GC4653_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc4653[dev] = pstCtx)
#define GC4653_SENSOR_RESET_CTX(dev) (g_pastGc4653[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunGc4653_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 3},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc4653_MirrorFip[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Gc4653_GainMode[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
***************************************************************************/
static ISP_FSWDR_MODE_E genFSWDRMode[VI_MAX_PIPE_NUM] = {
[0 ... VI_MAX_PIPE_NUM - 1] = ISP_FSWDR_NORMAL_MODE
};
static CVI_U32 gu32MaxTimeGetCnt[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Gc4653 Lines Range*****/
#define GC4653_FULL_LINES_MAX (0x3fff)
/*****Gc4653 Register Address*****/
#define GC4653_EXP_H_ADDR 0x0202 //bit[13:8]
#define GC4653_EXP_L_ADDR 0x0203
#define GC4653_AGAIN_H_ADDR 0x02b4 //bit[10:8]
#define GC4653_AGAIN_L_ADDR 0x02b3
#define GC4653_COL_AGAIN_H_ADDR 0x02b8 //bit[13:8]
#define GC4653_COL_AGAIN_L_ADDR 0x02b9
#define GC4653_DGAIN_H_ADDR 0x020e //bit[9:6]
#define GC4653_DGAIN_L_ADDR 0x020f //bit[5:0]
#define GC4653_AGAIN_MAG1_ADDR 0x0515
#define GC4653_AGAIN_MAG2_ADDR 0x0519
#define GC4653_AGAIN_MAG3_ADDR 0x02d9
#define GC4653_VTS_H_ADDR 0x0340 //bit[13:8]
#define GC4653_VTS_L_ADDR 0x0341
#define GC4653_FLIP_MIRROR_ADDR 0x0101
#define GC4653_FRAME_BUF_ADDR 0x031D
#define GC4653_RES_IS_1440P(w, h) ((w) <= 2560 && (h) <= 1440)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = GC4653_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
#if 0
pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0;
pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0;
pstAeSnsDft->bAERouteExValid = CVI_FALSE;
pstAeSnsDft->stAERouteAttr.u32TotalNum = 0;
pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0;
#endif
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = g_astGc4653_mode[GC4653_MODE_2560X1440P30].f32MaxFps;
pstAeSnsDft->f32MinFps = g_astGc4653_mode[GC4653_MODE_2560X1440P30].f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = 77648;
pstAeSnsDft->u32MinAgain = 1024;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = 10240;
pstAeSnsDft->u32MinDgain = 1024;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 2;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
g_au32InitExposure[ViPipe] : g_astGc4653_mode[GC4653_MODE_2560X1440P30].stExp[0].u16Def;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstAeSnsDft->u32MinIntTime = g_astGc4653_mode[GC4653_MODE_2560X1440P30].stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_astGc4653_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_astGc4653_mode[pstSnsState->u8ImgMode].f32MaxFps;
f32MinFps = g_astGc4653_mode[pstSnsState->u8ImgMode].f32MinFps;
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > GC4653_FULL_LINES_MAX) ? GC4653_FULL_LINES_MAX : u32VMAX;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_VTS_H].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_L].u32Data = (u32VMAX & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
pstSnsState->u32FLStd = u32VMAX;
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_H].u32Data = ((u32IntTime[0] >> 8) & 0x3F);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_L].u32Data = (u32IntTime[0] & 0xFF);
return CVI_SUCCESS;
}
static CVI_U32 regValTable[26][7] = {
/* [reg] 0x2b3, 0x2b4, 0x2b8, 0x2b9, 0x515, 0x519, 0x2d9
* [name] AGAIN_L AGAIN_H COLGA_H COLGA_L MAG1 MAG2 MAG3
*/
{0x00, 0x00, 0x01, 0x00, 0x30, 0x1e, 0x5C},
{0x20, 0x00, 0x01, 0x0B, 0x30, 0x1e, 0x5C},
{0x01, 0x00, 0x01, 0x19, 0x30, 0x1d, 0x5B},
{0x21, 0x00, 0x01, 0x2A, 0x30, 0x1e, 0x5C},
{0x02, 0x00, 0x02, 0x00, 0x30, 0x1e, 0x5C},
{0x22, 0x00, 0x02, 0x17, 0x30, 0x1d, 0x5B},
{0x03, 0x00, 0x02, 0x33, 0x20, 0x16, 0x54},
{0x23, 0x00, 0x03, 0x14, 0x20, 0x17, 0x55},
{0x04, 0x00, 0x04, 0x00, 0x20, 0x17, 0x55},
{0x24, 0x00, 0x04, 0x2F, 0x20, 0x19, 0x57},
{0x05, 0x00, 0x05, 0x26, 0x20, 0x19, 0x57},
{0x25, 0x00, 0x06, 0x28, 0x20, 0x1b, 0x59},
{0x0c, 0x00, 0x08, 0x00, 0x20, 0x1d, 0x5B},
{0x2C, 0x00, 0x09, 0x1E, 0x20, 0x1f, 0x5D},
{0x0D, 0x00, 0x0B, 0x0C, 0x20, 0x21, 0x5F},
{0x2D, 0x00, 0x0D, 0x11, 0x20, 0x24, 0x62},
{0x1C, 0x00, 0x10, 0x00, 0x20, 0x26, 0x64},
{0x3C, 0x00, 0x12, 0x3D, 0x18, 0x2a, 0x68},
{0x5C, 0x00, 0x16, 0x19, 0x18, 0x2c, 0x6A},
{0x7C, 0x00, 0x1A, 0x22, 0x18, 0x2e, 0x6C},
{0x9C, 0x00, 0x20, 0x00, 0x18, 0x32, 0x70},
{0xBC, 0x00, 0x25, 0x3A, 0x18, 0x35, 0x73},
{0xDC, 0x00, 0x2C, 0x33, 0x10, 0x36, 0x74},
{0xFC, 0x00, 0x35, 0x05, 0x10, 0x38, 0x76},
{0x1C, 0x01, 0x40, 0x00, 0x10, 0x3c, 0x7A},
{0x3C, 0x01, 0x4B, 0x35, 0x10, 0x42, 0x80},
};
static CVI_U32 gain_table[26] = {
1024, 1200, 1424, 1696, 2048, 2416, 2864, 3392, 4096, 4848, 5728,
6784, 8192, 9696, 11456, 13584, 16384, 19408, 22928, 27168, 32768,
38816, 45872, 54352, 65536, 77648
};
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
int i, total;
CVI_U32 pregain;
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
UNUSED(ViPipe);
total = sizeof(gain_table) / sizeof(CVI_U32);
if (*pu32AgainLin >= gain_table[total - 1]) {
*pu32AgainLin = *pu32AgainDb = gain_table[total - 1];
return CVI_SUCCESS;
}
for (i = 1; i < total; i++) {
if (*pu32AgainLin < gain_table[i])
break;
}
i--;
// find the pregain
pregain = *pu32AgainLin * 64 / gain_table[i];
// set the Db as the AE algo gain, we need this to do gain update
*pu32AgainDb = *pu32AgainLin;
// set the Lin as the closest sensor gain for AE algo reference
*pu32AgainLin = pregain * gain_table[i] / 64;
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
CVI_U32 pregain;
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
UNUSED(ViPipe);
// find the pregain
pregain = *pu32DgainLin * 64 / 1024;
// set the Db as the AE algo gain, we need this to do gain update
*pu32DgainDb = *pu32DgainLin;
// set the Lin as the closest sensor gain for AE algo reference
*pu32DgainLin = pregain * 16;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32Again;
CVI_U32 u32Dgain;
int i, total;
total = sizeof(gain_table) / sizeof(CVI_U32);
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* only surpport linear mode */
u32Again = pu32Again[0];
/* To kepp the linearity. we assume AE algo adjusts the dgain only when the again reachs the maximum value */
if (u32Again < (77648)) {
for (i = 1; i < total; i++) {
if (*pu32Again < gain_table[i])
break;
}
i--;
// find the pregain
u32Dgain = u32Again * 64 / gain_table[i];
u32Again = i;
} else {
u32Again = total - 1;
// find the pregain
u32Dgain = pu32Dgain[0] * 64 / 1024;
}
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_L].u32Data = regValTable[u32Again][0];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_H].u32Data = regValTable[u32Again][1];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_H].u32Data = regValTable[u32Again][2];
pstSnsRegsInfo->astI2cData[LINEAR_COL_AGAIN_L].u32Data = regValTable[u32Again][3];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_MAG1].u32Data = regValTable[u32Again][4];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_MAG2].u32Data = regValTable[u32Again][5];
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_MAG3].u32Data = regValTable[u32Again][6];
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 6);
pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0x3F) << 2;
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
{
UNUSED(ViPipe);
UNUSED(u16ManRatioEnable);
UNUSED(au32Ratio);
UNUSED(au32IntTimeMax);
UNUSED(au32IntTimeMin);
UNUSED(pu32LFMaxIntTime);
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode\n");
return CVI_SUCCESS;
}
/* Only used in LINE_WDR mode */
static CVI_S32 cmos_ae_fswdr_attr_set(VI_PIPE ViPipe, AE_FSWDR_ATTR_S *pstAeFSWDRAttr)
{
CMOS_CHECK_POINTER(pstAeFSWDRAttr);
genFSWDRMode[ViPipe] = pstAeFSWDRAttr->enFSWDRMode;
gu32MaxTimeGetCnt[ViPipe] = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
CMOS_CHECK_POINTER(pstAwbSnsDft);
UNUSED(ViPipe);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
UNUSED(ViPipe);
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
memcpy(pstDef->stNoiseCalibration.CalibrationCoef,
&g_stIspNoiseCalibratio, sizeof(ISP_CMOS_NOISE_CALIBRATION_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
CMOS_CHECK_POINTER(pstBlc);
UNUSED(ViPipe);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const GC4653_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astGc4653_mode[pstSnsState->u8ImgMode];
if (pstSnsState->enWDRMode != WDR_MODE_NONE) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
} else {
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
UNUSED(ViPipe);
UNUSED(u8Mode);
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunGc4653_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = gc4653_i2c_addr;
pstI2c_data[i].u32AddrByteNum = gc4653_addr_byte;
pstI2c_data[i].u32DataByteNum = gc4653_data_byte;
}
pstI2c_data[LINEAR_EXP_H].u32RegAddr = GC4653_EXP_H_ADDR;
pstI2c_data[LINEAR_EXP_L].u32RegAddr = GC4653_EXP_L_ADDR;
pstI2c_data[LINEAR_AGAIN_H].u32RegAddr = GC4653_AGAIN_H_ADDR;
pstI2c_data[LINEAR_AGAIN_L].u32RegAddr = GC4653_AGAIN_L_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_H].u32RegAddr = GC4653_COL_AGAIN_H_ADDR;
pstI2c_data[LINEAR_COL_AGAIN_L].u32RegAddr = GC4653_COL_AGAIN_L_ADDR;
pstI2c_data[LINEAR_AGAIN_MAG1].u32RegAddr = GC4653_AGAIN_MAG1_ADDR;
pstI2c_data[LINEAR_AGAIN_MAG2].u32RegAddr = GC4653_AGAIN_MAG2_ADDR;
pstI2c_data[LINEAR_AGAIN_MAG3].u32RegAddr = GC4653_AGAIN_MAG3_ADDR;
pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = GC4653_DGAIN_H_ADDR;
pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = GC4653_DGAIN_L_ADDR;
pstI2c_data[LINEAR_VTS_H].u32RegAddr = GC4653_VTS_H_ADDR;
pstI2c_data[LINEAR_VTS_L].u32RegAddr = GC4653_VTS_L_ADDR;
pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = GC4653_FLIP_MIRROR_ADDR;
pstI2c_data[LINEAR_FRAME_BUF_ON].u32RegAddr = GC4653_FRAME_BUF_ADDR;
pstI2c_data[LINEAR_FRAME_BUF_ON].u32Data = 0x2D;
pstI2c_data[LINEAR_FRAME_BUF_OFF].u32RegAddr = GC4653_FRAME_BUF_ADDR;
pstI2c_data[LINEAR_FRAME_BUF_OFF].u32Data = 0x28;
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
CVI_U32 gainsUpdate = 0, shutterUpdate = 0, vtsUpdate = 0;
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
if ((i >= LINEAR_AGAIN_H) && (i <= LINEAR_DGAIN_L))
gainsUpdate = 1;
if (i <= LINEAR_EXP_L)
shutterUpdate = 1;
if ((i >= LINEAR_VTS_H) && (i <= LINEAR_VTS_L))
vtsUpdate = 1;
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
if (gainsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_COL_AGAIN_L].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_MAG1].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_MAG2].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN_MAG3].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_L].bUpdate = CVI_TRUE;
}
if (shutterUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_EXP_L].bUpdate = CVI_TRUE;
}
if (vtsUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_H].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_VTS_L].bUpdate = CVI_TRUE;
}
if (pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bUpdate) {
pstCfg0->snsCfg.astI2cData[LINEAR_FRAME_BUF_ON].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.astI2cData[LINEAR_FRAME_BUF_OFF].bUpdate = CVI_TRUE;
}
/* check update isp crop or not */
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 30) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (GC4653_RES_IS_1440P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = GC4653_MODE_2560X1440P30;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps);
return CVI_FAILURE;
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U8 value;
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
/* Apply the setting on the fly */
if (pstSnsState->bInit == CVI_TRUE && g_aeGc4653_MirrorFip[ViPipe] != eSnsMirrorFlip) {
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
value = 0;
break;
case ISP_SNS_MIRROR:
value = 1;
break;
case ISP_SNS_FLIP:
value = 2;
break;
case ISP_SNS_MIRROR_FLIP:
value = 3;
break;
default:
return;
}
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
g_aeGc4653_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = GC4653_MODE_2560X1440P30;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astGc4653_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[0] = g_astGc4653_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[1] = g_astGc4653_mode[pstSnsState->u8ImgMode].u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
GC4653_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &gc4653_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_astGc4653_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astGc4653_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc4653_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = gc4653_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = gc4653_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (GC4653_I2C_ADDR_IS_VALID(s32I2cAddr))
gc4653_i2c_addr = s32I2cAddr;
}
static CVI_S32 gc4653_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunGc4653_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC4653_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
GC4653_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
GC4653_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
GC4653_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = GC4653_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC4653_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, GC4653_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, GC4653_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Gc4653_GainMode[ViPipe] = pstInitAttr->enGainMode;
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return gc4653_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsGc4653_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = gc4653_standby,
.pfnRestart = gc4653_restart,
.pfnWriteReg = gc4653_write_register,
.pfnReadReg = gc4653_read_register,
.pfnSetBusInfo = gc4653_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = sensor_probe,
};

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#ifndef __GC4653_CMOS_EX_H_
#define __GC4653_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#ifndef UNUSED
#define UNUSED(x) ((void)(x))
#endif
enum gc4653_linear_regs_e {
LINEAR_EXP_H, //0x0202 bit[13:8]
LINEAR_EXP_L, //0x0203
LINEAR_AGAIN_L, //0x02b3
LINEAR_AGAIN_H, //0x02b4 bit[10:8]
LINEAR_COL_AGAIN_H, //0x02b8 bit[13:8]
LINEAR_COL_AGAIN_L, //0x02b9
LINEAR_AGAIN_MAG1, //0x0515
LINEAR_AGAIN_MAG2, //0x0519
LINEAR_AGAIN_MAG3, //0x02d9
LINEAR_DGAIN_H, //0x020e bit[9:6]
LINEAR_DGAIN_L, //0x020f bit[5:0]
LINEAR_VTS_H, //0x0341 bit[13:8]
LINEAR_VTS_L, //0x0342
LINEAR_FRAME_BUF_ON,//0x031D
LINEAR_FLIP_MIRROR,
LINEAR_FRAME_BUF_OFF,//0x031D
LINEAR_REGS_NUM
};
typedef enum _GC4653_MODE_E {
GC4653_MODE_2560X1440P30 = 0,
GC4653_MODE_LINEAR_NUM,
GC4653_MODE_NUM
} GC4653_MODE_E;
typedef struct _GC4653_STATE_S {
CVI_U32 u32Sexp_MAX;
} GC4653_STATE_S;
typedef struct _GC4653_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
char name[64];
} GC4653_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastGc4653[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunGc4653_BusInfo[];
extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc4653_MirrorFip[VI_MAX_PIPE_NUM];
extern CVI_U8 gc4653_i2c_addr;
extern const CVI_U32 gc4653_addr_byte;
extern const CVI_U32 gc4653_data_byte;
extern void gc4653_init(VI_PIPE ViPipe);
extern void gc4653_exit(VI_PIPE ViPipe);
extern void gc4653_standby(VI_PIPE ViPipe);
extern void gc4653_restart(VI_PIPE ViPipe);
extern int gc4653_write_register(VI_PIPE ViPipe, int addr, int data);
extern int gc4653_read_register(VI_PIPE ViPipe, int addr);
extern int gc4653_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC4653_CMOS_EX_H_ */

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#ifndef __GC4653_CMOS_PARAM_H_
#define __GC4653_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc4653_cmos_ex.h"
static const GC4653_MODE_S g_astGc4653_mode[GC4653_MODE_NUM] = {
[GC4653_MODE_2560X1440P30] = {
.name = "2560X1440P30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.f32MaxFps = 30,
.f32MinFps = 2.75, /* 1500 * 30 / 16383 */
.u32HtsDef = 2200,
.u32VtsDef = 1500,
.stExp[0] = {
.u16Min = 1,
.u16Max = 0x3fff,
.u16Def = 0x2000,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 77648,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16368,
.u32Def = 1024,
.u32Step = 64,
},
},
};
static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = {
{ //iso 100
{0.04006369039416313171, 5.73531675338745117188}, //B: slope, intercept
{0.03064448758959770203, 8.56994438171386718750}, //Gb: slope, intercept
{0.03068985790014266968, 8.82220363616943359375}, //Gr: slope, intercept
{0.03361049667000770569, 7.20687675476074218750}, //R: slope, intercept
},
{ //iso 200
{0.05054308474063873291, 7.91628408432006835938}, //B: slope, intercept
{0.03632996603846549988, 13.05291843414306640625}, //Gb: slope, intercept
{0.03697143867611885071, 12.49540805816650390625}, //Gr: slope, intercept
{0.04156460240483283997, 10.44298553466796875000}, //R: slope, intercept
},
{ //iso 400
{0.06805337965488433838, 11.55693244934082031250}, //B: slope, intercept
{0.04390667378902435303, 18.59673881530761718750}, //Gb: slope, intercept
{0.04630871489644050598, 17.90183258056640625000}, //Gr: slope, intercept
{0.05292420834302902222, 15.17318439483642578125}, //R: slope, intercept
},
{ //iso 800
{0.08635756373405456543, 17.79124641418457031250}, //B: slope, intercept
{0.05776864662766456604, 26.76541900634765625000}, //Gb: slope, intercept
{0.05839699879288673401, 26.44194030761718750000}, //Gr: slope, intercept
{0.06750740110874176025, 22.42554473876953125000}, //R: slope, intercept
},
{ //iso 1600
{0.12254384160041809082, 26.20610046386718750000}, //B: slope, intercept
{0.07916855812072753906, 39.39273834228515625000}, //Gb: slope, intercept
{0.07857896387577056885, 39.03499984741210937500}, //Gr: slope, intercept
{0.09273355454206466675, 33.09597778320312500000}, //R: slope, intercept
},
{ //iso 3200
{0.18002016842365264893, 34.86975860595703125000}, //B: slope, intercept
{0.10951708257198333740, 54.58878326416015625000}, //Gb: slope, intercept
{0.10485322028398513794, 57.16654205322265625000}, //Gr: slope, intercept
{0.13257601857185363770, 46.27093505859375000000}, //R: slope, intercept
},
{ //iso 6400
{0.24713687598705291748, 48.62341690063476562500}, //B: slope, intercept
{0.14974890649318695068, 77.06428527832031250000}, //Gb: slope, intercept
{0.14544390141963958740, 76.57913970947265625000}, //Gr: slope, intercept
{0.19056233763694763184, 62.13500213623046875000}, //R: slope, intercept
},
{ //iso 12800
{0.37728109955787658691, 58.15543365478515625000}, //B: slope, intercept
{0.20440576970577239990, 100.45700073242187500000}, //Gb: slope, intercept
{0.20059910416603088379, 102.35488891601562500000}, //Gr: slope, intercept
{0.27388775348663330078, 79.65499877929687500000}, //R: slope, intercept
},
{ //iso 25600
{0.36612421274185180664, 115.28938293457031250000}, //B: slope, intercept
{0.22633622586727142334, 164.58416748046875000000}, //Gb: slope, intercept
{0.21590474247932434082, 168.92042541503906250000}, //Gr: slope, intercept
{0.33193346858024597168, 127.92090606689453125000}, //R: slope, intercept
},
{ //iso 51200
{0.48242908716201782227, 147.39015197753906250000}, //B: slope, intercept
{0.28994381427764892578, 223.02711486816406250000}, //Gb: slope, intercept
{0.29200506210327148438, 220.64030456542968750000}, //Gr: slope, intercept
{0.42304891347885131836, 173.74638366699218750000}, //R: slope, intercept
},
{ //iso 102400
{0.62099909782409667969, 130.97862243652343750000}, //B: slope, intercept
{0.39534106850624084473, 219.74490356445312500000}, //Gb: slope, intercept
{0.39458695054054260254, 213.37374877929687500000}, //Gr: slope, intercept
{0.55690109729766845703, 158.37773132324218750000}, //R: slope, intercept
},
{ //iso 204800
{0.75350415706634521484, 77.81707000732421875000}, //B: slope, intercept
{0.52716732025146484375, 148.77879333496093750000}, //Gb: slope, intercept
{0.51073729991912841797, 153.86495971679687500000}, //Gr: slope, intercept
{0.68910604715347290039, 102.12422180175781250000}, //R: slope, intercept
},
{ //iso 409600
{0.90276730060577392578, 43.78258514404296875000}, //B: slope, intercept
{0.62851423025131225586, 119.41429138183593750000}, //Gb: slope, intercept
{0.64918899536132812500, 110.74241638183593750000}, //Gr: slope, intercept
{0.80880594253540039063, 68.89983367919921875000}, //R: slope, intercept
},
{ //iso 819200
{0.90276730060577392578, 43.78258514404296875000}, //B: slope, intercept
{0.62851423025131225586, 119.41429138183593750000}, //Gb: slope, intercept
{0.64918899536132812500, 110.74241638183593750000}, //Gr: slope, intercept
{0.80880594253540039063, 68.89983367919921875000}, //R: slope, intercept
},
{ //iso 1638400
{0.90276730060577392578, 43.78258514404296875000}, //B: slope, intercept
{0.62851423025131225586, 119.41429138183593750000}, //Gb: slope, intercept
{0.64918899536132812500, 110.74241638183593750000}, //Gr: slope, intercept
{0.80880594253540039063, 68.89983367919921875000}, //R: slope, intercept
},
{ //iso 3276800
{0.90276730060577392578, 43.78258514404296875000}, //B: slope, intercept
{0.62851423025131225586, 119.41429138183593750000}, //Gb: slope, intercept
{0.64918899536132812500, 110.74241638183593750000}, //Gr: slope, intercept
{0.80880594253540039063, 68.89983367919921875000}, //R: slope, intercept
},
} };
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {256, 256, 256, 256, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1092, 1092, 1092, 1092
#endif
},
.stAuto = {
{255, 256, 256, 257, 260, 264, 272, 289, 324, 400, 468, 474, 475, 476, 466, 496 },
{255, 256, 256, 257, 260, 264, 272, 289, 325, 404, 469, 476, 477, 477, 467, 493 },
{255, 256, 256, 257, 260, 264, 272, 289, 325, 401, 468, 477, 476, 477, 467, 495 },
{255, 256, 256, 257, 260, 264, 272, 290, 325, 404, 471, 477, 478, 478, 468, 493 },
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1092, 1092, 1092, 1093, 1093, 1095, 1097, 1102, 1112, 1135, 1156, 1158, 1158, 1159,
1155, 1165},
{1092, 1092, 1092, 1093, 1093, 1095, 1097, 1102, 1112, 1136, 1156, 1159, 1159, 1159,
1156, 1164},
{1092, 1092, 1092, 1093, 1093, 1095, 1097, 1102, 1112, 1135, 1156, 1159, 1159, 1159,
1156, 1165},
{1092, 1092, 1092, 1093, 1093, 1095, 1097, 1102, 1112, 1136, 1157, 1159, 1159, 1159,
1156, 1164},
#endif
},
},
};
struct combo_dev_attr_s gc4653_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {2, 1, 3, -1, -1},
.pn_swap = {1, 1, 1, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __GC4653_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "gc4653_cmos_ex.h"
#define GC4653_CHIP_ID_ADDR_H 0x03f0
#define GC4653_CHIP_ID_ADDR_L 0x03f1
#define GC4653_CHIP_ID 0x4653
static void gc4653_linear_1440p30_init(VI_PIPE ViPipe);
CVI_U8 gc4653_i2c_addr = 0x10;
const CVI_U32 gc4653_addr_byte = 2;
const CVI_U32 gc4653_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int gc4653_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunGc4653_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc4653_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int gc4653_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int gc4653_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (gc4653_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, gc4653_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return ret;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, gc4653_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return ret;
}
// pack read back data
data = 0;
if (gc4653_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int gc4653_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (gc4653_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (gc4653_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, gc4653_addr_byte + gc4653_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
ret = read(g_fd[ViPipe], buf, gc4653_addr_byte + gc4653_data_byte);
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void gc4653_standby(VI_PIPE ViPipe)
{
gc4653_write_register(ViPipe, 0x0100, 0x00);
gc4653_write_register(ViPipe, 0x031c, 0xc7);
gc4653_write_register(ViPipe, 0x0317, 0x01);
printf("gc4653_standby\n");
}
void gc4653_restart(VI_PIPE ViPipe)
{
gc4653_write_register(ViPipe, 0x0317, 0x00);
gc4653_write_register(ViPipe, 0x031c, 0xc6);
gc4653_write_register(ViPipe, 0x0100, 0x09);
printf("gc4653_restart\n");
}
void gc4653_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastGc4653[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
gc4653_write_register(ViPipe,
g_pastGc4653[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastGc4653[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
int gc4653_probe(VI_PIPE ViPipe)
{
int nVal;
int nVal2;
usleep(50);
if (gc4653_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = gc4653_read_register(ViPipe, GC4653_CHIP_ID_ADDR_H);
nVal2 = gc4653_read_register(ViPipe, GC4653_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != GC4653_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void gc4653_init(VI_PIPE ViPipe)
{
gc4653_i2c_init(ViPipe);
gc4653_linear_1440p30_init(ViPipe);
g_pastGc4653[ViPipe]->bInit = CVI_TRUE;
}
void gc4653_exit(VI_PIPE ViPipe)
{
gc4653_i2c_exit(ViPipe);
}
static void gc4653_linear_1440p30_init(VI_PIPE ViPipe)
{
delay_ms(10);
/****system****/
gc4653_write_register(ViPipe, 0x03fe, 0xf0);
gc4653_write_register(ViPipe, 0x03fe, 0x00);
gc4653_write_register(ViPipe, 0x0317, 0x00);
gc4653_write_register(ViPipe, 0x0320, 0x77);
gc4653_write_register(ViPipe, 0x0324, 0xc8);
gc4653_write_register(ViPipe, 0x0325, 0x06);
gc4653_write_register(ViPipe, 0x0326, 0x60);
gc4653_write_register(ViPipe, 0x0327, 0x03);
gc4653_write_register(ViPipe, 0x0334, 0x40);
gc4653_write_register(ViPipe, 0x0336, 0x60);
gc4653_write_register(ViPipe, 0x0337, 0x82);
gc4653_write_register(ViPipe, 0x0315, 0x25);
gc4653_write_register(ViPipe, 0x031c, 0xc6);
/****************************************/
/*frame structure*/
/****************************************/
gc4653_write_register(ViPipe, 0x0287, 0x18);
gc4653_write_register(ViPipe, 0x0084, 0x00);
gc4653_write_register(ViPipe, 0x0087, 0x50);
gc4653_write_register(ViPipe, 0x029d, 0x08);
gc4653_write_register(ViPipe, 0x0290, 0x00);
/**********AHD 30 other need change ******************/
gc4653_write_register(ViPipe, 0x0340, 0x05);
gc4653_write_register(ViPipe, 0x0341, 0xdc);
gc4653_write_register(ViPipe, 0x0345, 0x06);
gc4653_write_register(ViPipe, 0x034b, 0xb0);
gc4653_write_register(ViPipe, 0x0352, 0x08);
gc4653_write_register(ViPipe, 0x0354, 0x08);
/****************************************/
/*ANALOG CIRCUIT*/
/****************************************/
gc4653_write_register(ViPipe, 0x02d1, 0xe0);
gc4653_write_register(ViPipe, 0x0223, 0xf2);
gc4653_write_register(ViPipe, 0x0238, 0xa4);
gc4653_write_register(ViPipe, 0x02ce, 0x7f);
gc4653_write_register(ViPipe, 0x0232, 0xc4);
gc4653_write_register(ViPipe, 0x02d3, 0x05);
gc4653_write_register(ViPipe, 0x0243, 0x06);
gc4653_write_register(ViPipe, 0x02ee, 0x30);
gc4653_write_register(ViPipe, 0x026f, 0x70);
gc4653_write_register(ViPipe, 0x0257, 0x09);
gc4653_write_register(ViPipe, 0x0211, 0x02);
gc4653_write_register(ViPipe, 0x0219, 0x09);
gc4653_write_register(ViPipe, 0x023f, 0x2d);
gc4653_write_register(ViPipe, 0x0518, 0x00);
gc4653_write_register(ViPipe, 0x0519, 0x01);
gc4653_write_register(ViPipe, 0x0515, 0x08);
gc4653_write_register(ViPipe, 0x02d9, 0x3f);
gc4653_write_register(ViPipe, 0x02da, 0x02);
gc4653_write_register(ViPipe, 0x02db, 0xe8);
gc4653_write_register(ViPipe, 0x02e6, 0x20);
gc4653_write_register(ViPipe, 0x021b, 0x10);
gc4653_write_register(ViPipe, 0x0252, 0x22);
gc4653_write_register(ViPipe, 0x024e, 0x22);
gc4653_write_register(ViPipe, 0x02c4, 0x01);
gc4653_write_register(ViPipe, 0x021d, 0x17);
gc4653_write_register(ViPipe, 0x024a, 0x01);
gc4653_write_register(ViPipe, 0x02ca, 0x02);
gc4653_write_register(ViPipe, 0x0262, 0x10);
gc4653_write_register(ViPipe, 0x029a, 0x20);
gc4653_write_register(ViPipe, 0x021c, 0x0e);
gc4653_write_register(ViPipe, 0x0298, 0x03);
gc4653_write_register(ViPipe, 0x029c, 0x00);
gc4653_write_register(ViPipe, 0x027e, 0x14);
gc4653_write_register(ViPipe, 0x02c2, 0x10);
gc4653_write_register(ViPipe, 0x0540, 0x20);
gc4653_write_register(ViPipe, 0x0546, 0x01);
gc4653_write_register(ViPipe, 0x0548, 0x01);
gc4653_write_register(ViPipe, 0x0544, 0x01);
gc4653_write_register(ViPipe, 0x0242, 0x1b);
gc4653_write_register(ViPipe, 0x02c0, 0x1b);
gc4653_write_register(ViPipe, 0x02c3, 0x20);
gc4653_write_register(ViPipe, 0x02e4, 0x10);
gc4653_write_register(ViPipe, 0x022e, 0x00);
gc4653_write_register(ViPipe, 0x027b, 0x3f);
gc4653_write_register(ViPipe, 0x0269, 0x0f);
gc4653_write_register(ViPipe, 0x02d2, 0x40);
gc4653_write_register(ViPipe, 0x027c, 0x08);
gc4653_write_register(ViPipe, 0x023a, 0x2e);
gc4653_write_register(ViPipe, 0x0245, 0xce);
gc4653_write_register(ViPipe, 0x0530, 0x20);
gc4653_write_register(ViPipe, 0x0531, 0x02);
gc4653_write_register(ViPipe, 0x0228, 0x50);
gc4653_write_register(ViPipe, 0x02ab, 0x00);
gc4653_write_register(ViPipe, 0x0250, 0x00);
gc4653_write_register(ViPipe, 0x0221, 0x50);
gc4653_write_register(ViPipe, 0x02ac, 0x00);
gc4653_write_register(ViPipe, 0x02a5, 0x02);
gc4653_write_register(ViPipe, 0x0260, 0x0b);
gc4653_write_register(ViPipe, 0x0216, 0x04);
gc4653_write_register(ViPipe, 0x0299, 0x1C);
gc4653_write_register(ViPipe, 0x02bb, 0x0d);
gc4653_write_register(ViPipe, 0x02a3, 0x02);
gc4653_write_register(ViPipe, 0x02a4, 0x02);
gc4653_write_register(ViPipe, 0x021e, 0x02);
gc4653_write_register(ViPipe, 0x024f, 0x08);
gc4653_write_register(ViPipe, 0x028c, 0x08);
gc4653_write_register(ViPipe, 0x0532, 0x3f);
gc4653_write_register(ViPipe, 0x0533, 0x02);
gc4653_write_register(ViPipe, 0x0277, 0xc0);
gc4653_write_register(ViPipe, 0x0276, 0xc0);
gc4653_write_register(ViPipe, 0x0239, 0xc0);
/*exp*/
gc4653_write_register(ViPipe, 0x0202, 0x05);
gc4653_write_register(ViPipe, 0x0203, 0x46);
/*gain*/
gc4653_write_register(ViPipe, 0x0205, 0xc0);
gc4653_write_register(ViPipe, 0x02b0, 0x68);
/*dpc*/
gc4653_write_register(ViPipe, 0x0002, 0xa9);
gc4653_write_register(ViPipe, 0x0004, 0x01);
/*dark_sun*/
gc4653_write_register(ViPipe, 0x021a, 0x98);
gc4653_write_register(ViPipe, 0x0266, 0xa0);
gc4653_write_register(ViPipe, 0x0020, 0x01);
gc4653_write_register(ViPipe, 0x0021, 0x03);
gc4653_write_register(ViPipe, 0x0022, 0x00);
gc4653_write_register(ViPipe, 0x0023, 0x04);
/****************************************/
/*mipi*/
/****************************************/
/*********** AHD 30 ******************/
/*30fps*/
gc4653_write_register(ViPipe, 0x0342, 0x06);
gc4653_write_register(ViPipe, 0x0343, 0x40);
/*30fps*/
gc4653_write_register(ViPipe, 0x03fe, 0x10);
gc4653_write_register(ViPipe, 0x03fe, 0x00);
gc4653_write_register(ViPipe, 0x0106, 0x78);
gc4653_write_register(ViPipe, 0x0108, 0x0c);
gc4653_write_register(ViPipe, 0x0114, 0x01);
gc4653_write_register(ViPipe, 0x0115, 0x12);
gc4653_write_register(ViPipe, 0x0180, 0x46);
gc4653_write_register(ViPipe, 0x0181, 0x30);
gc4653_write_register(ViPipe, 0x0182, 0x05);
gc4653_write_register(ViPipe, 0x0185, 0x01);
gc4653_write_register(ViPipe, 0x03fe, 0x10);
gc4653_write_register(ViPipe, 0x03fe, 0x00);
gc4653_write_register(ViPipe, 0x0100, 0x09);
// 0x008e = 0x00, which means disabling bayer transformation when flip/mirroring
//gc4653_write_register(ViPipe, 0x008e, 0x00);
//fix FPN
gc4653_write_register(ViPipe, 0x0277, 0x38);
gc4653_write_register(ViPipe, 0x0276, 0xc0);
gc4653_write_register(ViPipe, 0x000f, 0x10);
gc4653_write_register(ViPipe, 0x0059, 0x00);//close dither
//otp
gc4653_write_register(ViPipe, 0x0080, 0x02);
gc4653_write_register(ViPipe, 0x0097, 0x0a);
gc4653_write_register(ViPipe, 0x0098, 0x10);
gc4653_write_register(ViPipe, 0x0099, 0x05);
gc4653_write_register(ViPipe, 0x009a, 0xb0);
gc4653_write_register(ViPipe, 0x0317, 0x08);
gc4653_write_register(ViPipe, 0x0a67, 0x80);
gc4653_write_register(ViPipe, 0x0a70, 0x03);
gc4653_write_register(ViPipe, 0x0a82, 0x00);
gc4653_write_register(ViPipe, 0x0a83, 0x10);
gc4653_write_register(ViPipe, 0x0a80, 0x2b);
gc4653_write_register(ViPipe, 0x05be, 0x00);
gc4653_write_register(ViPipe, 0x05a9, 0x01);
gc4653_write_register(ViPipe, 0x0313, 0x80);
gc4653_write_register(ViPipe, 0x05be, 0x01);
gc4653_write_register(ViPipe, 0x0317, 0x00);
gc4653_write_register(ViPipe, 0x0a67, 0x00);
gc4653_default_reg_init(ViPipe);
delay_ms(10);
printf("ViPipe:%d,===GC4653 1440P 30fps 10bit LINEAR Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/nextchip_n5/Makefile Normal file
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@ -0,0 +1,36 @@
SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_n5.a
TARGET_SO = $(MW_LIB)/libsns_n5.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

290
middleware/v2/component/isp/sensor/cv180x/nextchip_n5/n5_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_isp.h"
#include "n5_cmos_ex.h"
#include "n5_cmos_param.h"
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_COMMBUS_U g_aunN5_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
ISP_SNS_STATE_S *g_pastN5[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define N5_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastN5[dev])
#define N5_SENSOR_SET_CTX(dev, pstCtx) (g_pastN5[dev] = pstCtx)
#define N5_SENSOR_RESET_CTX(dev) (g_pastN5[dev] = CVI_NULL)
#define N5_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080)
#define N5_ID 0xE0
/****************************************************************************
* local variables and functions *
****************************************************************************/
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const N5_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
N5_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astN5_mode[pstSnsState->u8ImgMode];
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
N5_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstCfg0 = &pstSnsState->astSyncInfo[0];
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
N5_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
if (pstSensorImageMode->f32Fps <= 30) {
if (N5_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
u8SensorImageMode = N5_MODE_1080P_25P;
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
N5_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->u8ImgMode = N5_MODE_1080P_25P;
pstSnsState->enWDRMode = WDR_MODE_NONE;
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
N5_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &n5_rx_attr, sizeof(*pstRxAttr));
CVI_TRACE_SNS(CVI_DBG_ERR, "get n5_rx0_attr\n");
pstRxAttr->img_size.width = g_astN5_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astN5_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &n5_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = n5_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = n5_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_S32 n5_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunN5_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
N5_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
N5_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
N5_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
N5_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
(void) pstAeLib;
(void) pstAwbLib;
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = N5_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
(void) pstAeLib;
(void) pstAwbLib;
CVI_S32 s32Ret;
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, N5_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
ISP_SNS_OBJ_S stSnsN5_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnMirrorFlip = CVI_NULL,
.pfnStandby = CVI_NULL,
.pfnRestart = CVI_NULL,
.pfnWriteReg = n5_write_register,
.pfnReadReg = n5_read_register,
.pfnSetBusInfo = n5_set_bus_info,
.pfnSetInit = CVI_NULL,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = CVI_NULL,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = CVI_NULL,
.pfnSnsProbe = CVI_NULL,
};

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#ifndef __N5_CMOS_EX_H_
#define __N5_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
typedef enum _N5_MODE_E {
N5_MODE_H720_NT = 1,
N5_MODE_H720_PAL,
N5_MODE_720P_30P,
N5_MODE_720P_25P,
N5_MODE_960P_30P,
N5_MODE_960P_25P,
N5_MODE_1080P_30P,
N5_MODE_1080P_25P,
N5_MODE_1080P_60P,
N5_MODE_1080P_50P,
N5_MODE_4M_30P,
N5_MODE_4M_25P,
N5_MODE_8M_15P,
N5_MODE_8M_12_5P,
N5_MODE_NUM
} N5_MODE_E;
typedef enum _n5_outmode_sel {
N5_OUTMODE_1MUX_SD = 0,
N5_OUTMODE_1MUX_HD,
N5_OUTMODE_1MUX_FHD,
N5_OUTMODE_1MUX_FHD_HALF,
N5_OUTMODE_2MUX_SD,
N5_OUTMODE_2MUX_HD,
N5_OUTMODE_2MUX_FHD,
N5_OUTMODE_1MUX_BT1120S,
N5_OUTMODE_2MUX_BT1120S_720P,
N5_OUTMODE_2MUX_BT1120S_1080P,
N5_OUTMODE_BUTT
} N5_OUTMODE_SEL;
typedef struct _N5_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
SNS_ATTR_S stAgain[2];
SNS_ATTR_S stDgain[2];
CVI_U8 u8DgainReg;
char name[64];
} N5_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastN5[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunN5_BusInfo[];
extern const CVI_U8 n5_i2c_addr;
extern const CVI_U32 n5_addr_byte;
extern const CVI_U32 n5_data_byte;
extern void n5_init(VI_PIPE ViPipe);
extern void n5_exit(VI_PIPE ViPipe);
extern void n5_standby(VI_PIPE ViPipe);
extern void n5_restart(VI_PIPE ViPipe);
extern int n5_write_register(VI_PIPE ViPipe, int addr, int data);
extern int n5_read_register(VI_PIPE ViPipe, int addr);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __N5_CMOS_EX_H_ */

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#ifndef __N5_CMOS_PARAM_H_
#define __N5_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "n5_cmos_ex.h"
static const N5_MODE_S g_astN5_mode[N5_MODE_NUM] = {
[N5_MODE_1080P_25P] = {
.name = "1080p25",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1280,
.u32Height = 720,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1280,
.u32Height = 720,
},
.stMaxSize = {
.u32Width = 1280,
.u32Height = 720,
},
},
},
};
struct combo_dev_attr_s n5_rx_attr = {
.input_mode = INPUT_MODE_BT_DEMUX,
.mac_clk = RX_MAC_CLK_400M,
.mclk = {
.cam = 1,
.freq = CAMPLL_FREQ_27M,
},
.bt_demux_attr = {
.func = {
-1, -1, -1, -1,
0, 1, 2, 3, 4, 5, 6, 7,
-1, -1, -1, -1,
-1, -1, -1, -1
},
.v_fp = 0xF,
.h_fp = 0xF,
.v_bp = 0,
.h_bp = 0,
.mode = BT_DEMUX_2,
.sync_code_part_A = {0xFF, 0, 0},
.sync_code_part_B[0] = {
.sav_vld = 0x80,
.sav_blk = 0xa0,
.eav_vld = 0x90,
.eav_blk = 0xb0,
},
.sync_code_part_B[1] = {
.sav_vld = 0x81,
.sav_blk = 0xa1,
.eav_vld = 0x91,
.eav_blk = 0xb1,
},
.sync_code_part_B[2] = {
.sav_vld = 0x82,
.sav_blk = 0xa2,
.eav_vld = 0x92,
.eav_blk = 0xb2,
},
.sync_code_part_B[3] = {
.sav_vld = 0x83,
.sav_blk = 0xa3,
.eav_vld = 0x93,
.eav_blk = 0xb3,
},
.yc_exchg = 0xF,
},
.devno = 0, // btdemux must use mac0
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __N5_CMOS_PARAM_H_ */

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_n6.a
TARGET_SO = $(MW_LIB)/libsns_n6.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_isp.h"
#include "n6_cmos_ex.h"
#include "n6_cmos_param.h"
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_COMMBUS_U g_aunN6_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
ISP_SNS_STATE_S *g_pastN6[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define N6_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastN6[dev])
#define N6_SENSOR_SET_CTX(dev, pstCtx) (g_pastN6[dev] = pstCtx)
#define N6_SENSOR_RESET_CTX(dev) (g_pastN6[dev] = CVI_NULL)
#define N6_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080)
#define N6_ID 0xE0
/****************************************************************************
* local variables and functions *
****************************************************************************/
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const N6_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
N6_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astN6_mode[pstSnsState->u8ImgMode];
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
N6_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstCfg0 = &pstSnsState->astSyncInfo[0];
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
N6_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
if (pstSensorImageMode->f32Fps <= 30) {
if (N6_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
u8SensorImageMode = N6_MODE_1080P_25P;
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
N6_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->u8ImgMode = N6_MODE_1080P_25P;
pstSnsState->enWDRMode = WDR_MODE_NONE;
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
N6_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &n6_rx_attr, sizeof(*pstRxAttr));
CVI_TRACE_SNS(CVI_DBG_ERR, "get n6_rx0_attr\n");
pstRxAttr->img_size.width = g_astN6_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astN6_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &n6_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = n6_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = n6_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_S32 n6_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunN6_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
N6_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
N6_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
N6_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
N6_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
(void) pstAeLib;
(void) pstAwbLib;
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = N6_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
(void) pstAeLib;
(void) pstAwbLib;
CVI_S32 s32Ret;
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, N6_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
ISP_SNS_OBJ_S stSnsN6_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnMirrorFlip = CVI_NULL,
.pfnStandby = CVI_NULL,
.pfnRestart = CVI_NULL,
.pfnWriteReg = n6_write_register,
.pfnReadReg = n6_read_register,
.pfnSetBusInfo = n6_set_bus_info,
.pfnSetInit = CVI_NULL,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = CVI_NULL,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = CVI_NULL,
.pfnSnsProbe = CVI_NULL,
};

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#ifndef __N6_CMOS_EX_H_
#define __N6_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
typedef enum _N6_MODE_E {
N6_MODE_H720_NT = 1,
N6_MODE_H720_PAL,
N6_MODE_720P_30P,
N6_MODE_720P_25P,
N6_MODE_960P_30P,
N6_MODE_960P_25P,
N6_MODE_1080P_30P,
N6_MODE_1080P_25P,
N6_MODE_1080P_60P,
N6_MODE_1080P_50P,
N6_MODE_4M_30P,
N6_MODE_4M_25P,
N6_MODE_8M_15P,
N6_MODE_8M_12_5P,
N6_MODE_NUM
} N6_MODE_E;
typedef enum _n6_outmode_sel {
N6_OUTMODE_1MUX_SD = 0,
N6_OUTMODE_1MUX_HD,
N6_OUTMODE_1MUX_FHD,
N6_OUTMODE_1MUX_FHD_HALF,
N6_OUTMODE_2MUX_SD,
N6_OUTMODE_2MUX_HD,
N6_OUTMODE_2MUX_FHD,
N6_OUTMODE_1MUX_BT1120S,
N6_OUTMODE_2MUX_BT1120S_720P,
N6_OUTMODE_2MUX_BT1120S_1080P,
N6_OUTMODE_BUTT
} N6_OUTMODE_SEL;
typedef struct _N6_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
SNS_ATTR_S stAgain[2];
SNS_ATTR_S stDgain[2];
CVI_U8 u8DgainReg;
char name[64];
} N6_MODE_S;
#define _MIPI_PORT0_
//#define _MIPI_PORT1_
#ifdef _MIPI_PORT0_
#define _MAR_BANK_ 0x20
#define _MTX_BANK_ 0x23
#else
#define _MAR_BANK_ 0x30
#define _MTX_BANK_ 0x33
#endif
#define CH0_NO 0
#define CH1_NO 1
#define NTPAL 0
#define VFMT_NTSC 0
#define VFMT_PAL 1
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastN6[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunN6_BusInfo[];
extern const CVI_U8 n6_i2c_addr;
extern const CVI_U32 n6_addr_byte;
extern const CVI_U32 n6_data_byte;
extern void n6_init(VI_PIPE ViPipe);
extern void n6_exit(VI_PIPE ViPipe);
extern void n6_standby(VI_PIPE ViPipe);
extern void n6_restart(VI_PIPE ViPipe);
extern int n6_write_register(VI_PIPE ViPipe, int addr, int data);
extern int n6_read_register(VI_PIPE ViPipe, int addr);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __N6_CMOS_EX_H_ */

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#ifndef __N6_CMOS_PARAM_H_
#define __N6_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "n6_cmos_ex.h"
static const N6_MODE_S g_astN6_mode[N6_MODE_NUM] = {
[N6_MODE_1080P_25P] = {
.name = "1080p25",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
},
};
struct combo_dev_attr_s n6_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_400M,
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_27M,
},
.mipi_attr = {
.raw_data_type = YUV422_8BIT,
.lane_id = {2, 0, 1, 3, 4},
.pn_swap = {1, 1, 1, 1, 1},
.wdr_mode = CVI_MIPI_WDR_MODE_VC,
.demux = {
.demux_en = 1,
.vc_mapping = {0, 1, 2, 3},
},
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __N6_CMOS_PARAM_H_ */

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middleware/v2/component/isp/sensor/cv180x/nextchip_n6/n6_sensor_ctrl.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include <linux/spi/spidev.h>
#include "cvi_sns_ctrl.h"
#include "n6_cmos_ex.h"
#include <pthread.h>
#include <signal.h>
const CVI_U8 n6_i2c_addr = 0x31; /* I2C slave address of N6, SA0=0:0x32, SA0=1:0x33*/
const CVI_U32 n6_addr_byte = 1;
const CVI_U32 n6_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
static CVI_U32 adet;
//static CVI_U32 fmt = 1; //0:960h 1:720P 2:1080P
//static unsigned int ntpal = 0; //0:ntsc/30p 1:pal/25p
static CVI_U32 mclk = 1; //0:1458 1:756
#define N6_TEST_PATTERN 1
int n6_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunN6_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
syslog(LOG_DEBUG, "open %s\n", acDevFile);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, n6_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int n6_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int n6_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return 0;
if (n6_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, n6_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return 0;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, n6_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return 0;
}
// pack read back data
data = 0;
if (n6_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int n6_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (n6_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
if (n6_data_byte == 2)
buf[idx++] = (data >> 8) & 0xff;
// add data byte 0
buf[idx++] = data & 0xff;
ret = write(g_fd[ViPipe], buf, n6_addr_byte + n6_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
#if 0 // read back checing
ret = n6_read_register(ViPipe, addr);
if (ret != data)
syslog(LOG_DEBUG, "i2c readback-check fail, 0x%x != 0x%x\n", ret, data);
#endif
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void n6_common_setting(VI_PIPE ViPipe)
{
CVI_U8 ch;
n6_write_register(ViPipe, 0xff, 0x00);
n6_write_register(ViPipe, 0x80, 0x0f);
n6_write_register(ViPipe, 0x00, 0x10);
n6_write_register(ViPipe, 0x01, 0x10);
n6_write_register(ViPipe, 0x02, 0x10);
n6_write_register(ViPipe, 0x03, 0x10);
n6_write_register(ViPipe, 0x22, 0x0b);
n6_write_register(ViPipe, 0x23, 0x41);
n6_write_register(ViPipe, 0x26, 0x0b);
n6_write_register(ViPipe, 0x27, 0x41);
n6_write_register(ViPipe, 0x2a, 0x0b);
n6_write_register(ViPipe, 0x2b, 0x41);
n6_write_register(ViPipe, 0x2e, 0x0b);
n6_write_register(ViPipe, 0x2f, 0x41);
n6_write_register(ViPipe, 0xff, 0x01);
n6_write_register(ViPipe, 0x98, 0x30);
n6_write_register(ViPipe, 0xed, 0x00);
for (ch = 0; ch < 4; ch++) {
n6_write_register(ViPipe, 0xff, 0x05 + ch);
n6_write_register(ViPipe, 0x00, 0xd0);
n6_write_register(ViPipe, 0x01, 0x22);
n6_write_register(ViPipe, 0x47, 0xee);
n6_write_register(ViPipe, 0x50, 0xc6);
n6_write_register(ViPipe, 0x57, 0x00);
n6_write_register(ViPipe, 0x58, 0x77);
n6_write_register(ViPipe, 0x5b, 0x41);
n6_write_register(ViPipe, 0x5c, 0x78);
n6_write_register(ViPipe, 0xB8, 0xB8);
}
n6_write_register(ViPipe, 0xff, 0x09);
n6_write_register(ViPipe, 0x50, 0x30);
n6_write_register(ViPipe, 0x51, 0x6f);
n6_write_register(ViPipe, 0x52, 0x67);
n6_write_register(ViPipe, 0x53, 0x48);
n6_write_register(ViPipe, 0x54, 0x30);
n6_write_register(ViPipe, 0x55, 0x6f);
n6_write_register(ViPipe, 0x56, 0x67);
n6_write_register(ViPipe, 0x57, 0x48);
n6_write_register(ViPipe, 0x58, 0x30);
n6_write_register(ViPipe, 0x59, 0x6f);
n6_write_register(ViPipe, 0x5a, 0x67);
n6_write_register(ViPipe, 0x5b, 0x48);
n6_write_register(ViPipe, 0x5c, 0x30);
n6_write_register(ViPipe, 0x5d, 0x6f);
n6_write_register(ViPipe, 0x5e, 0x67);
n6_write_register(ViPipe, 0x5f, 0x48);
n6_write_register(ViPipe, 0xff, 0x0a);
n6_write_register(ViPipe, 0x25, 0x10);
n6_write_register(ViPipe, 0x27, 0x1e);
n6_write_register(ViPipe, 0x30, 0xac);
n6_write_register(ViPipe, 0x31, 0x78);
n6_write_register(ViPipe, 0x32, 0x17);
n6_write_register(ViPipe, 0x33, 0xc1);
n6_write_register(ViPipe, 0x34, 0x40);
n6_write_register(ViPipe, 0x35, 0x00);
n6_write_register(ViPipe, 0x36, 0xc3);
n6_write_register(ViPipe, 0x37, 0x0a);
n6_write_register(ViPipe, 0x38, 0x00);
n6_write_register(ViPipe, 0x39, 0x02);
n6_write_register(ViPipe, 0x3a, 0x00);
n6_write_register(ViPipe, 0x3b, 0xb2);
n6_write_register(ViPipe, 0xa5, 0x10);
n6_write_register(ViPipe, 0xa7, 0x1e);
n6_write_register(ViPipe, 0xb0, 0xac);
n6_write_register(ViPipe, 0xb1, 0x78);
n6_write_register(ViPipe, 0xb2, 0x17);
n6_write_register(ViPipe, 0xb3, 0xc1);
n6_write_register(ViPipe, 0xb4, 0x40);
n6_write_register(ViPipe, 0xb5, 0x00);
n6_write_register(ViPipe, 0xb6, 0xc3);
n6_write_register(ViPipe, 0xb7, 0x0a);
n6_write_register(ViPipe, 0xb8, 0x00);
n6_write_register(ViPipe, 0xb9, 0x02);
n6_write_register(ViPipe, 0xba, 0x00);
n6_write_register(ViPipe, 0xbb, 0xb2);
n6_write_register(ViPipe, 0xff, 0x0b);
n6_write_register(ViPipe, 0x25, 0x10);
n6_write_register(ViPipe, 0x27, 0x1e);
n6_write_register(ViPipe, 0x30, 0xac);
n6_write_register(ViPipe, 0x31, 0x78);
n6_write_register(ViPipe, 0x32, 0x17);
n6_write_register(ViPipe, 0x33, 0xc1);
n6_write_register(ViPipe, 0x34, 0x40);
n6_write_register(ViPipe, 0x35, 0x00);
n6_write_register(ViPipe, 0x36, 0xc3);
n6_write_register(ViPipe, 0x37, 0x0a);
n6_write_register(ViPipe, 0x38, 0x00);
n6_write_register(ViPipe, 0x39, 0x02);
n6_write_register(ViPipe, 0x3a, 0x00);
n6_write_register(ViPipe, 0x3b, 0xb2);
n6_write_register(ViPipe, 0xa5, 0x10);
n6_write_register(ViPipe, 0xa7, 0x1e);
n6_write_register(ViPipe, 0xb0, 0xac);
n6_write_register(ViPipe, 0xb1, 0x78);
n6_write_register(ViPipe, 0xb2, 0x17);
n6_write_register(ViPipe, 0xb3, 0xc1);
n6_write_register(ViPipe, 0xb4, 0x40);
n6_write_register(ViPipe, 0xb5, 0x00);
n6_write_register(ViPipe, 0xb6, 0xc3);
n6_write_register(ViPipe, 0xb7, 0x0a);
n6_write_register(ViPipe, 0xb8, 0x00);
n6_write_register(ViPipe, 0xb9, 0x02);
n6_write_register(ViPipe, 0xba, 0x00);
n6_write_register(ViPipe, 0xbb, 0xb2);
n6_write_register(ViPipe, 0xff, 0x13);
n6_write_register(ViPipe, 0x05, 0xa0);
n6_write_register(ViPipe, 0x31, 0xff);
n6_write_register(ViPipe, 0x07, 0x47);
n6_write_register(ViPipe, 0x12, 0x04);
n6_write_register(ViPipe, 0x1e, 0x1f);
n6_write_register(ViPipe, 0x1f, 0x27);
n6_write_register(ViPipe, 0x2e, 0x10);
n6_write_register(ViPipe, 0x2f, 0xc8);
n6_write_register(ViPipe, 0x31, 0xff);
n6_write_register(ViPipe, 0x32, 0x00);
n6_write_register(ViPipe, 0x33, 0x00);
n6_write_register(ViPipe, 0x72, 0x05);
n6_write_register(ViPipe, 0x7a, 0xf0);
n6_write_register(ViPipe, 0xff, _MAR_BANK_);
n6_write_register(ViPipe, 0x10, 0xff);
n6_write_register(ViPipe, 0x11, 0xff);
if (mclk == 1) {
n6_write_register(ViPipe, 0x30, 0x0f);
n6_write_register(ViPipe, 0x32, 0x92);
n6_write_register(ViPipe, 0x34, 0xcd);
n6_write_register(ViPipe, 0x36, 0x04);
n6_write_register(ViPipe, 0x38, 0x58);
} else {
n6_write_register(ViPipe, 0x30, 0x0f);
n6_write_register(ViPipe, 0x32, 0xff);
n6_write_register(ViPipe, 0x34, 0xcd);
n6_write_register(ViPipe, 0x36, 0x04);
n6_write_register(ViPipe, 0x38, 0xff);
}
n6_write_register(ViPipe, 0x3c, 0x01);
n6_write_register(ViPipe, 0x3d, 0x11);
n6_write_register(ViPipe, 0x3e, 0x11);
n6_write_register(ViPipe, 0x45, 0x60);
n6_write_register(ViPipe, 0x46, 0x49);
n6_write_register(ViPipe, 0xff, _MTX_BANK_);
n6_write_register(ViPipe, 0xe9, 0x03);
n6_write_register(ViPipe, 0x03, 0x02);
n6_write_register(ViPipe, 0x01, 0xe4);
n6_write_register(ViPipe, 0x00, 0x7d);
n6_write_register(ViPipe, 0x01, 0xe0);
n6_write_register(ViPipe, 0x02, 0xa0);
n6_write_register(ViPipe, 0x20, 0x1e);
n6_write_register(ViPipe, 0x20, 0x1f);
if (mclk == 1) {
n6_write_register(ViPipe, 0x04, 0x38);
n6_write_register(ViPipe, 0x45, 0xc4);
n6_write_register(ViPipe, 0x46, 0x01);
n6_write_register(ViPipe, 0x47, 0x1b);
n6_write_register(ViPipe, 0x48, 0x08);
n6_write_register(ViPipe, 0x65, 0xc4);
n6_write_register(ViPipe, 0x66, 0x01);
n6_write_register(ViPipe, 0x67, 0x1b);
n6_write_register(ViPipe, 0x68, 0x08);
n6_write_register(ViPipe, 0x85, 0xc4);
n6_write_register(ViPipe, 0x86, 0x01);
n6_write_register(ViPipe, 0x87, 0x1b);
n6_write_register(ViPipe, 0x88, 0x08);
n6_write_register(ViPipe, 0xa5, 0xc4);
n6_write_register(ViPipe, 0xa6, 0x01);
n6_write_register(ViPipe, 0xa7, 0x1b);
n6_write_register(ViPipe, 0xa8, 0x08);
n6_write_register(ViPipe, 0xc5, 0xc4);
n6_write_register(ViPipe, 0xc6, 0x01);
n6_write_register(ViPipe, 0xc7, 0x1b);
n6_write_register(ViPipe, 0xc8, 0x08);
} else {
n6_write_register(ViPipe, 0x04, 0x6c);
n6_write_register(ViPipe, 0x45, 0xcd);
n6_write_register(ViPipe, 0x46, 0x42);
n6_write_register(ViPipe, 0x47, 0x36);
n6_write_register(ViPipe, 0x48, 0x0f);
n6_write_register(ViPipe, 0x65, 0xcd);
n6_write_register(ViPipe, 0x66, 0x42);
n6_write_register(ViPipe, 0x67, 0x0e);
n6_write_register(ViPipe, 0x68, 0x0f);
n6_write_register(ViPipe, 0x85, 0xcd);
n6_write_register(ViPipe, 0x86, 0x42);
n6_write_register(ViPipe, 0x87, 0x0e);
n6_write_register(ViPipe, 0x88, 0x0f);
n6_write_register(ViPipe, 0xa5, 0xcd);
n6_write_register(ViPipe, 0xa6, 0x42);
n6_write_register(ViPipe, 0xa7, 0x0e);
n6_write_register(ViPipe, 0xa8, 0x0f);
n6_write_register(ViPipe, 0xc5, 0xcd);
n6_write_register(ViPipe, 0xc6, 0x42);
n6_write_register(ViPipe, 0xc7, 0x0e);
n6_write_register(ViPipe, 0xc8, 0x0f);
}
n6_write_register(ViPipe, 0xeb, 0x8d);
n6_write_register(ViPipe, 0xff, _MAR_BANK_);
n6_write_register(ViPipe, 0x00, 0xff);
n6_write_register(ViPipe, 0x40, 0x01);
n6_write_register(ViPipe, 0x40, 0x00);
n6_write_register(ViPipe, 0xff, 0x01);
n6_write_register(ViPipe, 0x97, 0x00);
n6_write_register(ViPipe, 0x97, 0x0f);
n6_write_register(ViPipe, 0xff, 0x00); //test pattern
n6_write_register(ViPipe, 0x78, 0xba);
n6_write_register(ViPipe, 0x79, 0xac);
n6_write_register(ViPipe, 0xff, 0x05);
n6_write_register(ViPipe, 0x2c, 0x08);
n6_write_register(ViPipe, 0x6a, 0x80);
n6_write_register(ViPipe, 0xff, 0x06);
n6_write_register(ViPipe, 0x2c, 0x08);
n6_write_register(ViPipe, 0x6a, 0x80);
n6_write_register(ViPipe, 0xff, 0x07);
n6_write_register(ViPipe, 0x2c, 0x08);
n6_write_register(ViPipe, 0x6a, 0x80);
n6_write_register(ViPipe, 0xff, 0x08);
n6_write_register(ViPipe, 0x2c, 0x08);
n6_write_register(ViPipe, 0x6a, 0x80);
}
void n6_set_chn_960h(VI_PIPE ViPipe, CVI_U8 ch, CVI_U8 ntpal)
{
CVI_U8 val_0x54, val_20x01;
CVI_TRACE_SNS(CVI_DBG_INFO, "%s ch=%d\n", __func__, ch);
n6_write_register(ViPipe, 0xff, 0x00);
n6_write_register(ViPipe, 0x08 + ch, ntpal ? 0xdd : 0xa0);
n6_write_register(ViPipe, 0x18 + ch, 0x08);
n6_write_register(ViPipe, 0x22 + ch * 4, 0x0b);
n6_write_register(ViPipe, 0x23 + ch * 4, 0x41);
n6_write_register(ViPipe, 0x30 + ch, 0x12);
n6_write_register(ViPipe, 0x34 + ch, 0x01);
val_0x54 = n6_read_register(ViPipe, 0x54);
if (ntpal)
val_0x54 &= ~(0x10 << ch);
else
val_0x54 |= (0x10 << ch);
n6_write_register(ViPipe, 0x54, val_0x54);
n6_write_register(ViPipe, 0x58 + ch, ntpal ? 0x80 : 0x90);
n6_write_register(ViPipe, 0x5c + ch, ntpal ? 0xbe : 0xbc);
n6_write_register(ViPipe, 0x64 + ch, ntpal ? 0xa0 : 0x81);
n6_write_register(ViPipe, 0x81 + ch, ntpal ? 0xf0 : 0xe0);
n6_write_register(ViPipe, 0x85 + ch, 0x00);
n6_write_register(ViPipe, 0x89 + ch, 0x00);
n6_write_register(ViPipe, 0x8e + ch, 0x00);
n6_write_register(ViPipe, 0xa0 + ch, 0x05);
n6_write_register(ViPipe, 0xff, 0x01);
n6_write_register(ViPipe, 0x84 + ch, 0x02);
n6_write_register(ViPipe, 0x88 + ch, 0x00);
n6_write_register(ViPipe, 0x8c + ch, 0x40);
n6_write_register(ViPipe, 0xa0 + ch, 0x20);
n6_write_register(ViPipe, 0xed, 0x00);
n6_write_register(ViPipe, 0xff, 0x05 + ch);
n6_write_register(ViPipe, 0x01, 0x22);
n6_write_register(ViPipe, 0x05, 0x00);
n6_write_register(ViPipe, 0x08, 0x55);
n6_write_register(ViPipe, 0x25, 0xdc);
n6_write_register(ViPipe, 0x28, 0x80);
n6_write_register(ViPipe, 0x2f, 0x00);
n6_write_register(ViPipe, 0x30, 0xe0);
n6_write_register(ViPipe, 0x31, 0x43);
n6_write_register(ViPipe, 0x32, 0xa2);
n6_write_register(ViPipe, 0x47, 0x04);
n6_write_register(ViPipe, 0x50, 0x84);
n6_write_register(ViPipe, 0x57, 0x00);
n6_write_register(ViPipe, 0x58, 0x77);
n6_write_register(ViPipe, 0x5b, 0x43);
n6_write_register(ViPipe, 0x5c, 0x78);
n6_write_register(ViPipe, 0x5f, 0x00);
n6_write_register(ViPipe, 0x62, 0x20);
n6_write_register(ViPipe, 0x7b, 0x00);
n6_write_register(ViPipe, 0x7c, 0x01);
n6_write_register(ViPipe, 0x7d, 0x80);
n6_write_register(ViPipe, 0x80, 0x00);
n6_write_register(ViPipe, 0x90, 0x01);
n6_write_register(ViPipe, 0xa9, 0x00);
n6_write_register(ViPipe, 0xb5, 0x00);
n6_write_register(ViPipe, 0xb8, 0xb9);
n6_write_register(ViPipe, 0xb9, 0x72);
n6_write_register(ViPipe, 0xd1, 0x00);
n6_write_register(ViPipe, 0xd5, 0x80);
n6_write_register(ViPipe, 0xff, 0x09);
n6_write_register(ViPipe, 0x96 + ch * 0x20, 0x10);
n6_write_register(ViPipe, 0x98 + ch * 0x20, ntpal ? 0xc0 : 0xe0);
n6_write_register(ViPipe, 0x9e + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0xff, _MAR_BANK_);
val_20x01 = n6_read_register(ViPipe, 0x01);
val_20x01 &= (~(0x03 << (ch * 2)));
val_20x01 |= (0x02 << (ch * 2));
n6_write_register(ViPipe, 0x01, val_20x01);
n6_write_register(ViPipe, 0x12 + ch * 2, 0xe0);
n6_write_register(ViPipe, 0x13 + ch * 2, 0x01);
}
void n6_set_chn_720p(VI_PIPE ViPipe, CVI_U8 ch, CVI_U8 ntpal)
{
CVI_U8 val_0x54, val_20x01;
CVI_TRACE_SNS(CVI_DBG_INFO, "%s ch=%d\n", __func__, ch);
n6_write_register(ViPipe, 0xff, 0x00);
n6_write_register(ViPipe, 0x08 + ch, 0x00);
n6_write_register(ViPipe, 0x18 + ch, 0x3f);
n6_write_register(ViPipe, 0x30 + ch, 0x12);
n6_write_register(ViPipe, 0x34 + ch, 0x00);
val_0x54 = n6_read_register(ViPipe, 0x54);
val_0x54 &= ~(0x10 << ch);
n6_write_register(ViPipe, 0x54, val_0x54);
n6_write_register(ViPipe, 0x58 + ch, ntpal ? 0x80 : 0x80);
n6_write_register(ViPipe, 0x5c + ch, ntpal ? 0x00 : 0x00);
n6_write_register(ViPipe, 0x64 + ch, ntpal ? 0x01 : 0x01);
n6_write_register(ViPipe, 0x81 + ch, ntpal ? 0x0d : 0x0c);
n6_write_register(ViPipe, 0x85 + ch, 0x00);
n6_write_register(ViPipe, 0x89 + ch, 0x00);
n6_write_register(ViPipe, 0x8e + ch, 0x00);
n6_write_register(ViPipe, 0xa0 + ch, 0x05);
n6_write_register(ViPipe, 0xff, 0x01);
n6_write_register(ViPipe, 0x84 + ch, 0x02);
n6_write_register(ViPipe, 0x88 + ch, 0x00);
n6_write_register(ViPipe, 0x8c + ch, 0x40);
n6_write_register(ViPipe, 0xa0 + ch, 0x20);
n6_write_register(ViPipe, 0xff, 0x05 + ch);
n6_write_register(ViPipe, 0x01, 0x22);
n6_write_register(ViPipe, 0x05, 0x04);
n6_write_register(ViPipe, 0x08, 0x55);
n6_write_register(ViPipe, 0x25, 0xdc);
n6_write_register(ViPipe, 0x28, 0x80);
n6_write_register(ViPipe, 0x2f, 0x00);
n6_write_register(ViPipe, 0x30, 0xe0);
n6_write_register(ViPipe, 0x31, 0x43);
n6_write_register(ViPipe, 0x32, 0xa2);
n6_write_register(ViPipe, 0x47, 0xee);
n6_write_register(ViPipe, 0x50, 0xc6);
n6_write_register(ViPipe, 0x57, 0x00);
n6_write_register(ViPipe, 0x58, 0x77);
n6_write_register(ViPipe, 0x5b, 0x41);
n6_write_register(ViPipe, 0x5c, 0x7C);
n6_write_register(ViPipe, 0x5f, 0x00);
n6_write_register(ViPipe, 0x62, 0x20);
n6_write_register(ViPipe, 0x7b, 0x11);
n6_write_register(ViPipe, 0x7c, 0x01);
n6_write_register(ViPipe, 0x7d, 0x80);
n6_write_register(ViPipe, 0x80, 0x00);
n6_write_register(ViPipe, 0x90, 0x01);
n6_write_register(ViPipe, 0xa9, 0x00);
n6_write_register(ViPipe, 0xb5, 0x40);
n6_write_register(ViPipe, 0xb8, 0x39);
n6_write_register(ViPipe, 0xb9, 0x72);
n6_write_register(ViPipe, 0xd1, 0x00);
n6_write_register(ViPipe, 0xd5, 0x80);
n6_write_register(ViPipe, 0xff, 0x09);
n6_write_register(ViPipe, 0x96 + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0x98 + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0x9e + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0xff, _MAR_BANK_);
val_20x01 = n6_read_register(ViPipe, 0x01);
val_20x01 &= (~(0x03 << (ch * 2)));
val_20x01 |= (0x01 << (ch * 2));
n6_write_register(ViPipe, 0x01, val_20x01);
n6_write_register(ViPipe, 0x12 + ch * 2, 0x80);
n6_write_register(ViPipe, 0x13 + ch * 2, 0x02);
}
/*
* 1280x960p
* dev:0x60 / 0x62 / 0x64 / 0x66
* ch : 0 ~ 3
* ntpal: 1:25p, 0:30p
*/
void n6_set_chn_960p(VI_PIPE ViPipe, CVI_U8 ch, CVI_U8 ntpal)
{
CVI_U8 val_0x54, val_20x01;
CVI_TRACE_SNS(CVI_DBG_INFO, "%s ch=%d\n", __func__, ch);
n6_write_register(ViPipe, 0xff, 0x00);
n6_write_register(ViPipe, 0x08 + ch, 0x00);
n6_write_register(ViPipe, 0x18 + ch, 0x0f);
n6_write_register(ViPipe, 0x30 + ch, 0x12);
n6_write_register(ViPipe, 0x34 + ch, 0x00);
val_0x54 = n6_read_register(ViPipe, 0x54);
val_0x54 &= ~(0x10 << ch);
n6_write_register(ViPipe, 0x54, val_0x54);
n6_write_register(ViPipe, 0x58 + ch, ntpal ? 0x40 : 0x48);
n6_write_register(ViPipe, 0x5c + ch, ntpal ? 0x80 : 0x80);
n6_write_register(ViPipe, 0x64 + ch, ntpal ? 0x28 : 0x28);
n6_write_register(ViPipe, 0x81 + ch, ntpal ? 0x07 : 0x06);
n6_write_register(ViPipe, 0x85 + ch, 0x0b);
n6_write_register(ViPipe, 0x89 + ch, 0x00);
n6_write_register(ViPipe, 0x8e + ch, 0x00);
n6_write_register(ViPipe, 0xa0 + ch, 0x05);
n6_write_register(ViPipe, 0xff, 0x01);
n6_write_register(ViPipe, 0x84 + ch, 0x02);
n6_write_register(ViPipe, 0x88 + ch, 0x00);
n6_write_register(ViPipe, 0x8c + ch, 0x40);
n6_write_register(ViPipe, 0xa0 + ch, 0x20);
n6_write_register(ViPipe, 0xff, 0x05 + ch);
n6_write_register(ViPipe, 0x01, 0x22);
n6_write_register(ViPipe, 0x05, 0x04);
n6_write_register(ViPipe, 0x08, 0x55);
n6_write_register(ViPipe, 0x25, 0xdc);
n6_write_register(ViPipe, 0x28, 0x80);
n6_write_register(ViPipe, 0x2f, 0x00);
n6_write_register(ViPipe, 0x30, 0xe0);
n6_write_register(ViPipe, 0x31, 0x43);
n6_write_register(ViPipe, 0x32, 0xa2);
n6_write_register(ViPipe, 0x47, 0xee);
n6_write_register(ViPipe, 0x50, 0xc6);
n6_write_register(ViPipe, 0x57, 0x00);
n6_write_register(ViPipe, 0x58, 0x77);
n6_write_register(ViPipe, 0x5b, 0x41);
n6_write_register(ViPipe, 0x5c, 0x7C);
n6_write_register(ViPipe, 0x5f, 0x00);
n6_write_register(ViPipe, 0x62, 0x20);
n6_write_register(ViPipe, 0x7b, 0x11);
n6_write_register(ViPipe, 0x7c, 0x01);
n6_write_register(ViPipe, 0x7d, 0x80);
n6_write_register(ViPipe, 0x80, 0x00);
n6_write_register(ViPipe, 0x90, 0x01);
n6_write_register(ViPipe, 0xa9, 0x00);
n6_write_register(ViPipe, 0xb5, 0x40);
n6_write_register(ViPipe, 0xb8, 0x39);
n6_write_register(ViPipe, 0xb9, 0x72);
n6_write_register(ViPipe, 0xd1, 0x00);
n6_write_register(ViPipe, 0xd5, 0x80);
n6_write_register(ViPipe, 0xff, 0x09);
n6_write_register(ViPipe, 0x96 + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0x98 + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0x9e + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0xff, _MAR_BANK_);
val_20x01 = n6_read_register(ViPipe, 0x01);
val_20x01 &= (~(0x03 << (ch * 2)));
//val_20x01 |=(0x01<<(ch*2));
n6_write_register(ViPipe, 0x01, val_20x01);
n6_write_register(ViPipe, 0x12 + ch * 2, 0x80);
n6_write_register(ViPipe, 0x13 + ch * 2, 0x02);
}
void n6_set_chn_1080p(VI_PIPE ViPipe, CVI_U8 ch, CVI_U8 ntpal)
{
CVI_U8 val_0x54, val_20x01;
CVI_TRACE_SNS(CVI_DBG_INFO, "%s ch=%d\n", __func__, ch);
n6_write_register(ViPipe, 0xff, 0x00);
n6_write_register(ViPipe, 0x08 + ch, 0x00);
n6_write_register(ViPipe, 0x18 + ch, 0x3f);
n6_write_register(ViPipe, 0x30 + ch, 0x12);
n6_write_register(ViPipe, 0x34 + ch, 0x00);
val_0x54 = n6_read_register(ViPipe, 0x54);
val_0x54 &= ~(0x10 << ch);
n6_write_register(ViPipe, 0x54, val_0x54);
n6_write_register(ViPipe, 0x58 + ch, ntpal ? 0x80 : 0x80);
n6_write_register(ViPipe, 0x5c + ch, ntpal ? 0x00 : 0x00);
n6_write_register(ViPipe, 0x64 + ch, ntpal ? 0x01 : 0x01);
n6_write_register(ViPipe, 0x81 + ch, ntpal ? 0x03 : 0x02);
n6_write_register(ViPipe, 0x85 + ch, 0x00);
n6_write_register(ViPipe, 0x89 + ch, 0x10);
n6_write_register(ViPipe, 0x8e + ch, 0x00);
n6_write_register(ViPipe, 0xa0 + ch, 0x05);
n6_write_register(ViPipe, 0xff, 0x01);
n6_write_register(ViPipe, 0x84 + ch, 0x02);
n6_write_register(ViPipe, 0x88 + ch, 0x00);
n6_write_register(ViPipe, 0x8c + ch, 0x40);
n6_write_register(ViPipe, 0xa0 + ch, 0x20);
n6_write_register(ViPipe, 0xff, 0x05 + ch);
n6_write_register(ViPipe, 0x01, 0x22);
n6_write_register(ViPipe, 0x05, 0x04);
n6_write_register(ViPipe, 0x08, 0x55);
n6_write_register(ViPipe, 0x25, 0xdc);
n6_write_register(ViPipe, 0x28, 0x80);
n6_write_register(ViPipe, 0x2f, 0x00);
n6_write_register(ViPipe, 0x30, 0xe0);
n6_write_register(ViPipe, 0x31, 0x41);
n6_write_register(ViPipe, 0x32, 0xa2);
n6_write_register(ViPipe, 0x47, 0xee);
n6_write_register(ViPipe, 0x50, 0xc6);
n6_write_register(ViPipe, 0x57, 0x00);
n6_write_register(ViPipe, 0x58, 0x77);
n6_write_register(ViPipe, 0x5b, 0x41);
n6_write_register(ViPipe, 0x5c, 0x7C);
n6_write_register(ViPipe, 0x5f, 0x00);
n6_write_register(ViPipe, 0x62, 0x20);
n6_write_register(ViPipe, 0x7b, 0x11);
n6_write_register(ViPipe, 0x7c, 0x01);
n6_write_register(ViPipe, 0x7d, 0x80);
n6_write_register(ViPipe, 0x80, 0x00);
n6_write_register(ViPipe, 0x90, 0x01);
n6_write_register(ViPipe, 0xa9, 0x00);
n6_write_register(ViPipe, 0xb5, 0x40);
n6_write_register(ViPipe, 0xb8, 0x39);
n6_write_register(ViPipe, 0xb9, 0x72);
n6_write_register(ViPipe, 0xd1, 0x00);
n6_write_register(ViPipe, 0xd5, 0x80);
n6_write_register(ViPipe, 0xff, 0x09);
n6_write_register(ViPipe, 0x96 + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0x98 + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0x9e + ch * 0x20, 0x00);
n6_write_register(ViPipe, 0xff, _MAR_BANK_);
val_20x01 = n6_read_register(ViPipe, 0x01);
val_20x01 &= (~(0x03 << (ch * 2)));
n6_write_register(ViPipe, 0x01, val_20x01);
n6_write_register(ViPipe, 0x12 + ch*2, 0xc0);
n6_write_register(ViPipe, 0x13 + ch*2, 0x03);
}
unsigned char n6_read_vfc(VI_PIPE ViPipe, CVI_U8 ch)
{
CVI_U8 ch_vfc = 0xff;
n6_write_register(ViPipe, 0xff, 0x05 + ch);
ch_vfc = n6_read_register(ViPipe, 0xf0);
return ch_vfc;
}
void n6_device_auto_detect(VI_PIPE ViPipe)
{
CVI_U8 ch_vfc[16] = {0xff, 0xff, 0xff, 0xff, 0xff};
CVI_U8 val_13x70, val_13x71;
int check_cnt = 0;
CVI_U8 ch;
CVI_TRACE_SNS(CVI_DBG_INFO, "%s auto detection routine\n", __func__);
n6_write_register(ViPipe, 0xFF, 0x13);
n6_write_register(ViPipe, 0x30, 0x7f);
n6_write_register(ViPipe, 0x70, 0xf0);
n6_write_register(ViPipe, 0xFF, 0x00);
n6_write_register(ViPipe, 0x00, 0x18);
n6_write_register(ViPipe, 0x01, 0x18);
n6_write_register(ViPipe, 0x02, 0x18);
n6_write_register(ViPipe, 0x03, 0x18);
n6_write_register(ViPipe, 0x00, 0x10);
n6_write_register(ViPipe, 0x01, 0x10);
n6_write_register(ViPipe, 0x02, 0x10);
n6_write_register(ViPipe, 0x03, 0x10);
while ((check_cnt++) < 50) {
for (ch = 0; ch < 4; ch++) {
ch_vfc[ch] = n6_read_vfc(ViPipe, ch);
if (ch_vfc[ch] != 0xff)
syslog(LOG_DEBUG, "ch[%d] video vfc read value0 : %2x\n", ch, ch_vfc[ch]);
}
delay_ms(40);
}
for (ch = 0; ch < 4; ch++) {
n6_write_register(ViPipe, 0xFF, 0x13);
val_13x70 = n6_read_register(ViPipe, 0x70);
val_13x70 |= (0x01<<ch);
n6_write_register(ViPipe, 0x70, val_13x70);
val_13x71 = n6_read_register(ViPipe, 0x71);
val_13x71 |= (0x01<<ch);
n6_write_register(ViPipe, 0x71, val_13x71);
switch (ch_vfc[ch]) { // only check ch 0
case 0x00:
n6_set_chn_960h(ViPipe, ch, VFMT_NTSC);
break;
case 0x10:
n6_set_chn_960h(ViPipe, ch, VFMT_PAL);
break;
case 0x20:
n6_set_chn_720p(ViPipe, ch, VFMT_NTSC);
break;
case 0x21:
n6_set_chn_720p(ViPipe, ch, VFMT_PAL);
break;
case 0x30:
n6_set_chn_1080p(ViPipe, ch, VFMT_NTSC);
break;
case 0x31:
n6_set_chn_1080p(ViPipe, ch, VFMT_PAL);
break;
case 0xa0:
n6_set_chn_960p(ViPipe, ch, VFMT_NTSC);
break;
case 0xa1:
n6_set_chn_960p(ViPipe, ch, VFMT_PAL);
break;
default:
syslog(LOG_DEBUG, "ch_vfc not valid,set to default format\n");
n6_write_register(ViPipe, 0xFF, 0x13);
val_13x70 = n6_read_register(ViPipe, 0x70);
val_13x70 &= (~(0x01<<ch));
n6_write_register(ViPipe, 0x70, val_13x70);
n6_set_chn_1080p(ViPipe, ch, VFMT_NTSC);
break;
}
}
}
void n6_init(VI_PIPE ViPipe)
{
n6_i2c_init(ViPipe);
syslog(LOG_DEBUG, "Loading Nextchip N6 sensor\n");
// check sensor chip id
n6_write_register(ViPipe, 0xFF, 0x0);
if (n6_read_register(ViPipe, 0xf4) != 0xd3) {
syslog(LOG_DEBUG, "read N6 chip id fail\n");
return;
}
n6_common_setting(ViPipe);
if (adet == 0) { //manual mode
syslog(LOG_DEBUG, "manual mode 2\n");
#if 1
n6_set_chn_1080p(ViPipe, 0, VFMT_PAL);
n6_set_chn_1080p(ViPipe, 1, VFMT_PAL);
n6_set_chn_1080p(ViPipe, 2, VFMT_PAL);
n6_set_chn_1080p(ViPipe, 3, VFMT_PAL);
#else
n6_set_chn_720p(ViPipe, 0, VFMT_PAL);
n6_set_chn_720p(ViPipe, 2, VFMT_PAL);
#endif
} else {
syslog(LOG_DEBUG, "auto detect mode\n");
n6_device_auto_detect(ViPipe);
}
#if N6_TEST_PATTERN
// test_mode
n6_write_register(ViPipe, 0xFF, 0x5);
n6_write_register(ViPipe, 0x2c, 0x8);
n6_write_register(ViPipe, 0xFF, 0x6);
n6_write_register(ViPipe, 0x2c, 0x8);
n6_write_register(ViPipe, 0xFF, 0x7);
n6_write_register(ViPipe, 0x2c, 0x8);
n6_write_register(ViPipe, 0xFF, 0x8);
n6_write_register(ViPipe, 0x2c, 0x8);
n6_write_register(ViPipe, 0xFF, 0x0);
n6_write_register(ViPipe, 0x78, 0xaa);
n6_write_register(ViPipe, 0x79, 0xaa);
#endif
n6_write_register(ViPipe, 0xff, 0x23); //continuous clock
n6_write_register(ViPipe, 0xe1, 0x02);
n6_write_register(ViPipe, 0xff, 0x33); //continuous clock
n6_write_register(ViPipe, 0xe1, 0x02);
// wait for the sensor signal to stabilize
delay_ms(300);
}
void n6_exit(VI_PIPE ViPipe)
{
n6_i2c_exit(ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/ov_os04a10/Makefile Normal file
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@ -0,0 +1,36 @@
SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_os04a10.a
TARGET_SO = $(MW_LIB)/libsns_os04a10.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

1431
middleware/v2/component/isp/sensor/cv180x/ov_os04a10/os04a10_cmos.c Normal file
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File diff suppressed because it is too large Load Diff

117
middleware/v2/component/isp/sensor/cv180x/ov_os04a10/os04a10_cmos_ex.h Normal file
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#ifndef __OS04A10_CMOS_EX_H_
#define __OS04A10_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
enum os04a10_linear_regs_e {
LINEAR_HOLD_START = 0,
LINEAR_EXP_0,
LINEAR_EXP_1,
LINEAR_AGAIN_0,
LINEAR_AGAIN_1,
LINEAR_DGAIN_0,
LINEAR_DGAIN_1,
LINEAR_DGAIN_2,
LINEAR_VTS_0,
LINEAR_VTS_1,
LINEAR_HOLD_END,
LINEAR_LAUNCH_0,
LINEAR_LAUNCH_1,
LINEAR_REGS_NUM
};
enum os04a10_wdr2_regs_e {
WDR2_HOLD_START = 0,
WDR2_EXP1_0,
WDR2_EXP1_1,
WDR2_EXP2_0,
WDR2_EXP2_1,
WDR2_AGAIN1_0,
WDR2_AGAIN1_1,
WDR2_AGAIN2_0,
WDR2_AGAIN2_1,
WDR2_DGAIN1_0,
WDR2_DGAIN1_1,
WDR2_DGAIN1_2,
WDR2_DGAIN2_0,
WDR2_DGAIN2_1,
WDR2_DGAIN2_2,
WDR2_VTS_0,
WDR2_VTS_1,
WDR2_HOLD_END,
WDR2_LAUNCH_0,
WDR2_LAUNCH_1,
WDR2_REGS_NUM
};
typedef enum _OS04A10_MODE_E {
OS04A10_MODE_1440P30_12BIT = 0,
OS04A10_MODE_LINEAR_NUM,
OS04A10_MODE_1440P30_WDR = OS04A10_MODE_LINEAR_NUM,
OS04A10_MODE_NUM
} OS04A10_MODE_E;
typedef struct _OS04A10_STATE_S {
CVI_U32 u32Sexp_MAX;
} OS04A10_STATE_S;
typedef struct _OS04A10_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
char name[64];
CVI_U32 u32L2S_offset;
CVI_U32 u32IspResTime;
CVI_U32 u32VStart;
CVI_U32 u32VEnd;
} OS04A10_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastOs04a10[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunOs04a10_BusInfo[];
extern CVI_U16 g_au16Os04a10_GainMode[];
extern CVI_U16 g_au16Os04a10_UseHwSync[VI_MAX_PIPE_NUM];
extern CVI_U8 os04a10_i2c_addr;
extern const CVI_U32 os04a10_addr_byte;
extern const CVI_U32 os04a10_data_byte;
extern void os04a10_init(VI_PIPE ViPipe);
extern void os04a10_exit(VI_PIPE ViPipe);
extern void os04a10_standby(VI_PIPE ViPipe);
extern void os04a10_restart(VI_PIPE ViPipe);
extern void os04a10_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int os04a10_write_register(VI_PIPE ViPipe, int addr, int data);
extern int os04a10_read_register(VI_PIPE ViPipe, int addr);
extern int os04a10_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OS04A10_CMOS_EX_H_ */

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#ifndef __OS04A10_CMOS_PARAM_H_
#define __OS04A10_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "os04a10_cmos_ex.h"
static const OS04A10_MODE_S g_astOs04a10_mode[OS04A10_MODE_NUM] = {
[OS04A10_MODE_1440P30_12BIT] = {
.name = "1440p30_12bit",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2688,
.u32Height = 1520,
},
.stWndRect = {
.s32X = 64,
.s32Y = 40,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2688,
.u32Height = 1520,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.74, /* 0x658 * 30 / 0xFFFF */
.u32HtsDef = 2688,
.u32VtsDef = 1624,
.stExp[0] = {
.u16Min = 2,
.u16Max = 1624 - 8,
.u16Def = 500,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16373,
.u32Def = 1024,
.u32Step = 1,
},
},
[OS04A10_MODE_1440P30_WDR] = {
.name = "1440p30wdr",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2688,
.u32Height = 1520,
},
.stWndRect = {
.s32X = 64,
.s32Y = 40,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2688,
.u32Height = 1520,
},
},
.astImg[1] = {
.stSnsSize = {
.u32Width = 2688,
.u32Height = 1520,
},
.stWndRect = {
.s32X = 64,
.s32Y = 40,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2688,
.u32Height = 1520,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.74, /* 1624 * 30 / 0xFFFF */
.u32HtsDef = 2972,
.u32VtsDef = 1624,
.u32L2S_offset = 40,
.u32IspResTime = 49, /* ceil((u32Vts * f32MaxFps) / 1000); about 1ms*/
.u32VStart = 0,
.u32VEnd = 0x5ff,
.stExp[0] = {
.u16Min = 8,
.u16Max = 88,
.u16Def = 88,
.u16Step = 1,
},
.stExp[1] = {
.u16Min = 8,
.u16Max = 0x486 - 4 - 88,
.u16Def = 500,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stAgain[1] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16373,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[1] = {
.u32Min = 1024,
.u32Max = 16373,
.u32Def = 1024,
.u32Step = 1,
},
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {128, 128, 128, 128, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1057, 1057, 1057, 1057
#endif
},
.stAuto = {
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
#endif
},
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio10Bit = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {256, 256, 256, 256, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1092, 1092, 1092, 1092
#endif
},
.stAuto = {
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
#endif
},
},
};
struct combo_dev_attr_s os04a10_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_500M,
.mipi_attr = {
.raw_data_type = RAW_DATA_12BIT,
.lane_id = {0, 1, 2, 3, 4},
.wdr_mode = CVI_MIPI_WDR_MODE_VC,
.dphy = {
.enable = 1,
.hs_settle = 8,
},
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_25M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OS04A10_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "os04a10_cmos_ex.h"
static void os04a10_wdr_1520p30_2to1_init(VI_PIPE ViPipe);
static void os04a10_linear_1520p30_12BIT_init(VI_PIPE ViPipe);
CVI_U8 os04a10_i2c_addr = 0x36; /* I2C Address of OS04A10 */
const CVI_U32 os04a10_addr_byte = 2;
const CVI_U32 os04a10_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
ISP_SNS_MIRRORFLIP_TYPE_E g_aeOs04a10_MirrorFip_Initial[VI_MAX_PIPE_NUM] = {
ISP_SNS_MIRROR, ISP_SNS_MIRROR, ISP_SNS_MIRROR, ISP_SNS_MIRROR};
int os04a10_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunOs04a10_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, os04a10_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int os04a10_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int os04a10_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (os04a10_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, os04a10_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return 0;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, os04a10_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return 0;
}
// pack read back data
data = 0;
if (os04a10_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int os04a10_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (os04a10_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (os04a10_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, os04a10_addr_byte + os04a10_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
/*
*static void delay_ms(int ms)
*{
* usleep(ms * 1000);
*}
*/
void os04a10_standby(VI_PIPE ViPipe)
{
os04a10_write_register(ViPipe, 0x0100, 0x00); /* STANDBY */
}
void os04a10_restart(VI_PIPE ViPipe)
{
os04a10_write_register(ViPipe, 0x0100, 0x01); /* resume */
}
void os04a10_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
CVI_U32 start = 1;
CVI_U32 end = g_pastOs04a10[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum - 3;
for (i = start; i < end; i++) {
os04a10_write_register(ViPipe,
g_pastOs04a10[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastOs04a10[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
CVI_TRACE_SNS(CVI_DBG_INFO, "i2c_addr:%#x, i2c_data:%#x\n",
g_pastOs04a10[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastOs04a10[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
ISP_SNS_MIRRORFLIP_TYPE_E aeSnsMirrorFlipMap[ISP_SNS_BUTT][ISP_SNS_BUTT] = {
{ISP_SNS_NORMAL, ISP_SNS_MIRROR, ISP_SNS_FLIP, ISP_SNS_MIRROR_FLIP},
{ISP_SNS_MIRROR, ISP_SNS_NORMAL, ISP_SNS_MIRROR_FLIP, ISP_SNS_FLIP},
{ISP_SNS_FLIP, ISP_SNS_MIRROR_FLIP, ISP_SNS_NORMAL, ISP_SNS_MIRROR},
{ISP_SNS_MIRROR_FLIP, ISP_SNS_FLIP, ISP_SNS_MIRROR, ISP_SNS_NORMAL}
};
#define OS04A10_ORIEN_ADDR (0x3820)
void os04a10_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 val = 0;
CVI_U32 i = 0;
for (i = 0; i < ISP_SNS_BUTT; i++) {
if (g_aeOs04a10_MirrorFip_Initial[ViPipe] == aeSnsMirrorFlipMap[i][0]) {
eSnsMirrorFlip = aeSnsMirrorFlipMap[i][eSnsMirrorFlip];
break;
}
}
val = os04a10_read_register(ViPipe, OS04A10_ORIEN_ADDR);
val &= ~(0x3 << 1);
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
val |= 0x1<<1;
break;
case ISP_SNS_FLIP:
val |= 0x1<<2;
break;
case ISP_SNS_MIRROR_FLIP:
val |= 0x1<<1;
val |= 0x1<<2;
break;
default:
return;
}
os04a10_standby(ViPipe);
os04a10_write_register(ViPipe, OS04A10_ORIEN_ADDR, val);
usleep(1000*100);
os04a10_restart(ViPipe);
}
#define OS04A10_CHIP_ID_ADDR_H 0x300A
#define OS04A10_CHIP_ID_ADDR_M 0x300B
#define OS04A10_CHIP_ID_ADDR_L 0x300C
#define OS04A10_CHIP_ID 0x530441
int os04a10_probe(VI_PIPE ViPipe)
{
int nVal, nVal2, nVal3;
usleep(500);
if (os04a10_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = os04a10_read_register(ViPipe, OS04A10_CHIP_ID_ADDR_H);
nVal2 = os04a10_read_register(ViPipe, OS04A10_CHIP_ID_ADDR_M);
nVal3 = os04a10_read_register(ViPipe, OS04A10_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0 || nVal3 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 16) | ((nVal2 & 0xFF) << 8) | (nVal3 & 0xFF)) != OS04A10_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void os04a10_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode;
CVI_U8 u8ImgMode;
enWDRMode = g_pastOs04a10[ViPipe]->enWDRMode;
u8ImgMode = g_pastOs04a10[ViPipe]->u8ImgMode;
os04a10_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
if (u8ImgMode == OS04A10_MODE_1440P30_WDR)
os04a10_wdr_1520p30_2to1_init(ViPipe);
} else {
if (u8ImgMode == OS04A10_MODE_1440P30_12BIT)
os04a10_linear_1520p30_12BIT_init(ViPipe);
}
g_pastOs04a10[ViPipe]->bInit = CVI_TRUE;
}
void os04a10_exit(VI_PIPE ViPipe)
{
os04a10_i2c_exit(ViPipe);
}
static void os04a10_linear_1520p30_12BIT_init(VI_PIPE ViPipe)
{
os04a10_write_register(ViPipe, 0x0103, 0x01);
os04a10_write_register(ViPipe, 0x0109, 0x01);
os04a10_write_register(ViPipe, 0x0104, 0x02);
os04a10_write_register(ViPipe, 0x0102, 0x00);
os04a10_write_register(ViPipe, 0x0305, 0x40);
os04a10_write_register(ViPipe, 0x0306, 0x00);
os04a10_write_register(ViPipe, 0x0307, 0x00);
os04a10_write_register(ViPipe, 0x0308, 0x05);
os04a10_write_register(ViPipe, 0x030a, 0x01);
os04a10_write_register(ViPipe, 0x0317, 0x0a);
os04a10_write_register(ViPipe, 0x0322, 0x01);
os04a10_write_register(ViPipe, 0x0323, 0x02);
os04a10_write_register(ViPipe, 0x0324, 0x00);
os04a10_write_register(ViPipe, 0x0325, 0x8b);
os04a10_write_register(ViPipe, 0x0327, 0x05);
os04a10_write_register(ViPipe, 0x0329, 0x02);
os04a10_write_register(ViPipe, 0x032c, 0x02);
os04a10_write_register(ViPipe, 0x032d, 0x02);
os04a10_write_register(ViPipe, 0x032e, 0x02);
os04a10_write_register(ViPipe, 0x300f, 0x11);
os04a10_write_register(ViPipe, 0x3012, 0x41);
os04a10_write_register(ViPipe, 0x3026, 0x10);
os04a10_write_register(ViPipe, 0x3027, 0x08);
os04a10_write_register(ViPipe, 0x302d, 0x24);
os04a10_write_register(ViPipe, 0x3104, 0x01);
os04a10_write_register(ViPipe, 0x3106, 0x11);
os04a10_write_register(ViPipe, 0x3400, 0x00);
os04a10_write_register(ViPipe, 0x3408, 0x05);
os04a10_write_register(ViPipe, 0x340c, 0x0c);
os04a10_write_register(ViPipe, 0x340d, 0xb0);
os04a10_write_register(ViPipe, 0x3425, 0x51);
os04a10_write_register(ViPipe, 0x3426, 0x10);
os04a10_write_register(ViPipe, 0x3427, 0x14);
os04a10_write_register(ViPipe, 0x3428, 0x10);
os04a10_write_register(ViPipe, 0x3429, 0x10);
os04a10_write_register(ViPipe, 0x342a, 0x10);
os04a10_write_register(ViPipe, 0x342b, 0x04);
os04a10_write_register(ViPipe, 0x3501, 0x02);
os04a10_write_register(ViPipe, 0x3504, 0x08);
os04a10_write_register(ViPipe, 0x3508, 0x01);
os04a10_write_register(ViPipe, 0x3509, 0x00);
os04a10_write_register(ViPipe, 0x350a, 0x01);
os04a10_write_register(ViPipe, 0x3544, 0x08);
os04a10_write_register(ViPipe, 0x3548, 0x01);
os04a10_write_register(ViPipe, 0x3549, 0x00);
os04a10_write_register(ViPipe, 0x3584, 0x08);
os04a10_write_register(ViPipe, 0x3588, 0x01);
os04a10_write_register(ViPipe, 0x3589, 0x00);
os04a10_write_register(ViPipe, 0x3601, 0x70);
os04a10_write_register(ViPipe, 0x3604, 0xe3);
os04a10_write_register(ViPipe, 0x3605, 0xff);
os04a10_write_register(ViPipe, 0x3606, 0x01);
os04a10_write_register(ViPipe, 0x3608, 0xa8);
os04a10_write_register(ViPipe, 0x360a, 0xd0);
os04a10_write_register(ViPipe, 0x360b, 0x08);
os04a10_write_register(ViPipe, 0x360e, 0xc8);
os04a10_write_register(ViPipe, 0x360f, 0x66);
os04a10_write_register(ViPipe, 0x3610, 0x89);
os04a10_write_register(ViPipe, 0x3611, 0x8a);
os04a10_write_register(ViPipe, 0x3612, 0x4e);
os04a10_write_register(ViPipe, 0x3613, 0xbd);
os04a10_write_register(ViPipe, 0x3614, 0x9b);
os04a10_write_register(ViPipe, 0x362a, 0x0e);
os04a10_write_register(ViPipe, 0x362b, 0x0e);
os04a10_write_register(ViPipe, 0x362c, 0x0e);
os04a10_write_register(ViPipe, 0x362d, 0x09);
os04a10_write_register(ViPipe, 0x362e, 0x1a);
os04a10_write_register(ViPipe, 0x362f, 0x34);
os04a10_write_register(ViPipe, 0x3630, 0x67);
os04a10_write_register(ViPipe, 0x3631, 0x7f);
os04a10_write_register(ViPipe, 0x3638, 0x00);
os04a10_write_register(ViPipe, 0x3643, 0x00);
os04a10_write_register(ViPipe, 0x3644, 0x00);
os04a10_write_register(ViPipe, 0x3645, 0x00);
os04a10_write_register(ViPipe, 0x3646, 0x00);
os04a10_write_register(ViPipe, 0x3647, 0x00);
os04a10_write_register(ViPipe, 0x3648, 0x00);
os04a10_write_register(ViPipe, 0x3649, 0x00);
os04a10_write_register(ViPipe, 0x364a, 0x04);
os04a10_write_register(ViPipe, 0x364c, 0x0e);
os04a10_write_register(ViPipe, 0x364d, 0x0e);
os04a10_write_register(ViPipe, 0x364e, 0x0e);
os04a10_write_register(ViPipe, 0x364f, 0x0e);
os04a10_write_register(ViPipe, 0x3650, 0xff);
os04a10_write_register(ViPipe, 0x3651, 0xff);
os04a10_write_register(ViPipe, 0x365a, 0x00);
os04a10_write_register(ViPipe, 0x365b, 0x00);
os04a10_write_register(ViPipe, 0x365c, 0x00);
os04a10_write_register(ViPipe, 0x365d, 0x00);
os04a10_write_register(ViPipe, 0x3661, 0x07);
os04a10_write_register(ViPipe, 0x3662, 0x00);
os04a10_write_register(ViPipe, 0x3663, 0x20);
os04a10_write_register(ViPipe, 0x3665, 0x12);
os04a10_write_register(ViPipe, 0x3667, 0xd4);
os04a10_write_register(ViPipe, 0x3668, 0x80);
os04a10_write_register(ViPipe, 0x366c, 0x00);
os04a10_write_register(ViPipe, 0x366d, 0x00);
os04a10_write_register(ViPipe, 0x366e, 0x00);
os04a10_write_register(ViPipe, 0x366f, 0x00);
os04a10_write_register(ViPipe, 0x3671, 0x08);
os04a10_write_register(ViPipe, 0x3673, 0x2a);
os04a10_write_register(ViPipe, 0x3681, 0x80);
os04a10_write_register(ViPipe, 0x3700, 0x2d);
os04a10_write_register(ViPipe, 0x3701, 0x22);
os04a10_write_register(ViPipe, 0x3702, 0x25);
os04a10_write_register(ViPipe, 0x3703, 0x28);
os04a10_write_register(ViPipe, 0x3705, 0x00);
os04a10_write_register(ViPipe, 0x3706, 0xf0);
os04a10_write_register(ViPipe, 0x3707, 0x0a);
os04a10_write_register(ViPipe, 0x3708, 0x36);
os04a10_write_register(ViPipe, 0x3709, 0x57);
os04a10_write_register(ViPipe, 0x370a, 0x03);
os04a10_write_register(ViPipe, 0x370b, 0x15);
os04a10_write_register(ViPipe, 0x3714, 0x01);
os04a10_write_register(ViPipe, 0x3719, 0x24);
os04a10_write_register(ViPipe, 0x371b, 0x1f);
os04a10_write_register(ViPipe, 0x371c, 0x00);
os04a10_write_register(ViPipe, 0x371d, 0x08);
os04a10_write_register(ViPipe, 0x373f, 0x63);
os04a10_write_register(ViPipe, 0x3740, 0x63);
os04a10_write_register(ViPipe, 0x3741, 0x63);
os04a10_write_register(ViPipe, 0x3742, 0x63);
os04a10_write_register(ViPipe, 0x3743, 0x01);
os04a10_write_register(ViPipe, 0x3756, 0xe7);
os04a10_write_register(ViPipe, 0x3757, 0xe7);
os04a10_write_register(ViPipe, 0x3762, 0x1c);
os04a10_write_register(ViPipe, 0x376c, 0x10);
os04a10_write_register(ViPipe, 0x3776, 0x05);
os04a10_write_register(ViPipe, 0x3777, 0x22);
os04a10_write_register(ViPipe, 0x3779, 0x60);
os04a10_write_register(ViPipe, 0x377c, 0x48);
os04a10_write_register(ViPipe, 0x3784, 0x06);
os04a10_write_register(ViPipe, 0x3785, 0x0a);
os04a10_write_register(ViPipe, 0x3790, 0x10);
os04a10_write_register(ViPipe, 0x3793, 0x04);
os04a10_write_register(ViPipe, 0x3794, 0x07);
os04a10_write_register(ViPipe, 0x3796, 0x00);
os04a10_write_register(ViPipe, 0x3797, 0x02);
os04a10_write_register(ViPipe, 0x379c, 0x4d);
os04a10_write_register(ViPipe, 0x37a1, 0x80);
os04a10_write_register(ViPipe, 0x37bb, 0x88);
os04a10_write_register(ViPipe, 0x37be, 0x48);
os04a10_write_register(ViPipe, 0x37bf, 0x01);
os04a10_write_register(ViPipe, 0x37c0, 0x01);
os04a10_write_register(ViPipe, 0x37c4, 0x72);
os04a10_write_register(ViPipe, 0x37c5, 0x72);
os04a10_write_register(ViPipe, 0x37c6, 0x72);
os04a10_write_register(ViPipe, 0x37ca, 0x21);
os04a10_write_register(ViPipe, 0x37cc, 0x15);
os04a10_write_register(ViPipe, 0x37cd, 0x90);
os04a10_write_register(ViPipe, 0x37cf, 0x02);
os04a10_write_register(ViPipe, 0x37d0, 0x00);
os04a10_write_register(ViPipe, 0x37d1, 0xf0);
os04a10_write_register(ViPipe, 0x37d2, 0x03);
os04a10_write_register(ViPipe, 0x37d3, 0x15);
os04a10_write_register(ViPipe, 0x37d4, 0x01);
os04a10_write_register(ViPipe, 0x37d5, 0x00);
os04a10_write_register(ViPipe, 0x37d6, 0x03);
os04a10_write_register(ViPipe, 0x37d7, 0x15);
os04a10_write_register(ViPipe, 0x37d8, 0x01);
os04a10_write_register(ViPipe, 0x37dc, 0x00);
os04a10_write_register(ViPipe, 0x37dd, 0x00);
os04a10_write_register(ViPipe, 0x37da, 0x00);
os04a10_write_register(ViPipe, 0x37db, 0x00);
os04a10_write_register(ViPipe, 0x3800, 0x00);
os04a10_write_register(ViPipe, 0x3801, 0x00);
os04a10_write_register(ViPipe, 0x3802, 0x00);
os04a10_write_register(ViPipe, 0x3803, 0x00);
os04a10_write_register(ViPipe, 0x3804, 0x0a);
os04a10_write_register(ViPipe, 0x3805, 0x8f);
os04a10_write_register(ViPipe, 0x3806, 0x05);
os04a10_write_register(ViPipe, 0x3807, 0xff);
os04a10_write_register(ViPipe, 0x3808, 0x0a);
os04a10_write_register(ViPipe, 0x3809, 0x80);
os04a10_write_register(ViPipe, 0x380a, 0x05);
os04a10_write_register(ViPipe, 0x380b, 0xf0);
os04a10_write_register(ViPipe, 0x380c, 0x05);
os04a10_write_register(ViPipe, 0x380d, 0xcc);
os04a10_write_register(ViPipe, 0x380e, 0x06);
os04a10_write_register(ViPipe, 0x380f, 0x58);
os04a10_write_register(ViPipe, 0x3811, 0x08);
os04a10_write_register(ViPipe, 0x3813, 0x08);
os04a10_write_register(ViPipe, 0x3814, 0x01);
os04a10_write_register(ViPipe, 0x3815, 0x01);
os04a10_write_register(ViPipe, 0x3816, 0x01);
os04a10_write_register(ViPipe, 0x3817, 0x01);
os04a10_write_register(ViPipe, 0x381c, 0x00);
os04a10_write_register(ViPipe, 0x3820, 0x02);
os04a10_write_register(ViPipe, 0x3821, 0x00);
os04a10_write_register(ViPipe, 0x3822, 0x14);
os04a10_write_register(ViPipe, 0x3823, 0x18);
os04a10_write_register(ViPipe, 0x3826, 0x00);
os04a10_write_register(ViPipe, 0x3827, 0x00);
os04a10_write_register(ViPipe, 0x3833, 0x40);
os04a10_write_register(ViPipe, 0x384c, 0x05);
os04a10_write_register(ViPipe, 0x384d, 0xc4);
os04a10_write_register(ViPipe, 0x3858, 0x3c);
os04a10_write_register(ViPipe, 0x3865, 0x02);
os04a10_write_register(ViPipe, 0x3866, 0x00);
os04a10_write_register(ViPipe, 0x3867, 0x00);
os04a10_write_register(ViPipe, 0x3868, 0x02);
os04a10_write_register(ViPipe, 0x3900, 0x13);
os04a10_write_register(ViPipe, 0x3940, 0x13);
os04a10_write_register(ViPipe, 0x3980, 0x13);
os04a10_write_register(ViPipe, 0x3c01, 0x11);
os04a10_write_register(ViPipe, 0x3c05, 0x00);
os04a10_write_register(ViPipe, 0x3c0f, 0x1c);
os04a10_write_register(ViPipe, 0x3c12, 0x0d);
os04a10_write_register(ViPipe, 0x3c19, 0x00);
os04a10_write_register(ViPipe, 0x3c21, 0x00);
os04a10_write_register(ViPipe, 0x3c3a, 0x10);
os04a10_write_register(ViPipe, 0x3c3b, 0x18);
os04a10_write_register(ViPipe, 0x3c3d, 0xc6);
os04a10_write_register(ViPipe, 0x3c55, 0x08);
os04a10_write_register(ViPipe, 0x3c5a, 0xe5);
os04a10_write_register(ViPipe, 0x3c5d, 0xcf);
os04a10_write_register(ViPipe, 0x3c5e, 0xcf);
os04a10_write_register(ViPipe, 0x3d8c, 0x70);
os04a10_write_register(ViPipe, 0x3d8d, 0x10);
os04a10_write_register(ViPipe, 0x4000, 0xf9);
os04a10_write_register(ViPipe, 0x4001, 0x2f);
os04a10_write_register(ViPipe, 0x4004, 0x00);
os04a10_write_register(ViPipe, 0x4005, 0x80);
os04a10_write_register(ViPipe, 0x4008, 0x02);
os04a10_write_register(ViPipe, 0x4009, 0x11);
os04a10_write_register(ViPipe, 0x400a, 0x03);
os04a10_write_register(ViPipe, 0x400b, 0x27);
os04a10_write_register(ViPipe, 0x400e, 0x40);
os04a10_write_register(ViPipe, 0x402e, 0x00);
os04a10_write_register(ViPipe, 0x402f, 0x80);
os04a10_write_register(ViPipe, 0x4030, 0x00);
os04a10_write_register(ViPipe, 0x4031, 0x80);
os04a10_write_register(ViPipe, 0x4032, 0x9f);
os04a10_write_register(ViPipe, 0x4033, 0x80);
os04a10_write_register(ViPipe, 0x4050, 0x00);
os04a10_write_register(ViPipe, 0x4051, 0x07);
os04a10_write_register(ViPipe, 0x4011, 0xbb);
os04a10_write_register(ViPipe, 0x410f, 0x01);
os04a10_write_register(ViPipe, 0x4288, 0xcf);
os04a10_write_register(ViPipe, 0x4289, 0x00);
os04a10_write_register(ViPipe, 0x428a, 0x46);
os04a10_write_register(ViPipe, 0x430b, 0xff);
os04a10_write_register(ViPipe, 0x430c, 0xff);
os04a10_write_register(ViPipe, 0x430d, 0x00);
os04a10_write_register(ViPipe, 0x430e, 0x00);
os04a10_write_register(ViPipe, 0x4314, 0x04);
os04a10_write_register(ViPipe, 0x4500, 0x18);
os04a10_write_register(ViPipe, 0x4501, 0x18);
os04a10_write_register(ViPipe, 0x4503, 0x10);
os04a10_write_register(ViPipe, 0x4504, 0x00);
os04a10_write_register(ViPipe, 0x4506, 0x32);
os04a10_write_register(ViPipe, 0x4507, 0x02);
os04a10_write_register(ViPipe, 0x4601, 0x30);
os04a10_write_register(ViPipe, 0x4603, 0x00);
os04a10_write_register(ViPipe, 0x460a, 0x50);
os04a10_write_register(ViPipe, 0x460c, 0x60);
os04a10_write_register(ViPipe, 0x4640, 0x62);
os04a10_write_register(ViPipe, 0x4646, 0xaa);
os04a10_write_register(ViPipe, 0x4647, 0x55);
os04a10_write_register(ViPipe, 0x4648, 0x99);
os04a10_write_register(ViPipe, 0x4649, 0x66);
os04a10_write_register(ViPipe, 0x464d, 0x00);
os04a10_write_register(ViPipe, 0x4654, 0x11);
os04a10_write_register(ViPipe, 0x4655, 0x22);
os04a10_write_register(ViPipe, 0x4800, 0x44);
os04a10_write_register(ViPipe, 0x480e, 0x00);
os04a10_write_register(ViPipe, 0x4810, 0xff);
os04a10_write_register(ViPipe, 0x4811, 0xff);
os04a10_write_register(ViPipe, 0x4813, 0x00);
os04a10_write_register(ViPipe, 0x481f, 0x30);
os04a10_write_register(ViPipe, 0x4837, 0x14);
os04a10_write_register(ViPipe, 0x484b, 0x27);
os04a10_write_register(ViPipe, 0x4d00, 0x4d);
os04a10_write_register(ViPipe, 0x4d01, 0x9d);
os04a10_write_register(ViPipe, 0x4d02, 0xb9);
os04a10_write_register(ViPipe, 0x4d03, 0x2e);
os04a10_write_register(ViPipe, 0x4d04, 0x4a);
os04a10_write_register(ViPipe, 0x4d05, 0x3d);
os04a10_write_register(ViPipe, 0x4d09, 0x4f);
os04a10_write_register(ViPipe, 0x5000, 0x7f);
os04a10_write_register(ViPipe, 0x5001, 0x0d);
os04a10_write_register(ViPipe, 0x5080, 0x00);
os04a10_write_register(ViPipe, 0x50c0, 0x00);
os04a10_write_register(ViPipe, 0x5100, 0x00);
os04a10_write_register(ViPipe, 0x5200, 0x00);
os04a10_write_register(ViPipe, 0x5201, 0x00);
os04a10_write_register(ViPipe, 0x5202, 0x03);
os04a10_write_register(ViPipe, 0x5203, 0xff);
os04a10_write_register(ViPipe, 0x5780, 0x53);
os04a10_write_register(ViPipe, 0x5782, 0x60);
os04a10_write_register(ViPipe, 0x5783, 0xf0);
os04a10_write_register(ViPipe, 0x5786, 0x01);
os04a10_write_register(ViPipe, 0x5788, 0x60);
os04a10_write_register(ViPipe, 0x5789, 0xf0);
os04a10_write_register(ViPipe, 0x5792, 0x11);
os04a10_write_register(ViPipe, 0x5793, 0x33);
os04a10_write_register(ViPipe, 0x5857, 0xff);
os04a10_write_register(ViPipe, 0x5858, 0xff);
os04a10_write_register(ViPipe, 0x5859, 0xff);
os04a10_write_register(ViPipe, 0x58d7, 0xff);
os04a10_write_register(ViPipe, 0x58d8, 0xff);
os04a10_write_register(ViPipe, 0x58d9, 0xff);
os04a10_default_reg_init(ViPipe);
os04a10_write_register(ViPipe, 0x0100, 0x01);
printf("ViPipe:%d,===OS04A10 1520P 30fps 12bit LINE Init OK!===\n", ViPipe);
}
static void os04a10_wdr_1520p30_2to1_init(VI_PIPE ViPipe)
{
os04a10_write_register(ViPipe, 0x0103, 0x01);
os04a10_write_register(ViPipe, 0x0109, 0x01);
os04a10_write_register(ViPipe, 0x0104, 0x02);
os04a10_write_register(ViPipe, 0x0102, 0x00);
os04a10_write_register(ViPipe, 0x0305, 0x3c);
os04a10_write_register(ViPipe, 0x0306, 0x00);
os04a10_write_register(ViPipe, 0x0307, 0x00);
os04a10_write_register(ViPipe, 0x0308, 0x04);
os04a10_write_register(ViPipe, 0x030a, 0x01);
os04a10_write_register(ViPipe, 0x0317, 0x09);
os04a10_write_register(ViPipe, 0x0322, 0x01);
os04a10_write_register(ViPipe, 0x0323, 0x02);
os04a10_write_register(ViPipe, 0x0324, 0x00);
os04a10_write_register(ViPipe, 0x0325, 0x90);
os04a10_write_register(ViPipe, 0x0327, 0x05);
os04a10_write_register(ViPipe, 0x0329, 0x02);
os04a10_write_register(ViPipe, 0x032c, 0x02);
os04a10_write_register(ViPipe, 0x032d, 0x02);
os04a10_write_register(ViPipe, 0x032e, 0x02);
os04a10_write_register(ViPipe, 0x300f, 0x11);
os04a10_write_register(ViPipe, 0x3012, 0x41);
os04a10_write_register(ViPipe, 0x3026, 0x10);
os04a10_write_register(ViPipe, 0x3027, 0x08);
os04a10_write_register(ViPipe, 0x302d, 0x24);
os04a10_write_register(ViPipe, 0x3104, 0x01);
os04a10_write_register(ViPipe, 0x3106, 0x11);
os04a10_write_register(ViPipe, 0x3400, 0x00);
os04a10_write_register(ViPipe, 0x3408, 0x05);
os04a10_write_register(ViPipe, 0x340c, 0x0c);
os04a10_write_register(ViPipe, 0x340d, 0xb0);
os04a10_write_register(ViPipe, 0x3425, 0x51);
os04a10_write_register(ViPipe, 0x3426, 0x10);
os04a10_write_register(ViPipe, 0x3427, 0x14);
os04a10_write_register(ViPipe, 0x3428, 0x10);
os04a10_write_register(ViPipe, 0x3429, 0x10);
os04a10_write_register(ViPipe, 0x342a, 0x10);
os04a10_write_register(ViPipe, 0x342b, 0x04);
os04a10_write_register(ViPipe, 0x3501, 0x02);
os04a10_write_register(ViPipe, 0x3504, 0x08);
os04a10_write_register(ViPipe, 0x3508, 0x01);
os04a10_write_register(ViPipe, 0x3509, 0x00);
os04a10_write_register(ViPipe, 0x350a, 0x01);
os04a10_write_register(ViPipe, 0x3544, 0x08);
os04a10_write_register(ViPipe, 0x3548, 0x01);
os04a10_write_register(ViPipe, 0x3549, 0x00);
os04a10_write_register(ViPipe, 0x3584, 0x08);
os04a10_write_register(ViPipe, 0x3588, 0x01);
os04a10_write_register(ViPipe, 0x3589, 0x00);
os04a10_write_register(ViPipe, 0x3601, 0x70);
os04a10_write_register(ViPipe, 0x3604, 0xe3);
os04a10_write_register(ViPipe, 0x3605, 0x7f);
os04a10_write_register(ViPipe, 0x3606, 0x80);
os04a10_write_register(ViPipe, 0x3608, 0xa8);
os04a10_write_register(ViPipe, 0x360a, 0xd0);
os04a10_write_register(ViPipe, 0x360b, 0x08);
os04a10_write_register(ViPipe, 0x360e, 0xc8);
os04a10_write_register(ViPipe, 0x360f, 0x66);
os04a10_write_register(ViPipe, 0x3610, 0x89);
os04a10_write_register(ViPipe, 0x3611, 0x8a);
os04a10_write_register(ViPipe, 0x3612, 0x4e);
os04a10_write_register(ViPipe, 0x3613, 0xbd);
os04a10_write_register(ViPipe, 0x3614, 0x9b);
os04a10_write_register(ViPipe, 0x362a, 0x0e);
os04a10_write_register(ViPipe, 0x362b, 0x0e);
os04a10_write_register(ViPipe, 0x362c, 0x0e);
os04a10_write_register(ViPipe, 0x362d, 0x0e);
os04a10_write_register(ViPipe, 0x362e, 0x1a);
os04a10_write_register(ViPipe, 0x362f, 0x34);
os04a10_write_register(ViPipe, 0x3630, 0x67);
os04a10_write_register(ViPipe, 0x3631, 0x7f);
os04a10_write_register(ViPipe, 0x3638, 0x00);
os04a10_write_register(ViPipe, 0x3643, 0x00);
os04a10_write_register(ViPipe, 0x3644, 0x00);
os04a10_write_register(ViPipe, 0x3645, 0x00);
os04a10_write_register(ViPipe, 0x3646, 0x00);
os04a10_write_register(ViPipe, 0x3647, 0x00);
os04a10_write_register(ViPipe, 0x3648, 0x00);
os04a10_write_register(ViPipe, 0x3649, 0x00);
os04a10_write_register(ViPipe, 0x364a, 0x04);
os04a10_write_register(ViPipe, 0x364c, 0x0e);
os04a10_write_register(ViPipe, 0x364d, 0x0e);
os04a10_write_register(ViPipe, 0x364e, 0x0e);
os04a10_write_register(ViPipe, 0x364f, 0x0e);
os04a10_write_register(ViPipe, 0x3650, 0xff);
os04a10_write_register(ViPipe, 0x3651, 0xff);
os04a10_write_register(ViPipe, 0x365a, 0x00);
os04a10_write_register(ViPipe, 0x365b, 0x00);
os04a10_write_register(ViPipe, 0x365c, 0x00);
os04a10_write_register(ViPipe, 0x365d, 0x00);
os04a10_write_register(ViPipe, 0x3661, 0x07);
os04a10_write_register(ViPipe, 0x3662, 0x02);
os04a10_write_register(ViPipe, 0x3663, 0x20);
os04a10_write_register(ViPipe, 0x3665, 0x12);
os04a10_write_register(ViPipe, 0x3667, 0x54);
os04a10_write_register(ViPipe, 0x3668, 0x80);
os04a10_write_register(ViPipe, 0x366c, 0x00);
os04a10_write_register(ViPipe, 0x366d, 0x00);
os04a10_write_register(ViPipe, 0x366e, 0x00);
os04a10_write_register(ViPipe, 0x366f, 0x00);
os04a10_write_register(ViPipe, 0x3671, 0x09);
os04a10_write_register(ViPipe, 0x3673, 0x2a);
os04a10_write_register(ViPipe, 0x3681, 0x80);
os04a10_write_register(ViPipe, 0x3700, 0x2d);
os04a10_write_register(ViPipe, 0x3701, 0x22);
os04a10_write_register(ViPipe, 0x3702, 0x25);
os04a10_write_register(ViPipe, 0x3703, 0x20);
os04a10_write_register(ViPipe, 0x3705, 0x00);
os04a10_write_register(ViPipe, 0x3706, 0x72);
os04a10_write_register(ViPipe, 0x3707, 0x0a);
os04a10_write_register(ViPipe, 0x3708, 0x36);
os04a10_write_register(ViPipe, 0x3709, 0x57);
os04a10_write_register(ViPipe, 0x370a, 0x01);
os04a10_write_register(ViPipe, 0x370b, 0x14);
os04a10_write_register(ViPipe, 0x3714, 0x01);
os04a10_write_register(ViPipe, 0x3719, 0x1f);
os04a10_write_register(ViPipe, 0x371b, 0x16);
os04a10_write_register(ViPipe, 0x371c, 0x00);
os04a10_write_register(ViPipe, 0x371d, 0x08);
os04a10_write_register(ViPipe, 0x373f, 0x63);
os04a10_write_register(ViPipe, 0x3740, 0x63);
os04a10_write_register(ViPipe, 0x3741, 0x63);
os04a10_write_register(ViPipe, 0x3742, 0x63);
os04a10_write_register(ViPipe, 0x3743, 0x01);
os04a10_write_register(ViPipe, 0x3756, 0x9d);
os04a10_write_register(ViPipe, 0x3757, 0x9d);
os04a10_write_register(ViPipe, 0x3762, 0x1c);
os04a10_write_register(ViPipe, 0x376c, 0x34);
os04a10_write_register(ViPipe, 0x3776, 0x05);
os04a10_write_register(ViPipe, 0x3777, 0x22);
os04a10_write_register(ViPipe, 0x3779, 0x60);
os04a10_write_register(ViPipe, 0x377c, 0x48);
os04a10_write_register(ViPipe, 0x3784, 0x06);
os04a10_write_register(ViPipe, 0x3785, 0x0a);
os04a10_write_register(ViPipe, 0x3790, 0x10);
os04a10_write_register(ViPipe, 0x3793, 0x04);
os04a10_write_register(ViPipe, 0x3794, 0x07);
os04a10_write_register(ViPipe, 0x3796, 0x00);
os04a10_write_register(ViPipe, 0x3797, 0x02);
os04a10_write_register(ViPipe, 0x379c, 0x4d);
os04a10_write_register(ViPipe, 0x37a1, 0x80);
os04a10_write_register(ViPipe, 0x37bb, 0x88);
os04a10_write_register(ViPipe, 0x37be, 0x48);
os04a10_write_register(ViPipe, 0x37bf, 0x01);
os04a10_write_register(ViPipe, 0x37c0, 0x01);
os04a10_write_register(ViPipe, 0x37c4, 0x72);
os04a10_write_register(ViPipe, 0x37c5, 0x72);
os04a10_write_register(ViPipe, 0x37c6, 0x72);
os04a10_write_register(ViPipe, 0x37ca, 0x21);
os04a10_write_register(ViPipe, 0x37cc, 0x13);
os04a10_write_register(ViPipe, 0x37cd, 0x90);
os04a10_write_register(ViPipe, 0x37cf, 0x02);
os04a10_write_register(ViPipe, 0x37d0, 0x00);
os04a10_write_register(ViPipe, 0x37d1, 0x72);
os04a10_write_register(ViPipe, 0x37d2, 0x01);
os04a10_write_register(ViPipe, 0x37d3, 0x14);
os04a10_write_register(ViPipe, 0x37d4, 0x00);
os04a10_write_register(ViPipe, 0x37d5, 0x6c);
os04a10_write_register(ViPipe, 0x37d6, 0x00);
os04a10_write_register(ViPipe, 0x37d7, 0xf7);
os04a10_write_register(ViPipe, 0x37d8, 0x01);
os04a10_write_register(ViPipe, 0x37dc, 0x00);
os04a10_write_register(ViPipe, 0x37dd, 0x00);
os04a10_write_register(ViPipe, 0x37da, 0x00);
os04a10_write_register(ViPipe, 0x37db, 0x00);
os04a10_write_register(ViPipe, 0x3800, 0x00);
os04a10_write_register(ViPipe, 0x3801, 0x00);
os04a10_write_register(ViPipe, 0x3802, 0x00);
os04a10_write_register(ViPipe, 0x3803, 0x00);
os04a10_write_register(ViPipe, 0x3804, 0x0a);
os04a10_write_register(ViPipe, 0x3805, 0x8f);
os04a10_write_register(ViPipe, 0x3806, 0x05);
os04a10_write_register(ViPipe, 0x3807, 0xff);
os04a10_write_register(ViPipe, 0x3808, 0x0a);
os04a10_write_register(ViPipe, 0x3809, 0x80);
os04a10_write_register(ViPipe, 0x380a, 0x05);
os04a10_write_register(ViPipe, 0x380b, 0xf0);
os04a10_write_register(ViPipe, 0x380c, 0x02);
os04a10_write_register(ViPipe, 0x380d, 0xdc);
os04a10_write_register(ViPipe, 0x380e, 0x06);
os04a10_write_register(ViPipe, 0x380f, 0x58);
os04a10_write_register(ViPipe, 0x3811, 0x08);
os04a10_write_register(ViPipe, 0x3813, 0x08);
os04a10_write_register(ViPipe, 0x3814, 0x01);
os04a10_write_register(ViPipe, 0x3815, 0x01);
os04a10_write_register(ViPipe, 0x3816, 0x01);
os04a10_write_register(ViPipe, 0x3817, 0x01);
os04a10_write_register(ViPipe, 0x381c, 0x08);
os04a10_write_register(ViPipe, 0x3820, 0x03);
os04a10_write_register(ViPipe, 0x3821, 0x00);
os04a10_write_register(ViPipe, 0x3822, 0x14);
os04a10_write_register(ViPipe, 0x3823, 0x18);
os04a10_write_register(ViPipe, 0x3826, 0x00);
os04a10_write_register(ViPipe, 0x3827, 0x00);
os04a10_write_register(ViPipe, 0x3833, 0x41);
os04a10_write_register(ViPipe, 0x384c, 0x02);
os04a10_write_register(ViPipe, 0x384d, 0xdc);
os04a10_write_register(ViPipe, 0x3858, 0x3c);
os04a10_write_register(ViPipe, 0x3865, 0x02);
os04a10_write_register(ViPipe, 0x3866, 0x00);
os04a10_write_register(ViPipe, 0x3867, 0x00);
os04a10_write_register(ViPipe, 0x3868, 0x02);
os04a10_write_register(ViPipe, 0x3900, 0x13);
os04a10_write_register(ViPipe, 0x3940, 0x13);
os04a10_write_register(ViPipe, 0x3980, 0x13);
os04a10_write_register(ViPipe, 0x3c01, 0x11);
os04a10_write_register(ViPipe, 0x3c05, 0x00);
os04a10_write_register(ViPipe, 0x3c0f, 0x1c);
os04a10_write_register(ViPipe, 0x3c12, 0x0d);
os04a10_write_register(ViPipe, 0x3c19, 0x00);
os04a10_write_register(ViPipe, 0x3c21, 0x00);
os04a10_write_register(ViPipe, 0x3c3a, 0x10);
os04a10_write_register(ViPipe, 0x3c3b, 0x18);
os04a10_write_register(ViPipe, 0x3c3d, 0xc6);
os04a10_write_register(ViPipe, 0x3c55, 0x08);
os04a10_write_register(ViPipe, 0x3c5a, 0x55);
os04a10_write_register(ViPipe, 0x3c5d, 0xcf);
os04a10_write_register(ViPipe, 0x3c5e, 0xcf);
os04a10_write_register(ViPipe, 0x3d8c, 0x70);
os04a10_write_register(ViPipe, 0x3d8d, 0x10);
os04a10_write_register(ViPipe, 0x4000, 0xf9);
os04a10_write_register(ViPipe, 0x4001, 0xef);
os04a10_write_register(ViPipe, 0x4004, 0x00);
os04a10_write_register(ViPipe, 0x4005, 0x40);
os04a10_write_register(ViPipe, 0x4008, 0x02);
os04a10_write_register(ViPipe, 0x4009, 0x11);
os04a10_write_register(ViPipe, 0x400a, 0x06);
os04a10_write_register(ViPipe, 0x400b, 0x40);
os04a10_write_register(ViPipe, 0x400e, 0x40);
os04a10_write_register(ViPipe, 0x402e, 0x00);
os04a10_write_register(ViPipe, 0x402f, 0x40);
os04a10_write_register(ViPipe, 0x4030, 0x00);
os04a10_write_register(ViPipe, 0x4031, 0x40);
os04a10_write_register(ViPipe, 0x4032, 0x0f);
os04a10_write_register(ViPipe, 0x4033, 0x80);
os04a10_write_register(ViPipe, 0x4050, 0x00);
os04a10_write_register(ViPipe, 0x4051, 0x07);
os04a10_write_register(ViPipe, 0x4011, 0xbb);
os04a10_write_register(ViPipe, 0x410f, 0x01);
os04a10_write_register(ViPipe, 0x4288, 0xce);
os04a10_write_register(ViPipe, 0x4289, 0x00);
os04a10_write_register(ViPipe, 0x428a, 0x46);
os04a10_write_register(ViPipe, 0x430b, 0x0f);
os04a10_write_register(ViPipe, 0x430c, 0xfc);
os04a10_write_register(ViPipe, 0x430d, 0x00);
os04a10_write_register(ViPipe, 0x430e, 0x00);
os04a10_write_register(ViPipe, 0x4314, 0x04);
os04a10_write_register(ViPipe, 0x4500, 0x18);
os04a10_write_register(ViPipe, 0x4501, 0x18);
os04a10_write_register(ViPipe, 0x4503, 0x10);
os04a10_write_register(ViPipe, 0x4504, 0x00);
os04a10_write_register(ViPipe, 0x4506, 0x32);
os04a10_write_register(ViPipe, 0x4507, 0x03);
os04a10_write_register(ViPipe, 0x4601, 0x30);
os04a10_write_register(ViPipe, 0x4603, 0x00);
os04a10_write_register(ViPipe, 0x460a, 0x50);
os04a10_write_register(ViPipe, 0x460c, 0x60);
os04a10_write_register(ViPipe, 0x4640, 0x62);
os04a10_write_register(ViPipe, 0x4646, 0xaa);
os04a10_write_register(ViPipe, 0x4647, 0x55);
os04a10_write_register(ViPipe, 0x4648, 0x99);
os04a10_write_register(ViPipe, 0x4649, 0x66);
os04a10_write_register(ViPipe, 0x464d, 0x00);
os04a10_write_register(ViPipe, 0x4654, 0x11);
os04a10_write_register(ViPipe, 0x4655, 0x22);
os04a10_write_register(ViPipe, 0x4800, 0x44);
os04a10_write_register(ViPipe, 0x480e, 0x04);
os04a10_write_register(ViPipe, 0x4810, 0xff);
os04a10_write_register(ViPipe, 0x4811, 0xff);
os04a10_write_register(ViPipe, 0x4813, 0x84);
os04a10_write_register(ViPipe, 0x481f, 0x30);
os04a10_write_register(ViPipe, 0x4837, 0x0e);
os04a10_write_register(ViPipe, 0x484b, 0x67);
os04a10_write_register(ViPipe, 0x4d00, 0x4d);
os04a10_write_register(ViPipe, 0x4d01, 0x9d);
os04a10_write_register(ViPipe, 0x4d02, 0xb9);
os04a10_write_register(ViPipe, 0x4d03, 0x2e);
os04a10_write_register(ViPipe, 0x4d04, 0x4a);
os04a10_write_register(ViPipe, 0x4d05, 0x3d);
os04a10_write_register(ViPipe, 0x4d09, 0x4f);
os04a10_write_register(ViPipe, 0x5000, 0x1f);
os04a10_write_register(ViPipe, 0x5001, 0x0c);
os04a10_write_register(ViPipe, 0x5080, 0x00);
os04a10_write_register(ViPipe, 0x50c0, 0x00);
os04a10_write_register(ViPipe, 0x5100, 0x00);
os04a10_write_register(ViPipe, 0x5200, 0x00);
os04a10_write_register(ViPipe, 0x5201, 0x00);
os04a10_write_register(ViPipe, 0x5202, 0x03);
os04a10_write_register(ViPipe, 0x5203, 0xff);
os04a10_write_register(ViPipe, 0x5780, 0x53);
os04a10_write_register(ViPipe, 0x5782, 0x18);
os04a10_write_register(ViPipe, 0x5783, 0x3c);
os04a10_write_register(ViPipe, 0x5786, 0x01);
os04a10_write_register(ViPipe, 0x5788, 0x18);
os04a10_write_register(ViPipe, 0x5789, 0x3c);
os04a10_write_register(ViPipe, 0x5792, 0x11);
os04a10_write_register(ViPipe, 0x5793, 0x33);
os04a10_write_register(ViPipe, 0x5857, 0xff);
os04a10_write_register(ViPipe, 0x5858, 0xff);
os04a10_write_register(ViPipe, 0x5859, 0xff);
os04a10_write_register(ViPipe, 0x58d7, 0xff);
os04a10_write_register(ViPipe, 0x58d8, 0xff);
os04a10_write_register(ViPipe, 0x58d9, 0xff);
os04a10_default_reg_init(ViPipe);
os04a10_write_register(ViPipe, 0x0100, 0x01);
printf("ViPipe:%d,===OS04A10 1520P 30fps 10bit 2to1 WDR Init OK!===\n", ViPipe);
}

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_os04c10.a
TARGET_SO = $(MW_LIB)/libsns_os04c10.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

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middleware/v2/component/isp/sensor/cv180x/ov_os04c10/os04c10_cmos.c Normal file
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121
middleware/v2/component/isp/sensor/cv180x/ov_os04c10/os04c10_cmos_ex.h Normal file
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#ifndef __OS04C10_CMOS_EX_H_
#define __OS04C10_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
enum os04c10_linear_regs_e {
LINEAR_HOLD_START = 0,
LINEAR_EXP_0,
LINEAR_EXP_1,
LINEAR_AGAIN_0,
LINEAR_AGAIN_1,
LINEAR_DGAIN_0,
LINEAR_DGAIN_1,
LINEAR_VTS_0,
LINEAR_VTS_1,
LINEAR_HOLD_END,
LINEAR_LAUNCH_0,
LINEAR_LAUNCH_1,
LINEAR_REGS_NUM
};
enum os04c10_wdr2_regs_e {
WDR2_HOLD_START = 0,
WDR2_EXP1_0,
WDR2_EXP1_1,
WDR2_EXP2_0,
WDR2_EXP2_1,
WDR2_AGAIN1_0,
WDR2_AGAIN1_1,
WDR2_AGAIN2_0,
WDR2_AGAIN2_1,
WDR2_DGAIN1_0,
WDR2_DGAIN1_1,
WDR2_DGAIN2_0,
WDR2_DGAIN2_1,
WDR2_VTS_0,
WDR2_VTS_1,
WDR2_HOLD_END,
WDR2_LAUNCH_0,
WDR2_LAUNCH_1,
WDR2_GGAIN_0,
WDR2_GGAIN_1,
WDR2_REGS_NUM
};
typedef enum _OS04C10_MODE_E {
OS04C10_MODE_2688X1520P30 = 0,
OS04C10_MODE_2560X1440P30,
OS04C10_MODE_LINEAR_NUM,
OS04C10_MODE_2688X1520P30_WDR = OS04C10_MODE_LINEAR_NUM,
OS04C10_MODE_2560X1440P30_WDR,
OS04C10_MODE_NUM
} OS04C10_MODE_E;
typedef struct _OS04C10_STATE_S {
CVI_U32 u32Sexp_MAX;
} OS04C10_STATE_S;
typedef struct _OS04C10_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
CVI_U16 u16L2sOffset;
CVI_U16 u16TopBoundary;
CVI_U16 u16BotBoundary;
SNS_ATTR_S stExp[2];
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
CVI_U32 u32L2S_offset;
CVI_U32 u32IspResTime;
CVI_U32 u32HdrMargin;
char name[64];
} OS04C10_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastOs04c10[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunOs04c10_BusInfo[];
extern CVI_U16 g_au16Os04c10_GainMode[];
extern CVI_U16 g_au16Os04c10_UseHwSync[VI_MAX_PIPE_NUM];
extern CVI_U8 os04c10_i2c_addr;
extern const CVI_U32 os04c10_addr_byte;
extern const CVI_U32 os04c10_data_byte;
extern void os04c10_init(VI_PIPE ViPipe);
extern void os04c10_exit(VI_PIPE ViPipe);
extern void os04c10_standby(VI_PIPE ViPipe);
extern void os04c10_restart(VI_PIPE ViPipe);
extern int os04c10_write_register(VI_PIPE ViPipe, int addr, int data);
extern int os04c10_read_register(VI_PIPE ViPipe, int addr);
extern void os04c10_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int os04c10_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OS04C10_CMOS_EX_H_ */

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#ifndef __OS04C10_CMOS_PARAM_H_
#define __OS04C10_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "os04c10_cmos_ex.h"
static const OS04C10_MODE_S g_astOs04c10_mode[OS04C10_MODE_NUM] = {
[OS04C10_MODE_2688X1520P30] = {
.name = "2688x1520p30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2688,
.u32Height = 1520,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2688,
.u32Height = 1520,
},
.stMaxSize = {
.u32Width = 2688,
.u32Height = 1520,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.73, /* 0x626 * 30 / 0xFFFF */
.u32HtsDef = 3116,
.u32VtsDef = 1574,
.stExp[0] = {
.u16Min = 2,
.u16Max = 1574 - 8,
.u16Def = 500,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
},
[OS04C10_MODE_2560X1440P30] = {
.name = "2560x1440p30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.73, /* 0x626 * 30 / 0xFFFF */
.u32HtsDef = 3116,
.u32VtsDef = 1574,
.stExp[0] = {
.u16Min = 2,
.u16Max = 1574 - 8,
.u16Def = 500,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
},
[OS04C10_MODE_2688X1520P30_WDR] = {
.name = "2688x1520p30wdr",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2688,
.u32Height = 1520,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2688,
.u32Height = 1520,
},
.stMaxSize = {
.u32Width = 2688,
.u32Height = 1520,
},
},
.astImg[1] = {
.stSnsSize = {
.u32Width = 2688,
.u32Height = 1520,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2688,
.u32Height = 1520,
},
.stMaxSize = {
.u32Width = 2688,
.u32Height = 1520,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.77, /* 1682 * 30 / 0xFFFF */
.u32HtsDef = 2972,
.u32VtsDef = 1682,
.u16L2sOffset = 4,
.u16TopBoundary = 24,
.u16BotBoundary = 244,
.stExp[0] = {
.u16Min = 8,
.u16Max = 88,
.u16Def = 88,
.u16Step = 1,
},
.stExp[1] = {
.u16Min = 8,
.u16Max = 0x486 - 4 - 88,
.u16Def = 500,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stAgain[1] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[1] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
.u32L2S_offset = 4,
.u32IspResTime = 50, /* about 1ms * line rate */
.u32HdrMargin = 40, /* black_line + zero_line + ISP_offset * 2 */
},
[OS04C10_MODE_2560X1440P30_WDR] = {
.name = "2560x1440p30wdr",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.astImg[1] = {
.stSnsSize = {
.u32Width = 2560,
.u32Height = 1440,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2560,
.u32Height = 1440,
},
.stMaxSize = {
.u32Width = 2560,
.u32Height = 1440,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.77, /* 1682 * 30 / 0xFFFF */
.u32HtsDef = 2972,
.u32VtsDef = 1682,
.u16L2sOffset = 4,
.u16TopBoundary = 24,
.u16BotBoundary = 244,
.stExp[0] = {
.u16Min = 8,
.u16Max = 88,
.u16Def = 88,
.u16Step = 1,
},
.stExp[1] = {
.u16Min = 8,
.u16Max = 0x486 - 4 - 88,
.u16Def = 500,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stAgain[1] = {
.u32Min = 1024,
.u32Max = 15872,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[1] = {
.u32Min = 1024,
.u32Max = 16384,
.u32Def = 1024,
.u32Step = 1,
},
.u32L2S_offset = 4,
.u32IspResTime = 50, /* about 1ms * line rate */
.u32HdrMargin = 40, /* black_line + zero_line + ISP_offset * 2 */
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {128, 128, 128, 128, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1057, 1057, 1057, 1057
#endif
},
.stAuto = {
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
#endif
},
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio10Bit = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {256, 256, 256, 256, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1092, 1092, 1092, 1092
#endif
},
.stAuto = {
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
#endif
},
},
};
struct combo_dev_attr_s os04c10_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_12BIT,
.lane_id = {0, 1, 2, -1, -1},
.pn_swap = {1, 1, 1, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_VC,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_25M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OS04C10_CMOS_PARAM_H_ */

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_os08a20.a
TARGET_SO = $(MW_LIB)/libsns_os08a20.so
EXTRA_CFLAGS = $(INCS) $(PROJ_CFLAGS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@)
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@)
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

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#ifndef __OS08A20_CMOS_EX_H_
#define __OS08A20_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
enum os08a20_linear_regs_e {
LINEAR_HOLD1 = 0,
LINEAR_HOLD2,
LINEAR_HOLD3,
LINEAR_EXP_0,
LINEAR_EXP_1,
LINEAR_AGAIN_0,
LINEAR_AGAIN_1,
LINEAR_DGAIN_0,
LINEAR_DGAIN_1,
LINEAR_VTS_0,
LINEAR_VTS_1,
LINEAR_REL1,
LINEAR_REL2,
LINEAR_REL3,
LINEAR_REGS_NUM
};
enum os08a20_wdr2_regs_e {
WDR2_HOLD1 = 0,
WDR2_HOLD2,
WDR2_HOLD3,
WDR2_EXP1_0,
WDR2_EXP1_1,
WDR2_EXP2_0,
WDR2_EXP2_1,
WDR2_AGAIN1_0,
WDR2_AGAIN1_1,
WDR2_AGAIN2_0,
WDR2_AGAIN2_1,
WDR2_DGAIN1_0,
WDR2_DGAIN1_1,
WDR2_DGAIN2_0,
WDR2_DGAIN2_1,
WDR2_VTS_0,
WDR2_VTS_1,
WDR2_REL1,
WDR2_REL2,
WDR2_REL3,
WDR2_REGS_NUM
};
typedef enum _OS08A20_MODE_E {
OS08A20_MODE_2592X1944P30 = 0,
OS08A20_MODE_LINEAR_NUM,
OS08A20_MODE_2592X1944P30_WDR = OS08A20_MODE_LINEAR_NUM,
OS08A20_MODE_NUM
} OS08A20_MODE_E;
typedef struct _OS08A20_STATE_S {
CVI_U32 u32Sexp_MAX;
} OS08A20_STATE_S;
typedef struct _OS08A20_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
CVI_U16 u16L2sOffset;
CVI_U16 u16TopBoundary;
CVI_U16 u16BotBoundary;
SNS_ATTR_S stExp[2];
SNS_ATTR_S stAgain[2];
SNS_ATTR_S stDgain[2];
CVI_U32 u32L2S_MAX;
char name[64];
} OS08A20_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastOs08a20[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunOs08a20_BusInfo[];
extern CVI_U16 g_au16Os08a20_GainMode[];
extern CVI_U16 g_au16Os08a20_L2SMode[VI_MAX_PIPE_NUM];
extern const CVI_U8 os08a20_i2c_addr;
extern const CVI_U32 os08a20_addr_byte;
extern const CVI_U32 os08a20_data_byte;
extern void os08a20_init(VI_PIPE ViPipe);
extern void os08a20_exit(VI_PIPE ViPipe);
extern void os08a20_standby(VI_PIPE ViPipe);
extern void os08a20_restart(VI_PIPE ViPipe);
extern int os08a20_write_register(VI_PIPE ViPipe, int addr, int data);
extern int os08a20_read_register(VI_PIPE ViPipe, int addr);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OS08A20_CMOS_EX_H_ */

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#ifndef __OS08A20_CMOS_PARAM_H_
#define __OS08A20_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "os08a20_cmos_ex.h"
static const OS08A20_MODE_S g_astOs08a20_mode[OS08A20_MODE_NUM] = {
[OS08A20_MODE_2592X1944P30] = {
.name = "2592x1944p30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2592,
.u32Height = 1944,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2592,
.u32Height = 1944,
},
.stMaxSize = {
.u32Width = 2592,
.u32Height = 1944,
},
},
.f32MaxFps = 30,
.f32MinFps = 1.06, /* 0x90a * 30 / 0xFFFF */
.u32HtsDef = 0x818,
.u32VtsDef = 0x90a,
.stExp[0] = {
.u16Min = 8,
.u16Max = 0x90a - 8,
.u16Def = 0x462,
.u16Step = 1,
},
.stAgain[0] = {
.u16Min = 1024,
.u16Max = 15872,
.u16Def = 1024,
.u16Step = 1,
},
.stDgain[0] = {
.u16Min = 1024,
.u16Max = 16383,
.u16Def = 1024,
.u16Step = 1,
},
},
[OS08A20_MODE_2592X1944P30_WDR] = {
.name = "2592x1944p30wdr",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2592,
.u32Height = 1944,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2592,
.u32Height = 1944,
},
.stMaxSize = {
.u32Width = 2592,
.u32Height = 1944,
},
},
.astImg[1] = {
.stSnsSize = {
.u32Width = 2592,
.u32Height = 1944,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2592,
.u32Height = 1944,
},
.stMaxSize = {
.u32Width = 2592,
.u32Height = 1944,
},
},
.f32MaxFps = 30,
.f32MinFps = 1.08, /* 0x92a * 30 / 0xFFFF */
.u32HtsDef = 0x40c,
.u32VtsDef = 0x92a,
.u16L2sOffset = 4,
.u16TopBoundary = 36,
.u16BotBoundary = 8,
.stExp[0] = {
.u16Min = 8,
.u16Max = 312,
.u16Def = 100,
.u16Step = 1,
},
.stExp[1] = {
.u16Min = 8,
.u16Max = 0x486 - 4 - 312,
.u16Def = 500,
.u16Step = 1,
},
.stAgain[0] = {
.u16Min = 1024,
.u16Max = 15872,
.u16Def = 1024,
.u16Step = 1,
},
.stAgain[1] = {
.u16Min = 1024,
.u16Max = 15872,
.u16Def = 1024,
.u16Step = 1,
},
.stDgain[0] = {
.u16Min = 1024,
.u16Max = 16383,
.u16Def = 1024,
.u16Step = 1,
},
.stDgain[1] = {
.u16Min = 1024,
.u16Max = 16383,
.u16Def = 1024,
.u16Step = 1,
},
.u32L2S_MAX = 0x13D,
},
};
static ISP_CMOS_NOISE_CALIBRATION_S g_stIspNoiseCalibratio = {.CalibrationCoef = {
{ //iso 100
{0.03190412744879722595, 3.86617159843444824219}, //B: slope, intercept
{0.02441397681832313538, 4.87663412094116210938}, //Gb: slope, intercept
{0.02471913769841194153, 4.85860157012939453125}, //Gr: slope, intercept
{0.02652409672737121582, 4.48996973037719726563}, //R: slope, intercept
},
{ //iso 200
{0.04349273815751075745, 5.49785566329956054688}, //B: slope, intercept
{0.03087714128196239471, 7.49881792068481445313}, //Gb: slope, intercept
{0.03145518898963928223, 7.35760211944580078125}, //Gr: slope, intercept
{0.03530855849385261536, 6.56339693069458007813}, //R: slope, intercept
},
{ //iso 400
{0.05788951739668846130, 8.34851074218750000000}, //B: slope, intercept
{0.04015926644206047058, 11.21226787567138671875}, //Gb: slope, intercept
{0.04018958285450935364, 11.29319286346435546875}, //Gr: slope, intercept
{0.04840981587767601013, 9.35622310638427734375}, //R: slope, intercept
},
{ //iso 800
{0.08085585385560989380, 11.91084861755371093750}, //B: slope, intercept
{0.05333026498556137085, 16.38746833801269531250}, //Gb: slope, intercept
{0.05413141101598739624, 16.21148872375488281250}, //Gr: slope, intercept
{0.06530260294675827026, 13.91790008544921875000}, //R: slope, intercept
},
{ //iso 1600
{0.09407941251993179321, 17.58893775939941406250}, //B: slope, intercept
{0.05309880897402763367, 24.13221168518066406250}, //Gb: slope, intercept
{0.05440055206418037415, 23.84361267089843750000}, //Gr: slope, intercept
{0.06805266439914703369, 20.56119728088378906250}, //R: slope, intercept
},
{ //iso 3200
{0.09407941251993179321, 17.58893775939941406250}, //B: slope, intercept
{0.05309880897402763367, 24.13221168518066406250}, //Gb: slope, intercept
{0.05440055206418037415, 23.84361267089843750000}, //Gr: slope, intercept
{0.06805266439914703369, 20.56119728088378906250}, //R: slope, intercept
},
{ //iso 6400
{0.09407941251993179321, 17.58893775939941406250}, //B: slope, intercept
{0.05309880897402763367, 24.13221168518066406250}, //Gb: slope, intercept
{0.05440055206418037415, 23.84361267089843750000}, //Gr: slope, intercept
{0.06805266439914703369, 20.56119728088378906250}, //R: slope, intercept
},
{ //iso 12800
{0.09407941251993179321, 17.58893775939941406250}, //B: slope, intercept
{0.05309880897402763367, 24.13221168518066406250}, //Gb: slope, intercept
{0.05440055206418037415, 23.84361267089843750000}, //Gr: slope, intercept
{0.06805266439914703369, 20.56119728088378906250}, //R: slope, intercept
},
{ //iso 25600
{0.48950406908988952637, 67.73629760742187500000}, //B: slope, intercept
{0.25487670302391052246, 101.95156860351562500000}, //Gb: slope, intercept
{0.24315287172794342041, 105.36353302001953125000}, //Gr: slope, intercept
{0.33707463741302490234, 86.65032958984375000000}, //R: slope, intercept
},
{ //iso 51200
{0.48950406908988952637, 67.73629760742187500000}, //B: slope, intercept
{0.25487670302391052246, 101.95156860351562500000}, //Gb: slope, intercept
{0.24315287172794342041, 105.36353302001953125000}, //Gr: slope, intercept
{0.33707463741302490234, 86.65032958984375000000}, //R: slope, intercept
},
{ //iso 102400
{0.48950406908988952637, 67.73629760742187500000}, //B: slope, intercept
{0.25487670302391052246, 101.95156860351562500000}, //Gb: slope, intercept
{0.24315287172794342041, 105.36353302001953125000}, //Gr: slope, intercept
{0.33707463741302490234, 86.65032958984375000000}, //R: slope, intercept
},
{ //iso 204800
{0.48950406908988952637, 67.73629760742187500000}, //B: slope, intercept
{0.25487670302391052246, 101.95156860351562500000}, //Gb: slope, intercept
{0.24315287172794342041, 105.36353302001953125000}, //Gr: slope, intercept
{0.33707463741302490234, 86.65032958984375000000}, //R: slope, intercept
},
{ //iso 409600
{0.48950406908988952637, 67.73629760742187500000}, //B: slope, intercept
{0.25487670302391052246, 101.95156860351562500000}, //Gb: slope, intercept
{0.24315287172794342041, 105.36353302001953125000}, //Gr: slope, intercept
{0.33707463741302490234, 86.65032958984375000000}, //R: slope, intercept
},
{ //iso 819200
{0.48950406908988952637, 67.73629760742187500000}, //B: slope, intercept
{0.25487670302391052246, 101.95156860351562500000}, //Gb: slope, intercept
{0.24315287172794342041, 105.36353302001953125000}, //Gr: slope, intercept
{0.33707463741302490234, 86.65032958984375000000}, //R: slope, intercept
},
{ //iso 1638400
{0.48950406908988952637, 67.73629760742187500000}, //B: slope, intercept
{0.25487670302391052246, 101.95156860351562500000}, //Gb: slope, intercept
{0.24315287172794342041, 105.36353302001953125000}, //Gr: slope, intercept
{0.33707463741302490234, 86.65032958984375000000}, //R: slope, intercept
},
{ //iso 3276800
{0.48950406908988952637, 67.73629760742187500000}, //B: slope, intercept
{0.25487670302391052246, 101.95156860351562500000}, //Gb: slope, intercept
{0.24315287172794342041, 105.36353302001953125000}, //Gr: slope, intercept
{0.33707463741302490234, 86.65032958984375000000}, //R: slope, intercept
},
} };
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {256, 256, 256, 256, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1092, 1092, 1092, 1092
#endif
},
.stAuto = {
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{256, 256, 256, 256, 256, 256, 256, 256, /*8*/256, 256, 256, 256, 256, 256, 256, 256},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
{1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092,
/*8*/1092, 1092, 1092, 1092, 1092, 1092, 1092, 1092},
#endif
},
},
};
struct combo_dev_attr_s os08a20_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_600M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {3, 2, 1, 4, 0},
.pn_swap = {1, 1, 1, 1, 1},
.wdr_mode = CVI_MIPI_WDR_MODE_VC,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_25M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OS08A20_CMOS_PARAM_H_ */

585
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@ -0,0 +1,585 @@
#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "os08a20_cmos_ex.h"
static void os08a20_wdr_1944p30_2to1_init(VI_PIPE ViPipe);
static void os08a20_linear_1944p30_init(VI_PIPE ViPipe);
const CVI_U8 os08a20_i2c_addr = 0x36; /* I2C Address of OS08A20 */
const CVI_U32 os08a20_addr_byte = 2;
const CVI_U32 os08a20_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int os08a20_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunOs08a20_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, os08a20_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int os08a20_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int os08a20_read_register(VI_PIPE ViPipe, int addr)
{
/* TODO:*/
(void) ViPipe;
(void) addr;
return CVI_SUCCESS;
}
int os08a20_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (os08a20_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (os08a20_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, os08a20_addr_byte + os08a20_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void os08a20_standby(VI_PIPE ViPipe)
{
os08a20_write_register(ViPipe, 0x0100, 0x00); /* STANDBY */
}
void os08a20_restart(VI_PIPE ViPipe)
{
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
}
void os08a20_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
/* by pass the group hold and clear registers since it won't update when stream is off. */
for (i = 3; i < g_pastOs08a20[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum - 3; i++) {
os08a20_write_register(ViPipe,
g_pastOs08a20[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastOs08a20[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
void os08a20_init(VI_PIPE ViPipe)
{
WDR_MODE_E enWDRMode;
CVI_U8 u8ImgMode;
enWDRMode = g_pastOs08a20[ViPipe]->enWDRMode;
u8ImgMode = g_pastOs08a20[ViPipe]->u8ImgMode;
os08a20_i2c_init(ViPipe);
if (enWDRMode == WDR_MODE_2To1_LINE) {
if (u8ImgMode == OS08A20_MODE_2592X1944P30_WDR)
os08a20_wdr_1944p30_2to1_init(ViPipe);
else {
}
} else {
if (u8ImgMode == OS08A20_MODE_2592X1944P30)
os08a20_linear_1944p30_init(ViPipe);
else {
}
}
g_pastOs08a20[ViPipe]->bInit = CVI_TRUE;
}
void os08a20_exit(VI_PIPE ViPipe)
{
os08a20_i2c_exit(ViPipe);
}
/* 1944P30 and 1944P25 */
static void os08a20_linear_1944p30_init(VI_PIPE ViPipe)
{
os08a20_write_register(ViPipe, 0x0100, 0x00);
os08a20_write_register(ViPipe, 0x0103, 0x01);
os08a20_write_register(ViPipe, 0x0303, 0x01);
os08a20_write_register(ViPipe, 0x0305, 0x5a);
os08a20_write_register(ViPipe, 0x0306, 0x00);
os08a20_write_register(ViPipe, 0x0308, 0x03);
os08a20_write_register(ViPipe, 0x0309, 0x04);
os08a20_write_register(ViPipe, 0x032a, 0x00);
os08a20_write_register(ViPipe, 0x300f, 0x11);
os08a20_write_register(ViPipe, 0x3010, 0x01);
os08a20_write_register(ViPipe, 0x3011, 0x04);
os08a20_write_register(ViPipe, 0x3012, 0x41);
os08a20_write_register(ViPipe, 0x3016, 0xf0);
os08a20_write_register(ViPipe, 0x301e, 0x98);
os08a20_write_register(ViPipe, 0x3031, 0xa9);
os08a20_write_register(ViPipe, 0x3103, 0x92);
os08a20_write_register(ViPipe, 0x3104, 0x01);
os08a20_write_register(ViPipe, 0x3106, 0x10);
os08a20_write_register(ViPipe, 0x3400, 0x04);
os08a20_write_register(ViPipe, 0x3025, 0x03);
os08a20_write_register(ViPipe, 0x3425, 0x01);
os08a20_write_register(ViPipe, 0x3428, 0x01);
os08a20_write_register(ViPipe, 0x3406, 0x08);
os08a20_write_register(ViPipe, 0x3408, 0x03);
os08a20_write_register(ViPipe, 0x340c, 0xff);
os08a20_write_register(ViPipe, 0x340d, 0xff);
os08a20_write_register(ViPipe, 0x031e, 0x09);
os08a20_write_register(ViPipe, 0x3501, 0x08);
os08a20_write_register(ViPipe, 0x3502, 0xe5);
os08a20_write_register(ViPipe, 0x3505, 0x83);
os08a20_write_register(ViPipe, 0x3508, 0x00);
os08a20_write_register(ViPipe, 0x3509, 0x80);
os08a20_write_register(ViPipe, 0x350a, 0x04);
os08a20_write_register(ViPipe, 0x350b, 0x00);
os08a20_write_register(ViPipe, 0x350c, 0x00);
os08a20_write_register(ViPipe, 0x350d, 0x80);
os08a20_write_register(ViPipe, 0x350e, 0x04);
os08a20_write_register(ViPipe, 0x350f, 0x00);
os08a20_write_register(ViPipe, 0x3600, 0x00);
os08a20_write_register(ViPipe, 0x3603, 0x2c);
os08a20_write_register(ViPipe, 0x3605, 0x50);
os08a20_write_register(ViPipe, 0x3609, 0xb5);
os08a20_write_register(ViPipe, 0x3610, 0x39);
os08a20_write_register(ViPipe, 0x360c, 0x01);
os08a20_write_register(ViPipe, 0x3628, 0xa4);
os08a20_write_register(ViPipe, 0x362d, 0x10);
os08a20_write_register(ViPipe, 0x3660, 0x43);
os08a20_write_register(ViPipe, 0x3661, 0x06);
os08a20_write_register(ViPipe, 0x3662, 0x00);
os08a20_write_register(ViPipe, 0x3663, 0x28);
os08a20_write_register(ViPipe, 0x3664, 0x0d);
os08a20_write_register(ViPipe, 0x366a, 0x38);
os08a20_write_register(ViPipe, 0x366b, 0xa0);
os08a20_write_register(ViPipe, 0x366d, 0x00);
os08a20_write_register(ViPipe, 0x366e, 0x00);
os08a20_write_register(ViPipe, 0x3680, 0x00);
os08a20_write_register(ViPipe, 0x36c0, 0x00);
os08a20_write_register(ViPipe, 0x3701, 0x02);
os08a20_write_register(ViPipe, 0x373b, 0x02);
os08a20_write_register(ViPipe, 0x373c, 0x02);
os08a20_write_register(ViPipe, 0x3736, 0x02);
os08a20_write_register(ViPipe, 0x3737, 0x02);
os08a20_write_register(ViPipe, 0x3705, 0x00);
os08a20_write_register(ViPipe, 0x3706, 0x39);
os08a20_write_register(ViPipe, 0x370a, 0x00);
os08a20_write_register(ViPipe, 0x370b, 0x98);
os08a20_write_register(ViPipe, 0x3709, 0x49);
os08a20_write_register(ViPipe, 0x3714, 0x21);
os08a20_write_register(ViPipe, 0x371c, 0x00);
os08a20_write_register(ViPipe, 0x371d, 0x08);
os08a20_write_register(ViPipe, 0x3740, 0x1b);
os08a20_write_register(ViPipe, 0x3741, 0x04);
os08a20_write_register(ViPipe, 0x375e, 0x0b);
os08a20_write_register(ViPipe, 0x3760, 0x10);
os08a20_write_register(ViPipe, 0x3776, 0x10);
os08a20_write_register(ViPipe, 0x3781, 0x02);
os08a20_write_register(ViPipe, 0x3782, 0x04);
os08a20_write_register(ViPipe, 0x3783, 0x02);
os08a20_write_register(ViPipe, 0x3784, 0x08);
os08a20_write_register(ViPipe, 0x3785, 0x08);
os08a20_write_register(ViPipe, 0x3788, 0x01);
os08a20_write_register(ViPipe, 0x3789, 0x01);
os08a20_write_register(ViPipe, 0x3797, 0x04);
os08a20_write_register(ViPipe, 0x3762, 0x11);
os08a20_write_register(ViPipe, 0x3800, 0x00);
os08a20_write_register(ViPipe, 0x3801, 0x00);
os08a20_write_register(ViPipe, 0x3802, 0x00);
os08a20_write_register(ViPipe, 0x3803, 0x0c);
os08a20_write_register(ViPipe, 0x3804, 0x0e);
os08a20_write_register(ViPipe, 0x3805, 0xff);
os08a20_write_register(ViPipe, 0x3806, 0x08);
os08a20_write_register(ViPipe, 0x3807, 0x6f);
os08a20_write_register(ViPipe, 0x3808, 0x0f);
os08a20_write_register(ViPipe, 0x3809, 0x00);
os08a20_write_register(ViPipe, 0x380a, 0x08);
os08a20_write_register(ViPipe, 0x380b, 0x70);
os08a20_write_register(ViPipe, 0x380c, 0x04);
os08a20_write_register(ViPipe, 0x380d, 0x0c);
os08a20_write_register(ViPipe, 0x380e, 0x09);
os08a20_write_register(ViPipe, 0x380f, 0x0a);
os08a20_write_register(ViPipe, 0x3813, 0x10);
os08a20_write_register(ViPipe, 0x3814, 0x01);
os08a20_write_register(ViPipe, 0x3815, 0x01);
os08a20_write_register(ViPipe, 0x3816, 0x01);
os08a20_write_register(ViPipe, 0x3817, 0x01);
os08a20_write_register(ViPipe, 0x381c, 0x00);
os08a20_write_register(ViPipe, 0x3820, 0x00);
os08a20_write_register(ViPipe, 0x3821, 0x04);
os08a20_write_register(ViPipe, 0x3823, 0x08);
os08a20_write_register(ViPipe, 0x3826, 0x00);
os08a20_write_register(ViPipe, 0x3827, 0x08);
os08a20_write_register(ViPipe, 0x382d, 0x08);
os08a20_write_register(ViPipe, 0x3832, 0x02);
os08a20_write_register(ViPipe, 0x3833, 0x00);
os08a20_write_register(ViPipe, 0x383c, 0x48);
os08a20_write_register(ViPipe, 0x383d, 0xff);
os08a20_write_register(ViPipe, 0x3d85, 0x0b);
os08a20_write_register(ViPipe, 0x3d84, 0x40);
os08a20_write_register(ViPipe, 0x3d8c, 0x63);
os08a20_write_register(ViPipe, 0x3d8d, 0xd7);
os08a20_write_register(ViPipe, 0x4000, 0xf8);
os08a20_write_register(ViPipe, 0x4001, 0x2b);
os08a20_write_register(ViPipe, 0x4004, 0x00);
os08a20_write_register(ViPipe, 0x4005, 0x40);
os08a20_write_register(ViPipe, 0x400a, 0x01);
os08a20_write_register(ViPipe, 0x400f, 0xa0);
os08a20_write_register(ViPipe, 0x4010, 0x12);
os08a20_write_register(ViPipe, 0x4018, 0x00);
os08a20_write_register(ViPipe, 0x4008, 0x02);
os08a20_write_register(ViPipe, 0x4009, 0x0d);
os08a20_write_register(ViPipe, 0x401a, 0x58);
os08a20_write_register(ViPipe, 0x4050, 0x00);
os08a20_write_register(ViPipe, 0x4051, 0x01);
os08a20_write_register(ViPipe, 0x4028, 0x2f);
os08a20_write_register(ViPipe, 0x4052, 0x00);
os08a20_write_register(ViPipe, 0x4053, 0x80);
os08a20_write_register(ViPipe, 0x4054, 0x00);
os08a20_write_register(ViPipe, 0x4055, 0x80);
os08a20_write_register(ViPipe, 0x4056, 0x00);
os08a20_write_register(ViPipe, 0x4057, 0x80);
os08a20_write_register(ViPipe, 0x4058, 0x00);
os08a20_write_register(ViPipe, 0x4059, 0x80);
os08a20_write_register(ViPipe, 0x430b, 0xff);
os08a20_write_register(ViPipe, 0x430c, 0xff);
os08a20_write_register(ViPipe, 0x430d, 0x00);
os08a20_write_register(ViPipe, 0x430e, 0x00);
os08a20_write_register(ViPipe, 0x4501, 0x18);
os08a20_write_register(ViPipe, 0x4502, 0x00);
os08a20_write_register(ViPipe, 0x4643, 0x00);
os08a20_write_register(ViPipe, 0x4640, 0x01);
os08a20_write_register(ViPipe, 0x4641, 0x04);
os08a20_write_register(ViPipe, 0x4800, 0x64);
os08a20_write_register(ViPipe, 0x4809, 0x2b);
os08a20_write_register(ViPipe, 0x4813, 0x90);
os08a20_write_register(ViPipe, 0x4817, 0x04);
os08a20_write_register(ViPipe, 0x4833, 0x18);
os08a20_write_register(ViPipe, 0x4837, 0x0b);
os08a20_write_register(ViPipe, 0x483b, 0x00);
os08a20_write_register(ViPipe, 0x484b, 0x03);
os08a20_write_register(ViPipe, 0x4850, 0x7c);
os08a20_write_register(ViPipe, 0x4852, 0x06);
os08a20_write_register(ViPipe, 0x4856, 0x58);
os08a20_write_register(ViPipe, 0x4857, 0xaa);
os08a20_write_register(ViPipe, 0x4862, 0x0a);
os08a20_write_register(ViPipe, 0x4869, 0x18);
os08a20_write_register(ViPipe, 0x486a, 0xaa);
os08a20_write_register(ViPipe, 0x486e, 0x03);
os08a20_write_register(ViPipe, 0x486f, 0x55);
os08a20_write_register(ViPipe, 0x4875, 0xf0);
os08a20_write_register(ViPipe, 0x5000, 0x89);
os08a20_write_register(ViPipe, 0x5001, 0x42);
os08a20_write_register(ViPipe, 0x5004, 0x40);
os08a20_write_register(ViPipe, 0x5005, 0x00);
os08a20_write_register(ViPipe, 0x5180, 0x00);
os08a20_write_register(ViPipe, 0x5181, 0x10);
os08a20_write_register(ViPipe, 0x580b, 0x03);
os08a20_write_register(ViPipe, 0x4d00, 0x03);
os08a20_write_register(ViPipe, 0x4d01, 0xc9);
os08a20_write_register(ViPipe, 0x4d02, 0xbc);
os08a20_write_register(ViPipe, 0x4d03, 0xc6);
os08a20_write_register(ViPipe, 0x4d04, 0x4a);
os08a20_write_register(ViPipe, 0x4d05, 0x25);
os08a20_write_register(ViPipe, 0x4700, 0x2b);
os08a20_write_register(ViPipe, 0x4e00, 0x2b);
os08a20_write_register(ViPipe, 0x3501, 0x09);
os08a20_write_register(ViPipe, 0x3502, 0x01);
os08a20_write_register(ViPipe, 0x0305, 0x57);
os08a20_write_register(ViPipe, 0x380c, 0x08);
os08a20_write_register(ViPipe, 0x380d, 0x18);
os08a20_write_register(ViPipe, 0x380e, 0x09);
os08a20_write_register(ViPipe, 0x380f, 0x0a);
os08a20_write_register(ViPipe, 0x3501, 0x09);
os08a20_write_register(ViPipe, 0x3502, 0x02);
os08a20_write_register(ViPipe, 0x3808, 0x0a);
os08a20_write_register(ViPipe, 0x3809, 0x20);
os08a20_write_register(ViPipe, 0x380a, 0x07);
os08a20_write_register(ViPipe, 0x380b, 0x98);
os08a20_default_reg_init(ViPipe);
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
delay_ms(50);
printf("ViPipe:%d,===OS08A20 1944P 30fps 10bit LINE Init OK!===\n", ViPipe);
}
static void os08a20_wdr_1944p30_2to1_init(VI_PIPE ViPipe)
{
os08a20_write_register(ViPipe, 0x0100, 0x00);
os08a20_write_register(ViPipe, 0x0103, 0x01);
os08a20_write_register(ViPipe, 0x0303, 0x01);
os08a20_write_register(ViPipe, 0x0305, 0x5a);
os08a20_write_register(ViPipe, 0x0306, 0x00);
os08a20_write_register(ViPipe, 0x0308, 0x03);
os08a20_write_register(ViPipe, 0x0309, 0x04);
os08a20_write_register(ViPipe, 0x032a, 0x00);
os08a20_write_register(ViPipe, 0x300f, 0x11);
os08a20_write_register(ViPipe, 0x3010, 0x01);
os08a20_write_register(ViPipe, 0x3011, 0x04);
os08a20_write_register(ViPipe, 0x3012, 0x41);
os08a20_write_register(ViPipe, 0x3016, 0xf0);
os08a20_write_register(ViPipe, 0x301e, 0x98);
os08a20_write_register(ViPipe, 0x3031, 0xa9);
os08a20_write_register(ViPipe, 0x3103, 0x92);
os08a20_write_register(ViPipe, 0x3104, 0x01);
os08a20_write_register(ViPipe, 0x3106, 0x10);
os08a20_write_register(ViPipe, 0x340c, 0xff);
os08a20_write_register(ViPipe, 0x340d, 0xff);
os08a20_write_register(ViPipe, 0x031e, 0x09);
os08a20_write_register(ViPipe, 0x3501, 0x08);
os08a20_write_register(ViPipe, 0x3502, 0xe5);
os08a20_write_register(ViPipe, 0x3505, 0x83);
os08a20_write_register(ViPipe, 0x3508, 0x00);
os08a20_write_register(ViPipe, 0x3509, 0x80);
os08a20_write_register(ViPipe, 0x350a, 0x04);
os08a20_write_register(ViPipe, 0x350b, 0x00);
os08a20_write_register(ViPipe, 0x350c, 0x00);
os08a20_write_register(ViPipe, 0x350d, 0x80);
os08a20_write_register(ViPipe, 0x350e, 0x04);
os08a20_write_register(ViPipe, 0x350f, 0x00);
os08a20_write_register(ViPipe, 0x3600, 0x00);
os08a20_write_register(ViPipe, 0x3603, 0x2c);
os08a20_write_register(ViPipe, 0x3605, 0x50);
os08a20_write_register(ViPipe, 0x3609, 0xb5);
os08a20_write_register(ViPipe, 0x3610, 0x39);
os08a20_write_register(ViPipe, 0x360c, 0x01);
os08a20_write_register(ViPipe, 0x3628, 0xa4);
os08a20_write_register(ViPipe, 0x362d, 0x10);
os08a20_write_register(ViPipe, 0x3660, 0x42);
os08a20_write_register(ViPipe, 0x3661, 0x07);
os08a20_write_register(ViPipe, 0x3662, 0x00);
os08a20_write_register(ViPipe, 0x3663, 0x28);
os08a20_write_register(ViPipe, 0x3664, 0x0d);
os08a20_write_register(ViPipe, 0x366a, 0x38);
os08a20_write_register(ViPipe, 0x366b, 0xa0);
os08a20_write_register(ViPipe, 0x366d, 0x00);
os08a20_write_register(ViPipe, 0x366e, 0x00);
os08a20_write_register(ViPipe, 0x3680, 0x00);
os08a20_write_register(ViPipe, 0x36c0, 0x00);
os08a20_write_register(ViPipe, 0x3701, 0x02);
os08a20_write_register(ViPipe, 0x373b, 0x02);
os08a20_write_register(ViPipe, 0x373c, 0x02);
os08a20_write_register(ViPipe, 0x3736, 0x02);
os08a20_write_register(ViPipe, 0x3737, 0x02);
os08a20_write_register(ViPipe, 0x3705, 0x00);
os08a20_write_register(ViPipe, 0x3706, 0x39);
os08a20_write_register(ViPipe, 0x370a, 0x00);
os08a20_write_register(ViPipe, 0x370b, 0x98);
os08a20_write_register(ViPipe, 0x3709, 0x49);
os08a20_write_register(ViPipe, 0x3714, 0x21);
os08a20_write_register(ViPipe, 0x371c, 0x00);
os08a20_write_register(ViPipe, 0x371d, 0x08);
os08a20_write_register(ViPipe, 0x3740, 0x1b);
os08a20_write_register(ViPipe, 0x3741, 0x04);
os08a20_write_register(ViPipe, 0x375e, 0x0b);
os08a20_write_register(ViPipe, 0x3760, 0x10);
os08a20_write_register(ViPipe, 0x3776, 0x10);
os08a20_write_register(ViPipe, 0x3781, 0x02);
os08a20_write_register(ViPipe, 0x3782, 0x04);
os08a20_write_register(ViPipe, 0x3783, 0x02);
os08a20_write_register(ViPipe, 0x3784, 0x08);
os08a20_write_register(ViPipe, 0x3785, 0x08);
os08a20_write_register(ViPipe, 0x3788, 0x01);
os08a20_write_register(ViPipe, 0x3789, 0x01);
os08a20_write_register(ViPipe, 0x3797, 0x04);
os08a20_write_register(ViPipe, 0x3762, 0x11);
os08a20_write_register(ViPipe, 0x3800, 0x00);
os08a20_write_register(ViPipe, 0x3801, 0x00);
os08a20_write_register(ViPipe, 0x3802, 0x00);
os08a20_write_register(ViPipe, 0x3803, 0x0c);
os08a20_write_register(ViPipe, 0x3804, 0x0e);
os08a20_write_register(ViPipe, 0x3805, 0xff);
os08a20_write_register(ViPipe, 0x3806, 0x08);
os08a20_write_register(ViPipe, 0x3807, 0x6f);
os08a20_write_register(ViPipe, 0x3808, 0x0a);
os08a20_write_register(ViPipe, 0x3809, 0x20);
os08a20_write_register(ViPipe, 0x380a, 0x07);
os08a20_write_register(ViPipe, 0x380b, 0x98);
os08a20_write_register(ViPipe, 0x380c, 0x04);
os08a20_write_register(ViPipe, 0x380d, 0x0c);
os08a20_write_register(ViPipe, 0x380e, 0x09);
os08a20_write_register(ViPipe, 0x380f, 0x0a);
os08a20_write_register(ViPipe, 0x3813, 0x10);
os08a20_write_register(ViPipe, 0x3814, 0x01);
os08a20_write_register(ViPipe, 0x3815, 0x01);
os08a20_write_register(ViPipe, 0x3816, 0x01);
os08a20_write_register(ViPipe, 0x3817, 0x01);
os08a20_write_register(ViPipe, 0x381c, 0x08);
os08a20_write_register(ViPipe, 0x3820, 0x00);
os08a20_write_register(ViPipe, 0x3821, 0x24);
os08a20_write_register(ViPipe, 0x3823, 0x08);
os08a20_write_register(ViPipe, 0x3826, 0x00);
os08a20_write_register(ViPipe, 0x3827, 0x08);
os08a20_write_register(ViPipe, 0x382d, 0x08);
os08a20_write_register(ViPipe, 0x3832, 0x02);
os08a20_write_register(ViPipe, 0x3833, 0x01);
os08a20_write_register(ViPipe, 0x383c, 0x48);
os08a20_write_register(ViPipe, 0x383d, 0xff);
os08a20_write_register(ViPipe, 0x3d85, 0x0b);
os08a20_write_register(ViPipe, 0x3d84, 0x40);
os08a20_write_register(ViPipe, 0x3d8c, 0x63);
os08a20_write_register(ViPipe, 0x3d8d, 0xd7);
os08a20_write_register(ViPipe, 0x4000, 0xf8);
os08a20_write_register(ViPipe, 0x4001, 0x2b);
os08a20_write_register(ViPipe, 0x4004, 0x00);
os08a20_write_register(ViPipe, 0x4005, 0x40);
os08a20_write_register(ViPipe, 0x400a, 0x01);
os08a20_write_register(ViPipe, 0x400f, 0xa0);
os08a20_write_register(ViPipe, 0x4010, 0x12);
os08a20_write_register(ViPipe, 0x4018, 0x00);
os08a20_write_register(ViPipe, 0x4008, 0x02);
os08a20_write_register(ViPipe, 0x4009, 0x0d);
os08a20_write_register(ViPipe, 0x401a, 0x58);
os08a20_write_register(ViPipe, 0x4050, 0x00);
os08a20_write_register(ViPipe, 0x4051, 0x01);
os08a20_write_register(ViPipe, 0x4028, 0x2f);
os08a20_write_register(ViPipe, 0x4052, 0x00);
os08a20_write_register(ViPipe, 0x4053, 0x80);
os08a20_write_register(ViPipe, 0x4054, 0x00);
os08a20_write_register(ViPipe, 0x4055, 0x80);
os08a20_write_register(ViPipe, 0x4056, 0x00);
os08a20_write_register(ViPipe, 0x4057, 0x80);
os08a20_write_register(ViPipe, 0x4058, 0x00);
os08a20_write_register(ViPipe, 0x4059, 0x80);
os08a20_write_register(ViPipe, 0x430b, 0xff);
os08a20_write_register(ViPipe, 0x430c, 0xff);
os08a20_write_register(ViPipe, 0x430d, 0x00);
os08a20_write_register(ViPipe, 0x430e, 0x00);
os08a20_write_register(ViPipe, 0x4501, 0x18);
os08a20_write_register(ViPipe, 0x4502, 0x00);
os08a20_write_register(ViPipe, 0x4643, 0x00);
os08a20_write_register(ViPipe, 0x4640, 0x01);
os08a20_write_register(ViPipe, 0x4641, 0x04);
os08a20_write_register(ViPipe, 0x4800, 0x64);
os08a20_write_register(ViPipe, 0x4809, 0x2b);
os08a20_write_register(ViPipe, 0x4813, 0x98);
os08a20_write_register(ViPipe, 0x4817, 0x04);
os08a20_write_register(ViPipe, 0x4833, 0x18);
os08a20_write_register(ViPipe, 0x4837, 0x0b);
os08a20_write_register(ViPipe, 0x483b, 0x00);
os08a20_write_register(ViPipe, 0x484b, 0x03);
os08a20_write_register(ViPipe, 0x4850, 0x7c);
os08a20_write_register(ViPipe, 0x4852, 0x06);
os08a20_write_register(ViPipe, 0x4856, 0x58);
os08a20_write_register(ViPipe, 0x4857, 0xaa);
os08a20_write_register(ViPipe, 0x4862, 0x0a);
os08a20_write_register(ViPipe, 0x4869, 0x18);
os08a20_write_register(ViPipe, 0x486a, 0xaa);
os08a20_write_register(ViPipe, 0x486e, 0x07);
os08a20_write_register(ViPipe, 0x486f, 0x55);
os08a20_write_register(ViPipe, 0x4875, 0xf0);
os08a20_write_register(ViPipe, 0x5000, 0x89);
os08a20_write_register(ViPipe, 0x5001, 0x42);
os08a20_write_register(ViPipe, 0x5004, 0x40);
os08a20_write_register(ViPipe, 0x5005, 0x00);
os08a20_write_register(ViPipe, 0x5180, 0x00);
os08a20_write_register(ViPipe, 0x5181, 0x10);
os08a20_write_register(ViPipe, 0x580b, 0x03);
os08a20_write_register(ViPipe, 0x4d00, 0x03);
os08a20_write_register(ViPipe, 0x4d01, 0xc9);
os08a20_write_register(ViPipe, 0x4d02, 0xbc);
os08a20_write_register(ViPipe, 0x4d03, 0xc6);
os08a20_write_register(ViPipe, 0x4d04, 0x4a);
os08a20_write_register(ViPipe, 0x4d05, 0x25);
os08a20_write_register(ViPipe, 0x4700, 0x2b);
os08a20_write_register(ViPipe, 0x4e00, 0x2b);
os08a20_write_register(ViPipe, 0x3501, 0x08);
os08a20_write_register(ViPipe, 0x3502, 0xe1);
os08a20_write_register(ViPipe, 0x3511, 0x00);
os08a20_write_register(ViPipe, 0x3512, 0x20);
os08a20_write_register(ViPipe, 0x3833, 0x01);
os08a20_write_register(ViPipe, 0x0305, 0x57);
os08a20_write_register(ViPipe, 0x0325, 0x46);
os08a20_write_register(ViPipe, 0x380e, 0x09);
os08a20_write_register(ViPipe, 0x380f, 0x2a);
os08a20_write_register(ViPipe, 0x4028, 0x4f);
os08a20_write_register(ViPipe, 0x4029, 0x1f);
os08a20_write_register(ViPipe, 0x402a, 0x7f);
os08a20_write_register(ViPipe, 0x402b, 0x01);
os08a20_default_reg_init(ViPipe);
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
os08a20_write_register(ViPipe, 0x0100, 0x01); /* standby */
delay_ms(50);
printf("===Os08a20 sensor 1944P30fps 10bit 2to1 WDR(60fps->30fps) init success!=====\n");
}

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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_ov4689.a
TARGET_SO = $(MW_LIB)/libsns_ov4689.so
EXTRA_CFLAGS = $(INCS) $(PROJ_CFLAGS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@)
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@)
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

1034
middleware/v2/component/isp/sensor/cv180x/ov_ov4689/ov4689_cmos.c Normal file
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95
middleware/v2/component/isp/sensor/cv180x/ov_ov4689/ov4689_cmos_ex.h Normal file
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#ifndef __OV4689_CMOS_EX_H_
#define __OV4689_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
enum ov4689_linear_regs_e {
LINEAR_HOLD_START = 0,
LINEAR_EXP_0,
LINEAR_EXP_1,
LINEAR_EXP_2,
LINEAR_AGAIN_0,
LINEAR_AGAIN_1,
LINEAR_AGAIN_2,
LINEAR_DGAIN_0,
LINEAR_DGAIN_1,
LINEAR_VTS_0,
LINEAR_VTS_1,
LINEAR_HOLD_END,
LINEAR_LAUNCH_0,
LINEAR_LAUNCH_1,
LINEAR_REGS_NUM
};
typedef enum _OV4689_MODE_E {
OV4689_MODE_2688X1520P30 = 0,
OV4689_MODE_LINEAR_NUM,
OV4689_MODE_NUM
} OV4689_MODE_E;
typedef struct _OV4689_STATE_S {
CVI_U32 u32Sexp_MAX;
} OV4689_STATE_S;
typedef struct _OV4689_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
CVI_U16 u16L2sOffset;
CVI_U16 u16TopBoundary;
CVI_U16 u16BotBoundary;
SNS_ATTR_S stExp[2];
SNS_ATTR_LARGE_S stAgain[2];
SNS_ATTR_LARGE_S stDgain[2];
CVI_U32 u32L2S_offset;
CVI_U32 u32IspResTime;
CVI_U32 u32HdrMargin;
char name[64];
} OV4689_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastOv4689[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunOv4689_BusInfo[];
extern CVI_U16 g_au16Ov4689_GainMode[];
extern CVI_U16 g_au16Ov4689_UseHwSync[VI_MAX_PIPE_NUM];
extern CVI_U8 ov4689_i2c_addr;
extern const CVI_U32 ov4689_addr_byte;
extern const CVI_U32 ov4689_data_byte;
extern void ov4689_init(VI_PIPE ViPipe);
extern void ov4689_exit(VI_PIPE ViPipe);
extern void ov4689_standby(VI_PIPE ViPipe);
extern void ov4689_restart(VI_PIPE ViPipe);
extern int ov4689_write_register(VI_PIPE ViPipe, int addr, int data);
extern int ov4689_read_register(VI_PIPE ViPipe, int addr);
extern void ov4689_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int ov4689_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OV4689_CMOS_EX_H_ */

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middleware/v2/component/isp/sensor/cv180x/ov_ov4689/ov4689_cmos_param.h Normal file
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#ifndef __OV4689_CMOS_PARAM_H_
#define __OV4689_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "ov4689_cmos_ex.h"
static const OV4689_MODE_S g_astOv4689_mode[OV4689_MODE_NUM] = {
[OV4689_MODE_2688X1520P30] = {
.name = "2688x1520p30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 2688,
.u32Height = 1520,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 2688,
.u32Height = 1520,
},
.stMaxSize = {
.u32Width = 2688,
.u32Height = 1520,
},
},
.f32MaxFps = 30,
.f32MinFps = 0.711, /* 0x4e2 * 30 / 0xFFFF */
.u32HtsDef = 2584,
.u32VtsDef = 1554,
.stExp[0] = {
.u16Min = 4,
.u16Max = 1554 - 4,
.u16Def = 400,
.u16Step = 1,
},
.stAgain[0] = {
.u32Min = 1024,
.u32Max = 16320,
.u32Def = 1024,
.u32Step = 1,
},
.stDgain[0] = {
.u32Min = 1024,
.u32Max = 16320,
.u32Def = 1024,
.u32Step = 1,
},
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {60, 60, 60, 60, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1039, 1039, 1039, 1039
#endif
},
.stAuto = {
{60, 60, 60, 60, 60, 60, 60, 60, /*8*/60, 60, 60, 60, 60, 60, 60, 60},
{60, 60, 60, 60, 60, 60, 60, 60, /*8*/60, 60, 60, 60, 60, 60, 60, 60},
{60, 60, 60, 60, 60, 60, 60, 60, /*8*/60, 60, 60, 60, 60, 60, 60, 60},
{60, 60, 60, 60, 60, 60, 60, 60, /*8*/60, 60, 60, 60, 60, 60, 60, 60},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1039, 1039, 1039, 1039, 1039, 1039, 1039, 1039,
/*8*/1039, 1039, 1039, 1039, 1204, 1039, 1039, 1039},
{1039, 1039, 1039, 1039, 1039, 1039, 1039, 1039,
/*8*/1039, 1039, 1039, 1039, 1204, 1039, 1039, 1039},
{1039, 1039, 1039, 1039, 1039, 1039, 1039, 1039,
/*8*/1039, 1039, 1039, 1039, 1204, 1039, 1039, 1039},
{1039, 1039, 1039, 1039, 1039, 1039, 1039, 1039,
/*8*/1039, 1039, 1039, 1039, 1204, 1039, 1039, 1039},
#endif
},
},
};
struct combo_dev_attr_s ov4689_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_400M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {0, 1, 2, -1, -1},
.pn_swap = {0, 0, 0, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_24M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OV4689_CMOS_PARAM_H_ */

509
middleware/v2/component/isp/sensor/cv180x/ov_ov4689/ov4689_sensor_ctl.c Normal file
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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "ov4689_cmos_ex.h"
static void ov4689_linear_1520p30_init(VI_PIPE ViPipe);
CVI_U8 ov4689_i2c_addr = 0x36; /* I2C Address of OV4689 */
const CVI_U32 ov4689_addr_byte = 2;
const CVI_U32 ov4689_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int ov4689_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunOv4689_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, ov4689_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int ov4689_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int ov4689_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (ov4689_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, ov4689_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return 0;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, ov4689_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return 0;
}
// pack read back data
data = 0;
if (ov4689_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int ov4689_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (ov4689_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (ov4689_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, ov4689_addr_byte + ov4689_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void ov4689_standby(VI_PIPE ViPipe)
{
ov4689_write_register(ViPipe, 0x0100, 0x00); /* STANDBY */
}
void ov4689_restart(VI_PIPE ViPipe)
{
ov4689_write_register(ViPipe, 0x0100, 0x01); /* standby */
}
void ov4689_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
CVI_U32 start = 1;
CVI_U32 end = g_pastOv4689[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum - 3;
for (i = start; i < end; i++) {
ov4689_write_register(ViPipe,
g_pastOv4689[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastOv4689[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
#define OV4689_FLIP 0x3820
#define OV4689_MIRROR 0x3821
void ov4689_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 flip, mirror;
flip = ov4689_read_register(ViPipe, OV4689_FLIP);
mirror = ov4689_read_register(ViPipe, OV4689_MIRROR);
flip &= ~(0x3 << 1);
mirror &= ~(0x3 << 1);
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
mirror |= 0x3 << 1;
break;
case ISP_SNS_FLIP:
flip |= 0x3 << 1;
break;
case ISP_SNS_MIRROR_FLIP:
flip |= 0x3 << 1;
mirror |= 0x3 << 1;
break;
default:
return;
}
ov4689_write_register(ViPipe, OV4689_FLIP, flip);
ov4689_write_register(ViPipe, OV4689_MIRROR, mirror);
}
#define OV4689_CHIP_ID_ADDR_H 0x300A
#define OV4689_CHIP_ID_ADDR_L 0x300B
#define OV4689_CHIP_ID 0x4688
int ov4689_probe(VI_PIPE ViPipe)
{
int nVal, nVal2;
usleep(1000);
if (ov4689_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = ov4689_read_register(ViPipe, OV4689_CHIP_ID_ADDR_H);
nVal2 = ov4689_read_register(ViPipe, OV4689_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | (nVal2 & 0xFF)) != OV4689_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void ov4689_init(VI_PIPE ViPipe)
{
ov4689_i2c_init(ViPipe);
delay_ms(10);
ov4689_linear_1520p30_init(ViPipe);
g_pastOv4689[ViPipe]->bInit = CVI_TRUE;
}
void ov4689_exit(VI_PIPE ViPipe)
{
ov4689_i2c_exit(ViPipe);
}
/* 1080P30 */
static void ov4689_linear_1520p30_init(VI_PIPE ViPipe)
{
ov4689_write_register(ViPipe, 0x0103, 0x01);
ov4689_write_register(ViPipe, 0x3638, 0x00);
ov4689_write_register(ViPipe, 0x0300, 0x00);
ov4689_write_register(ViPipe, 0x0302, 0x2a);
ov4689_write_register(ViPipe, 0x0303, 0x00);
ov4689_write_register(ViPipe, 0x0304, 0x03);
ov4689_write_register(ViPipe, 0x030b, 0x00);
ov4689_write_register(ViPipe, 0x030d, 0x1e);
ov4689_write_register(ViPipe, 0x030e, 0x04);
ov4689_write_register(ViPipe, 0x030f, 0x01);
ov4689_write_register(ViPipe, 0x0312, 0x01);
ov4689_write_register(ViPipe, 0x031e, 0x00);
ov4689_write_register(ViPipe, 0x3000, 0x20);
ov4689_write_register(ViPipe, 0x3002, 0x00);
ov4689_write_register(ViPipe, 0x3018, 0x32);
ov4689_write_register(ViPipe, 0x3020, 0x93);
ov4689_write_register(ViPipe, 0x3021, 0x03);
ov4689_write_register(ViPipe, 0x3022, 0x01);
ov4689_write_register(ViPipe, 0x3031, 0x0a);
ov4689_write_register(ViPipe, 0x303f, 0x0c);
ov4689_write_register(ViPipe, 0x3305, 0xf1);
ov4689_write_register(ViPipe, 0x3307, 0x04);
ov4689_write_register(ViPipe, 0x3309, 0x29);
ov4689_write_register(ViPipe, 0x3500, 0x00);
ov4689_write_register(ViPipe, 0x3501, 0x60);
ov4689_write_register(ViPipe, 0x3502, 0x00);
ov4689_write_register(ViPipe, 0x3503, 0x04);
ov4689_write_register(ViPipe, 0x3504, 0x00);
ov4689_write_register(ViPipe, 0x3505, 0x00);
ov4689_write_register(ViPipe, 0x3506, 0x00);
ov4689_write_register(ViPipe, 0x3507, 0x00);
ov4689_write_register(ViPipe, 0x3508, 0x00);
ov4689_write_register(ViPipe, 0x3509, 0x80);
ov4689_write_register(ViPipe, 0x350a, 0x00);
ov4689_write_register(ViPipe, 0x350b, 0x00);
ov4689_write_register(ViPipe, 0x350c, 0x00);
ov4689_write_register(ViPipe, 0x350d, 0x00);
ov4689_write_register(ViPipe, 0x350e, 0x00);
ov4689_write_register(ViPipe, 0x350f, 0x80);
ov4689_write_register(ViPipe, 0x3510, 0x00);
ov4689_write_register(ViPipe, 0x3511, 0x00);
ov4689_write_register(ViPipe, 0x3512, 0x00);
ov4689_write_register(ViPipe, 0x3513, 0x00);
ov4689_write_register(ViPipe, 0x3514, 0x00);
ov4689_write_register(ViPipe, 0x3515, 0x80);
ov4689_write_register(ViPipe, 0x3516, 0x00);
ov4689_write_register(ViPipe, 0x3517, 0x00);
ov4689_write_register(ViPipe, 0x3518, 0x00);
ov4689_write_register(ViPipe, 0x3519, 0x00);
ov4689_write_register(ViPipe, 0x351a, 0x00);
ov4689_write_register(ViPipe, 0x351b, 0x80);
ov4689_write_register(ViPipe, 0x351c, 0x00);
ov4689_write_register(ViPipe, 0x351d, 0x00);
ov4689_write_register(ViPipe, 0x351e, 0x00);
ov4689_write_register(ViPipe, 0x351f, 0x00);
ov4689_write_register(ViPipe, 0x3520, 0x00);
ov4689_write_register(ViPipe, 0x3521, 0x80);
ov4689_write_register(ViPipe, 0x3522, 0x08);
ov4689_write_register(ViPipe, 0x3524, 0x08);
ov4689_write_register(ViPipe, 0x3526, 0x08);
ov4689_write_register(ViPipe, 0x3528, 0x08);
ov4689_write_register(ViPipe, 0x352a, 0x08);
ov4689_write_register(ViPipe, 0x3602, 0x00);
ov4689_write_register(ViPipe, 0x3603, 0x40);
ov4689_write_register(ViPipe, 0x3604, 0x02);
ov4689_write_register(ViPipe, 0x3605, 0x00);
ov4689_write_register(ViPipe, 0x3606, 0x00);
ov4689_write_register(ViPipe, 0x3607, 0x00);
ov4689_write_register(ViPipe, 0x3609, 0x12);
ov4689_write_register(ViPipe, 0x360a, 0x40);
ov4689_write_register(ViPipe, 0x360c, 0x08);
ov4689_write_register(ViPipe, 0x360f, 0xe5);
ov4689_write_register(ViPipe, 0x3608, 0x8f);
ov4689_write_register(ViPipe, 0x3611, 0x00);
ov4689_write_register(ViPipe, 0x3613, 0xf7);
ov4689_write_register(ViPipe, 0x3616, 0x58);
ov4689_write_register(ViPipe, 0x3619, 0x99);
ov4689_write_register(ViPipe, 0x361b, 0x60);
ov4689_write_register(ViPipe, 0x361c, 0x7a);
ov4689_write_register(ViPipe, 0x361e, 0x79);
ov4689_write_register(ViPipe, 0x361f, 0x02);
ov4689_write_register(ViPipe, 0x3632, 0x00);
ov4689_write_register(ViPipe, 0x3633, 0x10);
ov4689_write_register(ViPipe, 0x3634, 0x10);
ov4689_write_register(ViPipe, 0x3635, 0x10);
ov4689_write_register(ViPipe, 0x3636, 0x15);
ov4689_write_register(ViPipe, 0x3646, 0x86);
ov4689_write_register(ViPipe, 0x364a, 0x0b);
ov4689_write_register(ViPipe, 0x3700, 0x17);
ov4689_write_register(ViPipe, 0x3701, 0x22);
ov4689_write_register(ViPipe, 0x3703, 0x10);
ov4689_write_register(ViPipe, 0x370a, 0x37);
ov4689_write_register(ViPipe, 0x3705, 0x00);
ov4689_write_register(ViPipe, 0x3706, 0x63);
ov4689_write_register(ViPipe, 0x3709, 0x3c);
ov4689_write_register(ViPipe, 0x370b, 0x01);
ov4689_write_register(ViPipe, 0x370c, 0x30);
ov4689_write_register(ViPipe, 0x3710, 0x24);
ov4689_write_register(ViPipe, 0x3711, 0x0c);
ov4689_write_register(ViPipe, 0x3716, 0x00);
ov4689_write_register(ViPipe, 0x3720, 0x28);
ov4689_write_register(ViPipe, 0x3729, 0x7b);
ov4689_write_register(ViPipe, 0x372a, 0x84);
ov4689_write_register(ViPipe, 0x372b, 0xbd);
ov4689_write_register(ViPipe, 0x372c, 0xbc);
ov4689_write_register(ViPipe, 0x372e, 0x52);
ov4689_write_register(ViPipe, 0x373c, 0x0e);
ov4689_write_register(ViPipe, 0x373e, 0x33);
ov4689_write_register(ViPipe, 0x3743, 0x10);
ov4689_write_register(ViPipe, 0x3744, 0x88);
ov4689_write_register(ViPipe, 0x3745, 0xc0);
ov4689_write_register(ViPipe, 0x374a, 0x43);
ov4689_write_register(ViPipe, 0x374c, 0x00);
ov4689_write_register(ViPipe, 0x374e, 0x23);
ov4689_write_register(ViPipe, 0x3751, 0x7b);
ov4689_write_register(ViPipe, 0x3752, 0x84);
ov4689_write_register(ViPipe, 0x3753, 0xbd);
ov4689_write_register(ViPipe, 0x3754, 0xbc);
ov4689_write_register(ViPipe, 0x3756, 0x52);
ov4689_write_register(ViPipe, 0x375c, 0x00);
ov4689_write_register(ViPipe, 0x3760, 0x00);
ov4689_write_register(ViPipe, 0x3761, 0x00);
ov4689_write_register(ViPipe, 0x3762, 0x00);
ov4689_write_register(ViPipe, 0x3763, 0x00);
ov4689_write_register(ViPipe, 0x3764, 0x00);
ov4689_write_register(ViPipe, 0x3767, 0x04);
ov4689_write_register(ViPipe, 0x3768, 0x04);
ov4689_write_register(ViPipe, 0x3769, 0x08);
ov4689_write_register(ViPipe, 0x376a, 0x08);
ov4689_write_register(ViPipe, 0x376b, 0x20);
ov4689_write_register(ViPipe, 0x376c, 0x00);
ov4689_write_register(ViPipe, 0x376d, 0x00);
ov4689_write_register(ViPipe, 0x376e, 0x00);
ov4689_write_register(ViPipe, 0x3773, 0x00);
ov4689_write_register(ViPipe, 0x3774, 0x51);
ov4689_write_register(ViPipe, 0x3776, 0xbd);
ov4689_write_register(ViPipe, 0x3777, 0xbd);
ov4689_write_register(ViPipe, 0x3781, 0x18);
ov4689_write_register(ViPipe, 0x3783, 0x25);
ov4689_write_register(ViPipe, 0x3798, 0x1b);
ov4689_write_register(ViPipe, 0x3800, 0x00);
ov4689_write_register(ViPipe, 0x3801, 0x08);
ov4689_write_register(ViPipe, 0x3802, 0x00);
ov4689_write_register(ViPipe, 0x3803, 0x04);
ov4689_write_register(ViPipe, 0x3804, 0x0a);
ov4689_write_register(ViPipe, 0x3805, 0x97);
ov4689_write_register(ViPipe, 0x3806, 0x05);
ov4689_write_register(ViPipe, 0x3807, 0xfb);
ov4689_write_register(ViPipe, 0x3808, 0x0a);
ov4689_write_register(ViPipe, 0x3809, 0x80);
ov4689_write_register(ViPipe, 0x380a, 0x05);
ov4689_write_register(ViPipe, 0x380b, 0xf0);
ov4689_write_register(ViPipe, 0x380c, 0x0A);
ov4689_write_register(ViPipe, 0x380d, 0x18);
ov4689_write_register(ViPipe, 0x380e, 0x06);
ov4689_write_register(ViPipe, 0x380f, 0x12);
ov4689_write_register(ViPipe, 0x3810, 0x00);
ov4689_write_register(ViPipe, 0x3811, 0x08);
ov4689_write_register(ViPipe, 0x3812, 0x00);
ov4689_write_register(ViPipe, 0x3813, 0x04);
ov4689_write_register(ViPipe, 0x3814, 0x01);
ov4689_write_register(ViPipe, 0x3815, 0x01);
ov4689_write_register(ViPipe, 0x3819, 0x01);
ov4689_write_register(ViPipe, 0x3820, 0x00);
ov4689_write_register(ViPipe, 0x3821, 0x00);
ov4689_write_register(ViPipe, 0x3829, 0x00);
ov4689_write_register(ViPipe, 0x382a, 0x01);
ov4689_write_register(ViPipe, 0x382b, 0x01);
ov4689_write_register(ViPipe, 0x382d, 0x7f);
ov4689_write_register(ViPipe, 0x3830, 0x04);
ov4689_write_register(ViPipe, 0x3836, 0x01);
ov4689_write_register(ViPipe, 0x3837, 0x00);
ov4689_write_register(ViPipe, 0x3841, 0x02);
ov4689_write_register(ViPipe, 0x3846, 0x08);
ov4689_write_register(ViPipe, 0x3847, 0x07);
ov4689_write_register(ViPipe, 0x3d85, 0x36);
ov4689_write_register(ViPipe, 0x3d8c, 0x71);
ov4689_write_register(ViPipe, 0x3d8d, 0xcb);
ov4689_write_register(ViPipe, 0x3f0a, 0x00);
ov4689_write_register(ViPipe, 0x4000, 0xf1);
ov4689_write_register(ViPipe, 0x4001, 0x40);
ov4689_write_register(ViPipe, 0x4002, 0x04);
ov4689_write_register(ViPipe, 0x4003, 0x14);
ov4689_write_register(ViPipe, 0x400e, 0x00);
ov4689_write_register(ViPipe, 0x4011, 0x00);
ov4689_write_register(ViPipe, 0x401a, 0x00);
ov4689_write_register(ViPipe, 0x401b, 0x00);
ov4689_write_register(ViPipe, 0x401c, 0x00);
ov4689_write_register(ViPipe, 0x401d, 0x00);
ov4689_write_register(ViPipe, 0x401f, 0x00);
ov4689_write_register(ViPipe, 0x4020, 0x00);
ov4689_write_register(ViPipe, 0x4021, 0x10);
ov4689_write_register(ViPipe, 0x4022, 0x07);
ov4689_write_register(ViPipe, 0x4023, 0xcf);
ov4689_write_register(ViPipe, 0x4024, 0x09);
ov4689_write_register(ViPipe, 0x4025, 0x60);
ov4689_write_register(ViPipe, 0x4026, 0x09);
ov4689_write_register(ViPipe, 0x4027, 0x6f);
ov4689_write_register(ViPipe, 0x4028, 0x00);
ov4689_write_register(ViPipe, 0x4029, 0x02);
ov4689_write_register(ViPipe, 0x402a, 0x06);
ov4689_write_register(ViPipe, 0x402b, 0x04);
ov4689_write_register(ViPipe, 0x402c, 0x02);
ov4689_write_register(ViPipe, 0x402d, 0x02);
ov4689_write_register(ViPipe, 0x402e, 0x0e);
ov4689_write_register(ViPipe, 0x402f, 0x04);
ov4689_write_register(ViPipe, 0x4302, 0xff);
ov4689_write_register(ViPipe, 0x4303, 0xff);
ov4689_write_register(ViPipe, 0x4304, 0x00);
ov4689_write_register(ViPipe, 0x4305, 0x00);
ov4689_write_register(ViPipe, 0x4306, 0x00);
ov4689_write_register(ViPipe, 0x4308, 0x02);
ov4689_write_register(ViPipe, 0x4500, 0x6c);
ov4689_write_register(ViPipe, 0x4501, 0xc4);
ov4689_write_register(ViPipe, 0x4502, 0x40);
ov4689_write_register(ViPipe, 0x4503, 0x01);
ov4689_write_register(ViPipe, 0x4601, 0xA7);
ov4689_write_register(ViPipe, 0x4800, 0x04);
ov4689_write_register(ViPipe, 0x4813, 0x08);
ov4689_write_register(ViPipe, 0x481f, 0x40);
ov4689_write_register(ViPipe, 0x4829, 0x78);
ov4689_write_register(ViPipe, 0x4837, 0x10);
ov4689_write_register(ViPipe, 0x4b00, 0x2a);
ov4689_write_register(ViPipe, 0x4b0d, 0x00);
ov4689_write_register(ViPipe, 0x4d00, 0x04);
ov4689_write_register(ViPipe, 0x4d01, 0x42);
ov4689_write_register(ViPipe, 0x4d02, 0xd1);
ov4689_write_register(ViPipe, 0x4d03, 0x93);
ov4689_write_register(ViPipe, 0x4d04, 0xf5);
ov4689_write_register(ViPipe, 0x4d05, 0xc1);
ov4689_write_register(ViPipe, 0x5000, 0xf3);
ov4689_write_register(ViPipe, 0x5001, 0x11);
ov4689_write_register(ViPipe, 0x5004, 0x00);
ov4689_write_register(ViPipe, 0x500a, 0x00);
ov4689_write_register(ViPipe, 0x500b, 0x00);
ov4689_write_register(ViPipe, 0x5032, 0x00);
ov4689_write_register(ViPipe, 0x5040, 0x00);
ov4689_write_register(ViPipe, 0x5050, 0x0c);
ov4689_write_register(ViPipe, 0x5500, 0x00);
ov4689_write_register(ViPipe, 0x5501, 0x10);
ov4689_write_register(ViPipe, 0x5502, 0x01);
ov4689_write_register(ViPipe, 0x5503, 0x0f);
ov4689_write_register(ViPipe, 0x8000, 0x00);
ov4689_write_register(ViPipe, 0x8001, 0x00);
ov4689_write_register(ViPipe, 0x8002, 0x00);
ov4689_write_register(ViPipe, 0x8003, 0x00);
ov4689_write_register(ViPipe, 0x8004, 0x00);
ov4689_write_register(ViPipe, 0x8005, 0x00);
ov4689_write_register(ViPipe, 0x8006, 0x00);
ov4689_write_register(ViPipe, 0x8007, 0x00);
ov4689_write_register(ViPipe, 0x8008, 0x00);
ov4689_write_register(ViPipe, 0x3638, 0x00);
ov4689_default_reg_init(ViPipe);
ov4689_write_register(ViPipe, 0x0100, 0x01);
delay_ms(100);
printf("ViPipe:%d,===OV4689 1520P 30fps 10bit LINE Init OK!===\n", ViPipe);
}

36
middleware/v2/component/isp/sensor/cv180x/ov_ov6211/Makefile Normal file
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@ -0,0 +1,36 @@
SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_ov6211.a
TARGET_SO = $(MW_LIB)/libsns_ov6211.so
EXTRA_CFLAGS = $(INCS) $(PROJ_CFLAGS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@)
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@)
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

966
middleware/v2/component/isp/sensor/cv180x/ov_ov6211/ov6211_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "ov6211_cmos_ex.h"
#include "ov6211_cmos_param.h"
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define OV6211_ID 6211
#define OV6211_I2C_ADDR_1 0x60
#define OV6211_I2C_ADDR_2 0x70
#define OV6211_I2C_ADDR_IS_VALID(addr) ((addr) == OV6211_I2C_ADDR_1 || (addr) == OV6211_I2C_ADDR_2)
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_STATE_S *g_pastOv6211[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define OV6211_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastOv6211[dev])
#define OV6211_SENSOR_SET_CTX(dev, pstCtx) (g_pastOv6211[dev] = pstCtx)
#define OV6211_SENSOR_RESET_CTX(dev) (g_pastOv6211[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunOv6211_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
CVI_U16 g_au16Ov6211_GainMode[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Ov6211_L2SMode[VI_MAX_PIPE_NUM] = {0};
ISP_SNS_MIRRORFLIP_TYPE_E g_aeOv6211_MirrorFip[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
****************************************************************************/
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Ov6211 Lines Range*****/
#define OV6211_FULL_LINES_MAX (0xFFFF)
/*****Ov6211 Register Address*****/
#define OV6211_EXP_ADDR 0x3500
#define OV6211_AGAIN_ADDR 0x350a
#define OV6211_VTS_ADDR 0x380E
#define OV6211_RES_IS_400P(w, h) ((w) == 400 && (h) == 400)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
const OV6211_MODE_S *pstMode;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astOv6211_mode[pstSnsState->u8ImgMode];
#if 0
memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S));
#endif
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = OV6211_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_DB;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
pstAeSnsDft->u32SnsStableFrame = 0;
#if 0
pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0;
pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0;
pstAeSnsDft->bAERouteExValid = CVI_FALSE;
pstAeSnsDft->stAERouteAttr.u32TotalNum = 0;
pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0;
#endif
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u16Max;
pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u16Min;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u16Max;
pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u16Min;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_astOv6211_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_astOv6211_mode[pstSnsState->u8ImgMode].f32MaxFps;
f32MinFps = g_astOv6211_mode[pstSnsState->u8ImgMode].f32MinFps;
switch (pstSnsState->u8ImgMode) {
case OV6211_MODE_400X400P120:
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > OV6211_FULL_LINES_MAX) ? OV6211_FULL_LINES_MAX : u32VMAX;
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode);
return CVI_FAILURE;
}
pstSnsState->u32FLStd = u32VMAX;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = (u32VMAX & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32TmpIntTime, u32MinTime, u32MaxTime;
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
/* linear exposure reg range:
* min : 1
* max : vts - 4
* step : 1
*/
u32MinTime = 1;
u32MaxTime = pstSnsState->au32FL[0] - 4;
u32TmpIntTime = (u32IntTime[0] > u32MaxTime) ? u32MaxTime : u32IntTime[0];
u32TmpIntTime = (u32TmpIntTime < u32MinTime) ? u32MinTime : u32TmpIntTime;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((u32TmpIntTime & 0xF000) >> 12);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = ((u32TmpIntTime & 0x000F) << 4);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
typedef struct gain_tbl_info_s {
CVI_U16 gainMax;
CVI_U16 idxBase;
CVI_U8 regGain;
CVI_U8 regGainFineBase;
CVI_U8 regGainFineStep;
} gain_tbl_info_s;
static struct gain_tbl_info_s AgainInfo[15] = {
{
.gainMax = 1984,
.idxBase = 0,
.regGain = 0x01,
.regGainFineBase = 0x00,
.regGainFineStep = 1,
},
{
.gainMax = 2944,
.idxBase = 16,
.regGain = 0x02,
.regGainFineBase = 0x00,
.regGainFineStep = 2,
},
{
.gainMax = 3968,
.idxBase = 24,
.regGain = 0x03,
.regGainFineBase = 0x00,
.regGainFineStep = 2,
},
{
.gainMax = 4864,
.idxBase = 32,
.regGain = 0x04,
.regGainFineBase = 0x00,
.regGainFineStep = 4,
},
{
.gainMax = 5888,
.idxBase = 36,
.regGain = 0x05,
.regGainFineBase = 0x00,
.regGainFineStep = 4,
},
{
.gainMax = 6912,
.idxBase = 40,
.regGain = 0x06,
.regGainFineBase = 0x00,
.regGainFineStep = 4,
},
{
.gainMax = 7936,
.idxBase = 44,
.regGain = 0x07,
.regGainFineBase = 0x00,
.regGainFineStep = 4,
},
{
.gainMax = 8704,
.idxBase = 48,
.regGain = 0x08,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 9728,
.idxBase = 50,
.regGain = 0x09,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 10752,
.idxBase = 52,
.regGain = 0x0a,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 11776,
.idxBase = 54,
.regGain = 0x0b,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 12800,
.idxBase = 56,
.regGain = 0x0c,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 13824,
.idxBase = 58,
.regGain = 0x0d,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 14848,
.idxBase = 60,
.regGain = 0x0e,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 15872,
.idxBase = 62,
.regGain = 0x0f,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
};
static CVI_U32 Again_table[64] = {
1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792,
1856, 1920, 1984, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200,
3328, 3456, 3584, 3712, 3840, 3968, 4096, 4352, 4608, 4864, 5120, 5376, 5632,
5888, 6144, 6400, 6656, 6912, 7168, 7424, 7680, 7936, 8192, 8704, 9216, 9728,
10240, 10752, 11264, 11776, 12288, 12800, 13312, 13824, 14336, 14848, 15360,
15872
};
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
int i;
(void) ViPipe;
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
if (*pu32AgainLin >= Again_table[63]) {
*pu32AgainLin = Again_table[63];
*pu32AgainDb = 63;
return CVI_SUCCESS;
}
for (i = 1; i < 64; i++) {
if (*pu32AgainLin < Again_table[i]) {
*pu32AgainLin = Again_table[i - 1];
*pu32AgainDb = i - 1;
break;
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
(void) ViPipe;
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
*pu32DgainLin = 1024;
*pu32DgainDb = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32Again;
struct gain_tbl_info_s *info;
int i, tbl_num;
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
u32Again = pu32Again[0];
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
/* linear mode */
/* find Again register setting. */
tbl_num = sizeof(AgainInfo)/sizeof(struct gain_tbl_info_s);
for (i = tbl_num - 1; i >= 0; i--) {
info = &AgainInfo[i];
if (u32Again >= info->idxBase)
break;
}
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN0].u32Data = 0x00;
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN1].u32Data = (info->regGain & 0x0F) << 4;
u32Again = info->regGainFineBase + (u32Again - info->idxBase) * info->regGainFineStep;
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN1].u32Data |= (u32Again & 0x0F);
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
//pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
//pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
//pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
(void) ViPipe;
CMOS_CHECK_POINTER(pstAwbSnsDft);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
(void) ViPipe;
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
(void) ViPipe;
CMOS_CHECK_POINTER(pstBlc);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const OV6211_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astOv6211_mode[pstSnsState->u8ImgMode];
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsState->bSyncInit = CVI_FALSE;
switch (u8Mode) {
case WDR_MODE_NONE:
pstSnsState->u8ImgMode = OV6211_MODE_400X400P120;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astOv6211_mode[pstSnsState->u8ImgMode].u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_NONE\n");
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_FAILURE;
}
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunOv6211_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = ov6211_i2c_addr;
pstI2c_data[i].u32AddrByteNum = ov6211_addr_byte;
pstI2c_data[i].u32DataByteNum = ov6211_data_byte;
}
switch (pstSnsState->enWDRMode) {
case WDR_MODE_NONE:
pstI2c_data[LINEAR_EXP_0].u32RegAddr = OV6211_EXP_ADDR;
pstI2c_data[LINEAR_EXP_1].u32RegAddr = OV6211_EXP_ADDR + 1;
pstI2c_data[LINEAR_EXP_2].u32RegAddr = OV6211_EXP_ADDR + 2;
pstI2c_data[LINEAR_AGAIN0].u32RegAddr = OV6211_AGAIN_ADDR;
pstI2c_data[LINEAR_AGAIN1].u32RegAddr = OV6211_AGAIN_ADDR + 1;
pstI2c_data[LINEAR_VTS_0].u32RegAddr = OV6211_VTS_ADDR;
pstI2c_data[LINEAR_VTS_1].u32RegAddr = OV6211_VTS_ADDR + 1;
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
/* check update isp crop or not */
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 120) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (OV6211_RES_IS_400P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = OV6211_MODE_400X400P120;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
if (pstSnsState->bInit == CVI_TRUE && g_aeOv6211_MirrorFip[ViPipe] != eSnsMirrorFlip) {
ov6211_mirror_flip(ViPipe, eSnsMirrorFlip);
g_aeOv6211_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = OV6211_MODE_400X400P120;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astOv6211_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[0] = g_astOv6211_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[1] = g_astOv6211_mode[pstSnsState->u8ImgMode].u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV6211_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &ov6211_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_astOv6211_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astOv6211_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &ov6211_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = ov6211_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = ov6211_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (OV6211_I2C_ADDR_IS_VALID(s32I2cAddr))
ov6211_i2c_addr = s32I2cAddr;
}
static CVI_S32 ov6211_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunOv6211_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
OV6211_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
OV6211_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
OV6211_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
OV6211_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = OV6211_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, OV6211_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, OV6211_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, OV6211_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Ov6211_GainMode[ViPipe] = pstInitAttr->enGainMode;
g_au16Ov6211_L2SMode[ViPipe] = pstInitAttr->enL2SMode;
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return ov6211_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsOv6211_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = ov6211_standby,
.pfnRestart = ov6211_restart,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnWriteReg = ov6211_write_register,
.pfnReadReg = ov6211_read_register,
.pfnSetBusInfo = ov6211_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = sensor_probe,
};

86
middleware/v2/component/isp/sensor/cv180x/ov_ov6211/ov6211_cmos_ex.h Normal file
View File

@ -0,0 +1,86 @@
#ifndef __OV6211_CMOS_EX_H_
#define __OV6211_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
enum ov6211_linear_regs_e {
LINEAR_EXP_0 = 0,
LINEAR_EXP_1,
LINEAR_EXP_2,
LINEAR_AGAIN0,
LINEAR_AGAIN1,
LINEAR_VTS_0,
LINEAR_VTS_1,
LINEAR_REGS_NUM
};
typedef enum _OV6211_MODE_E {
OV6211_MODE_400X400P120 = 0,
OV6211_MODE_LINEAR_NUM,
OV6211_MODE_NUM
} OV6211_MODE_E;
typedef struct _OV6211_STATE_S {
CVI_U32 u32Sexp_MAX;
} OV6211_STATE_S;
typedef struct _OV6211_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
CVI_U16 u16L2sOffset;
CVI_U16 u16TopBoundary;
CVI_U16 u16BotBoundary;
SNS_ATTR_S stExp[2];
SNS_ATTR_S stAgain[2];
SNS_ATTR_S stDgain[2];
CVI_U32 u32L2S_MAX;
char name[64];
} OV6211_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastOv6211[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunOv6211_BusInfo[];
extern CVI_U16 g_au16Ov6211_GainMode[];
extern CVI_U16 g_au16Ov6211_L2SMode[VI_MAX_PIPE_NUM];
extern CVI_U8 ov6211_i2c_addr;
extern const CVI_U32 ov6211_addr_byte;
extern const CVI_U32 ov6211_data_byte;
extern void ov6211_init(VI_PIPE ViPipe);
extern void ov6211_exit(VI_PIPE ViPipe);
extern void ov6211_standby(VI_PIPE ViPipe);
extern void ov6211_restart(VI_PIPE ViPipe);
extern int ov6211_write_register(VI_PIPE ViPipe, int addr, int data);
extern int ov6211_read_register(VI_PIPE ViPipe, int addr);
extern void ov6211_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int ov6211_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OV6211_CMOS_EX_H_ */

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#ifndef __OV6211_CMOS_PARAM_H_
#define __OV6211_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "ov6211_cmos_ex.h"
static const OV6211_MODE_S g_astOv6211_mode[OV6211_MODE_NUM] = {
[OV6211_MODE_400X400P120] = {
.name = "400X400P120",
.astImg[0] = {
.stSnsSize = {
.u32Width = 400,
.u32Height = 400,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 400,
.u32Height = 400,
},
.stMaxSize = {
.u32Width = 400,
.u32Height = 400,
},
},
.f32MaxFps = 120,
.f32MinFps = 0.80, /* 0x1b6 * 120 / 0xFFFF */
.u32HtsDef = 1522,
.u32VtsDef = 438,
.stExp[0] = {
.u16Min = 1,
.u16Max = 438 - 4,
.u16Def = 100,
.u16Step = 1,
},
.stAgain[0] = {
.u16Min = 1024,
.u16Max = 15872,
.u16Def = 1024,
.u16Step = 1,
},
.stDgain[0] = {
.u16Min = 1024,
.u16Max = 1024,
.u16Def = 1024,
.u16Step = 1,
},
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {128, 128, 128, 128, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1057, 1057, 1057, 1057
#endif
},
.stAuto = {
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{128, 128, 128, 128, 128, 128, 128, 128, /*8*/128, 128, 128, 128, 128, 128, 128, 128},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
{1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057,
/*8*/1057, 1057, 1057, 1057, 1057, 1057, 1057, 1057},
#endif
},
},
};
struct combo_dev_attr_s ov6211_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {1, 0, -1, -1, -1},
.pn_swap = {1, 1, 0, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
.dphy = {
.enable = 1,
.hs_settle = 8,
}
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_24M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OV6211_CMOS_PARAM_H_ */

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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "ov6211_cmos_ex.h"
static void ov6211_linear_400p120_init(VI_PIPE ViPipe);
CVI_U8 ov6211_i2c_addr = 0x60; /* I2C Address of OV6211 */
const CVI_U32 ov6211_addr_byte = 2;
const CVI_U32 ov6211_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int ov6211_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunOv6211_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, ov6211_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int ov6211_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int ov6211_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (ov6211_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, ov6211_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return 0;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, ov6211_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return 0;
}
// pack read back data
data = 0;
if (ov6211_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int ov6211_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (ov6211_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (ov6211_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, ov6211_addr_byte + ov6211_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void ov6211_standby(VI_PIPE ViPipe)
{
ov6211_write_register(ViPipe, 0x0100, 0x00); /* standby */
}
void ov6211_restart(VI_PIPE ViPipe)
{
ov6211_write_register(ViPipe, 0x0100, 0x01); /* restart */
}
void ov6211_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastOv6211[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
if (g_pastOv6211[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].bUpdate == CVI_TRUE) {
ov6211_write_register(ViPipe,
g_pastOv6211[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastOv6211[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
}
void ov6211_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 flip, mirror;
flip = ov6211_read_register(ViPipe, 0x3820);
mirror = ov6211_read_register(ViPipe, 0x3821);
flip &= ~(0x1 << 2);
mirror &= ~(0x1 << 2);
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
mirror |= 0x1 << 2;
break;
case ISP_SNS_FLIP:
flip |= 0x1 << 2;
break;
case ISP_SNS_MIRROR_FLIP:
flip |= 0x1 << 2;
mirror |= 0x1 << 2;
break;
default:
return;
}
ov6211_write_register(ViPipe, 0x3820, flip);
ov6211_write_register(ViPipe, 0x3821, mirror);
}
#define OV6211_CHIP_ID_ADDR_H 0x300A
#define OV6211_CHIP_ID_ADDR_L 0x300B
#define OV6211_CHIP_ID 0x6710
int ov6211_probe(VI_PIPE ViPipe)
{
int nVal, nVal2;
usleep(500);
if (ov6211_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
nVal = ov6211_read_register(ViPipe, OV6211_CHIP_ID_ADDR_H);
nVal2 = ov6211_read_register(ViPipe, OV6211_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | ((nVal2 & 0xFF) << 0)) != OV6211_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void ov6211_init(VI_PIPE ViPipe)
{
ov6211_i2c_init(ViPipe);
delay_ms(50);
ov6211_linear_400p120_init(ViPipe);
g_pastOv6211[ViPipe]->bInit = CVI_TRUE;
}
void ov6211_exit(VI_PIPE ViPipe)
{
ov6211_i2c_exit(ViPipe);
}
/* 1944P30 and 1944P25 */
static void ov6211_linear_400p120_init(VI_PIPE ViPipe)
{
ov6211_write_register(ViPipe, 0x0103, 0x01);
ov6211_write_register(ViPipe, 0x0100, 0x00);
ov6211_write_register(ViPipe, 0x3005, 0x00);
ov6211_write_register(ViPipe, 0x3013, 0x12);
ov6211_write_register(ViPipe, 0x3014, 0x04);
ov6211_write_register(ViPipe, 0x3016, 0x10);
ov6211_write_register(ViPipe, 0x3017, 0x00);
ov6211_write_register(ViPipe, 0x3018, 0x00);
ov6211_write_register(ViPipe, 0x301a, 0x00);
ov6211_write_register(ViPipe, 0x301b, 0x00);
ov6211_write_register(ViPipe, 0x301c, 0x00);
ov6211_write_register(ViPipe, 0x3037, 0xf0);
ov6211_write_register(ViPipe, 0x3080, 0x01);
ov6211_write_register(ViPipe, 0x3081, 0x00);
ov6211_write_register(ViPipe, 0x3082, 0x01);
ov6211_write_register(ViPipe, 0x3098, 0x04);
ov6211_write_register(ViPipe, 0x3099, 0x28);
ov6211_write_register(ViPipe, 0x309a, 0x06);
ov6211_write_register(ViPipe, 0x309b, 0x04);
ov6211_write_register(ViPipe, 0x309c, 0x00);
ov6211_write_register(ViPipe, 0x309d, 0x00);
ov6211_write_register(ViPipe, 0x309e, 0x01);
ov6211_write_register(ViPipe, 0x309f, 0x00);
ov6211_write_register(ViPipe, 0x30b0, 0x0a);
ov6211_write_register(ViPipe, 0x30b1, 0x02);
ov6211_write_register(ViPipe, 0x30b2, 0x00);
ov6211_write_register(ViPipe, 0x30b3, 0x32);
ov6211_write_register(ViPipe, 0x30b4, 0x02);
ov6211_write_register(ViPipe, 0x30b5, 0x05);
ov6211_write_register(ViPipe, 0x3106, 0xd9);
ov6211_write_register(ViPipe, 0x3500, 0x00);
ov6211_write_register(ViPipe, 0x3501, 0x1b);
ov6211_write_register(ViPipe, 0x3502, 0x20);
ov6211_write_register(ViPipe, 0x3503, 0x07);
ov6211_write_register(ViPipe, 0x3509, 0x10);
ov6211_write_register(ViPipe, 0x350b, 0x10);
ov6211_write_register(ViPipe, 0x3600, 0xfc);
ov6211_write_register(ViPipe, 0x3620, 0xb7);
ov6211_write_register(ViPipe, 0x3621, 0x05);
ov6211_write_register(ViPipe, 0x3626, 0x31);
ov6211_write_register(ViPipe, 0x3627, 0x40);
ov6211_write_register(ViPipe, 0x3632, 0xa3);
ov6211_write_register(ViPipe, 0x3633, 0x34);
ov6211_write_register(ViPipe, 0x3634, 0x40);
ov6211_write_register(ViPipe, 0x3636, 0x00);
ov6211_write_register(ViPipe, 0x3660, 0x80);
ov6211_write_register(ViPipe, 0x3662, 0x01);
ov6211_write_register(ViPipe, 0x3664, 0xf0);
ov6211_write_register(ViPipe, 0x366a, 0x10);
ov6211_write_register(ViPipe, 0x366b, 0x06);
ov6211_write_register(ViPipe, 0x3680, 0xf4);
ov6211_write_register(ViPipe, 0x3681, 0x50);
ov6211_write_register(ViPipe, 0x3682, 0x00);
ov6211_write_register(ViPipe, 0x3708, 0x20);
ov6211_write_register(ViPipe, 0x3709, 0x40);
ov6211_write_register(ViPipe, 0x370d, 0x03);
ov6211_write_register(ViPipe, 0x373b, 0x02);
ov6211_write_register(ViPipe, 0x373c, 0x08);
ov6211_write_register(ViPipe, 0x3742, 0x00);
ov6211_write_register(ViPipe, 0x3744, 0x16);
ov6211_write_register(ViPipe, 0x3745, 0x08);
ov6211_write_register(ViPipe, 0x3781, 0xfc);
ov6211_write_register(ViPipe, 0x3788, 0x00);
ov6211_write_register(ViPipe, 0x3800, 0x00);
ov6211_write_register(ViPipe, 0x3801, 0x04);
ov6211_write_register(ViPipe, 0x3802, 0x00);
ov6211_write_register(ViPipe, 0x3803, 0x04);
ov6211_write_register(ViPipe, 0x3804, 0x01);
ov6211_write_register(ViPipe, 0x3805, 0x9b);
ov6211_write_register(ViPipe, 0x3806, 0x01);
ov6211_write_register(ViPipe, 0x3807, 0x9b);
ov6211_write_register(ViPipe, 0x3808, 0x01);
ov6211_write_register(ViPipe, 0x3809, 0x90);
ov6211_write_register(ViPipe, 0x380a, 0x01);
ov6211_write_register(ViPipe, 0x380b, 0x90);
ov6211_write_register(ViPipe, 0x380c, 0x05);
ov6211_write_register(ViPipe, 0x380d, 0xf2);
ov6211_write_register(ViPipe, 0x380e, 0x01);
ov6211_write_register(ViPipe, 0x380f, 0xb6);
ov6211_write_register(ViPipe, 0x3810, 0x00);
ov6211_write_register(ViPipe, 0x3811, 0x04);
ov6211_write_register(ViPipe, 0x3812, 0x00);
ov6211_write_register(ViPipe, 0x3813, 0x04);
ov6211_write_register(ViPipe, 0x3814, 0x11);
ov6211_write_register(ViPipe, 0x3815, 0x11);
ov6211_write_register(ViPipe, 0x3820, 0x00);
ov6211_write_register(ViPipe, 0x3821, 0x00);
ov6211_write_register(ViPipe, 0x382b, 0xfa);
ov6211_write_register(ViPipe, 0x382f, 0x04);
ov6211_write_register(ViPipe, 0x3832, 0x00);
ov6211_write_register(ViPipe, 0x3833, 0x05);
ov6211_write_register(ViPipe, 0x3834, 0x00);
ov6211_write_register(ViPipe, 0x3835, 0x05);
ov6211_write_register(ViPipe, 0x3882, 0x04);
ov6211_write_register(ViPipe, 0x3883, 0x00);
ov6211_write_register(ViPipe, 0x38a4, 0x10);
ov6211_write_register(ViPipe, 0x38a5, 0x00);
ov6211_write_register(ViPipe, 0x38b1, 0x03);
ov6211_write_register(ViPipe, 0x3b80, 0x00);
ov6211_write_register(ViPipe, 0x3b81, 0xa5);
ov6211_write_register(ViPipe, 0x3b82, 0x10);
ov6211_write_register(ViPipe, 0x3b83, 0x00);
ov6211_write_register(ViPipe, 0x3b84, 0x08);
ov6211_write_register(ViPipe, 0x3b85, 0x00);
ov6211_write_register(ViPipe, 0x3b86, 0x01);
ov6211_write_register(ViPipe, 0x3b87, 0x00);
ov6211_write_register(ViPipe, 0x3b88, 0x00);
ov6211_write_register(ViPipe, 0x3b89, 0x00);
ov6211_write_register(ViPipe, 0x3b8a, 0x00);
ov6211_write_register(ViPipe, 0x3b8b, 0x05);
ov6211_write_register(ViPipe, 0x3b8c, 0x00);
ov6211_write_register(ViPipe, 0x3b8d, 0x00);
ov6211_write_register(ViPipe, 0x3b8e, 0x00);
ov6211_write_register(ViPipe, 0x3b8f, 0x1a);
ov6211_write_register(ViPipe, 0x3b94, 0x05);
ov6211_write_register(ViPipe, 0x3b95, 0xf2);
ov6211_write_register(ViPipe, 0x3b96, 0xf0);
ov6211_write_register(ViPipe, 0x4004, 0x04);
ov6211_write_register(ViPipe, 0x404e, 0x01);
ov6211_write_register(ViPipe, 0x4801, 0x0f);
ov6211_write_register(ViPipe, 0x4806, 0x0f);
ov6211_write_register(ViPipe, 0x4818, 0x00);
ov6211_write_register(ViPipe, 0x4819, 0xaa);
ov6211_write_register(ViPipe, 0x482a, 0x08);
ov6211_write_register(ViPipe, 0x481a, 0x00);
ov6211_write_register(ViPipe, 0x481b, 0x4a);
ov6211_write_register(ViPipe, 0x482b, 0x08);
ov6211_write_register(ViPipe, 0x4837, 0x43);
ov6211_write_register(ViPipe, 0x5a08, 0x00);
ov6211_write_register(ViPipe, 0x5a01, 0x00);
ov6211_write_register(ViPipe, 0x5a03, 0x00);
ov6211_write_register(ViPipe, 0x5a04, 0x10);
ov6211_write_register(ViPipe, 0x5a05, 0xa0);
ov6211_write_register(ViPipe, 0x5a06, 0x0c);
ov6211_write_register(ViPipe, 0x5a07, 0x78);
ov6211_default_reg_init(ViPipe);
ov6211_write_register(ViPipe, 0x0100, 0x01);
delay_ms(100);
printf("ViPipe:%d,===OV6211 400P 120fps 10bit LINE Init OK!===\n", ViPipe);
}

36
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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_ov7251.a
TARGET_SO = $(MW_LIB)/libsns_ov7251.so
EXTRA_CFLAGS = $(INCS) $(PROJ_CFLAGS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@)
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@)
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

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middleware/v2/component/isp/sensor/cv180x/ov_ov7251/ov7251_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_ae_comm.h"
#include "cvi_awb_comm.h"
#include "cvi_ae.h"
#include "cvi_awb.h"
#include "cvi_isp.h"
#include "ov7251_cmos_ex.h"
#include "ov7251_cmos_param.h"
#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a))
#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a))
#define OV7251_ID 7251
#define OV7251_I2C_ADDR_1 0x60
#define OV7251_I2C_ADDR_2 0x70
#define OV7251_I2C_ADDR_IS_VALID(addr) ((addr) == OV7251_I2C_ADDR_1 || (addr) == OV7251_I2C_ADDR_2)
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_STATE_S *g_pastOv7251[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define OV7251_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastOv7251[dev])
#define OV7251_SENSOR_SET_CTX(dev, pstCtx) (g_pastOv7251[dev] = pstCtx)
#define OV7251_SENSOR_RESET_CTX(dev) (g_pastOv7251[dev] = CVI_NULL)
ISP_SNS_COMMBUS_U g_aunOv7251_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
CVI_U16 g_au16Ov7251_GainMode[VI_MAX_PIPE_NUM] = {0};
CVI_U16 g_au16Ov7251_L2SMode[VI_MAX_PIPE_NUM] = {0};
ISP_SNS_MIRRORFLIP_TYPE_E g_aeOv7251_MirrorFip[VI_MAX_PIPE_NUM] = {0};
/****************************************************************************
* local variables and functions *
****************************************************************************/
static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0};
static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} };
static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
/*****Ov7251 Lines Range*****/
#define OV7251_FULL_LINES_MAX (0xFFFF)
/*****Ov7251 Register Address*****/
#define OV7251_EXP_ADDR 0x3500
#define OV7251_AGAIN_ADDR 0x350a
#define OV7251_VTS_ADDR 0x380E
#define OV7251_RES_IS_480P(w, h) ((w) == 640 && (h) == 480)
static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
const OV7251_MODE_S *pstMode;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astOv7251_mode[pstSnsState->u8ImgMode];
#if 0
memset(&pstAeSnsDft->stAERouteAttr, 0, sizeof(ISP_AE_ROUTE_S));
#endif
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32FlickerFreq = 50 * 256;
pstAeSnsDft->u32FullLinesMax = OV7251_FULL_LINES_MAX;
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30);
pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_DB;
pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
pstAeSnsDft->u32ISPDgainShift = 8;
pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift;
pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
if (g_au32LinesPer500ms[ViPipe] == 0)
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2;
else
pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
pstAeSnsDft->u32SnsStableFrame = 0;
#if 0
pstAeSnsDft->enMaxIrisFNO = ISP_IRIS_F_NO_1_0;
pstAeSnsDft->enMinIrisFNO = ISP_IRIS_F_NO_32_0;
pstAeSnsDft->bAERouteExValid = CVI_FALSE;
pstAeSnsDft->stAERouteAttr.u32TotalNum = 0;
pstAeSnsDft->stAERouteAttrEx.u32TotalNum = 0;
#endif
switch (pstSnsState->enWDRMode) {
default:
case WDR_MODE_NONE: /*linear mode*/
pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
pstAeSnsDft->au8HistThresh[0] = 0xd;
pstAeSnsDft->au8HistThresh[1] = 0x28;
pstAeSnsDft->au8HistThresh[2] = 0x60;
pstAeSnsDft->au8HistThresh[3] = 0x80;
pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u16Max;
pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u16Min;
pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u16Max;
pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u16Min;
pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
pstAeSnsDft->u8AeCompensation = 40;
pstAeSnsDft->u32InitAESpeed = 64;
pstAeSnsDft->u32InitAETolerance = 5;
pstAeSnsDft->u32AEResponseFrame = 4;
pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151;
pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
pstAeSnsDft->u32MaxIntTimeTarget = 65535;
pstAeSnsDft->u32MinIntTimeTarget = 1;
break;
}
return CVI_SUCCESS;
}
/* the function of sensor set fps */
static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CVI_U32 u32VMAX;
CVI_FLOAT f32MaxFps = 0;
CVI_FLOAT f32MinFps = 0;
CVI_U32 u32Vts = 0;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CMOS_CHECK_POINTER(pstAeSnsDft);
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u32Vts = g_astOv7251_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
f32MaxFps = g_astOv7251_mode[pstSnsState->u8ImgMode].f32MaxFps;
f32MinFps = g_astOv7251_mode[pstSnsState->u8ImgMode].f32MinFps;
switch (pstSnsState->u8ImgMode) {
case OV7251_MODE_640X480P120:
if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps);
return CVI_FAILURE;
}
u32VMAX = (u32VMAX > OV7251_FULL_LINES_MAX) ? OV7251_FULL_LINES_MAX : u32VMAX;
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode);
return CVI_FAILURE;
}
pstSnsState->u32FLStd = u32VMAX;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = ((u32VMAX & 0xFF00) >> 8);
pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = (u32VMAX & 0xFF);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
pstAeSnsDft->f32Fps = f32Fps;
pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2;
pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0];
pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps));
return CVI_SUCCESS;
}
/* while isp notify ae to update sensor regs, ae call these funcs. */
static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32TmpIntTime, u32MinTime, u32MaxTime;
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(u32IntTime);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
/* linear exposure reg range:
* min : 2
* max : vts - 20
* step : 1
*/
u32MinTime = 2;
u32MaxTime = pstSnsState->au32FL[0] - 20;
u32TmpIntTime = (u32IntTime[0] > u32MaxTime) ? u32MaxTime : u32IntTime[0];
u32TmpIntTime = (u32TmpIntTime < u32MinTime) ? u32MinTime : u32TmpIntTime;
pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((u32TmpIntTime & 0xF000) >> 12);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((u32TmpIntTime & 0x0FF0) >> 4);
pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = ((u32TmpIntTime & 0x000F) << 4);
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
typedef struct gain_tbl_info_s {
CVI_U16 gainMax;
CVI_U16 idxBase;
CVI_U8 regGain;
CVI_U8 regGainFineBase;
CVI_U8 regGainFineStep;
} gain_tbl_info_s;
static struct gain_tbl_info_s AgainInfo[15] = {
{
.gainMax = 1984,
.idxBase = 0,
.regGain = 0x01,
.regGainFineBase = 0x00,
.regGainFineStep = 1,
},
{
.gainMax = 2944,
.idxBase = 16,
.regGain = 0x02,
.regGainFineBase = 0x00,
.regGainFineStep = 2,
},
{
.gainMax = 3968,
.idxBase = 24,
.regGain = 0x03,
.regGainFineBase = 0x00,
.regGainFineStep = 2,
},
{
.gainMax = 4864,
.idxBase = 32,
.regGain = 0x04,
.regGainFineBase = 0x00,
.regGainFineStep = 4,
},
{
.gainMax = 5888,
.idxBase = 36,
.regGain = 0x05,
.regGainFineBase = 0x00,
.regGainFineStep = 4,
},
{
.gainMax = 6912,
.idxBase = 40,
.regGain = 0x06,
.regGainFineBase = 0x00,
.regGainFineStep = 4,
},
{
.gainMax = 7936,
.idxBase = 44,
.regGain = 0x07,
.regGainFineBase = 0x00,
.regGainFineStep = 4,
},
{
.gainMax = 8704,
.idxBase = 48,
.regGain = 0x08,
.regGainFineBase = 0x08,
.regGainFineStep = 8,
},
{
.gainMax = 9728,
.idxBase = 49,
.regGain = 0x09,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 10752,
.idxBase = 51,
.regGain = 0x0a,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 11776,
.idxBase = 53,
.regGain = 0x0b,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 12800,
.idxBase = 55,
.regGain = 0x0c,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 13824,
.idxBase = 57,
.regGain = 0x0d,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 14848,
.idxBase = 59,
.regGain = 0x0e,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
{
.gainMax = 15872,
.idxBase = 61,
.regGain = 0x0f,
.regGainFineBase = 0x00,
.regGainFineStep = 8,
},
};
static CVI_U32 Again_table[] = {
1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792,
1856, 1920, 1984, 2048, 2176, 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200,
3328, 3456, 3584, 3712, 3840, 3968, 4096, 4352, 4608, 4864, 5120, 5376, 5632,
5888, 6144, 6400, 6656, 6912, 7168, 7424, 7680, 7936, 8704, 9216, 9728, 10240,
10752, 11264, 11776, 12288, 12800, 13312, 13824, 14336, 14848, 15360, 15872
};
static const CVI_U32 again_table_size = ARRAY_SIZE(Again_table);
static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb)
{
CVI_U32 i;
(void) ViPipe;
CMOS_CHECK_POINTER(pu32AgainLin);
CMOS_CHECK_POINTER(pu32AgainDb);
if (*pu32AgainLin >= Again_table[again_table_size - 1]) {
*pu32AgainLin = Again_table[again_table_size - 1];
*pu32AgainDb = again_table_size - 1;
return CVI_SUCCESS;
}
for (i = 1; i < again_table_size; i++) {
if (*pu32AgainLin < Again_table[i]) {
*pu32AgainLin = Again_table[i - 1];
*pu32AgainDb = i - 1;
break;
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb)
{
(void) ViPipe;
CMOS_CHECK_POINTER(pu32DgainLin);
CMOS_CHECK_POINTER(pu32DgainDb);
*pu32DgainLin = 1024;
*pu32DgainDb = 0;
return CVI_SUCCESS;
}
static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
CVI_U32 u32Again;
struct gain_tbl_info_s *info;
int i, tbl_num;
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pu32Again);
CMOS_CHECK_POINTER(pu32Dgain);
pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
u32Again = pu32Again[0];
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
/* linear mode */
/* find Again register setting. */
tbl_num = sizeof(AgainInfo)/sizeof(struct gain_tbl_info_s);
for (i = tbl_num - 1; i >= 0; i--) {
info = &AgainInfo[i];
if (u32Again >= info->idxBase)
break;
}
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN0].u32Data = 0x00;
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN1].u32Data = (info->regGain & 0x0F) << 4;
u32Again = info->regGainFineBase + (u32Again - info->idxBase) * info->regGainFineStep;
pstSnsRegsInfo->astI2cData[LINEAR_AGAIN1].u32Data |= (u32Again & 0x0F);
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default;
pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set;
//pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set;
pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update;
pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update;
pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table;
pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table;
//pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max;
//pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
{
(void) ViPipe;
CMOS_CHECK_POINTER(pstAwbSnsDft);
memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
pstAwbSnsDft->u16InitGgain = 1024;
pstAwbSnsDft->u8AWBRunInterval = 1;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
{
CMOS_CHECK_POINTER(pstExpFuncs);
memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S));
pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default;
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
{
(void) ViPipe;
memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
{
(void) ViPipe;
CMOS_CHECK_POINTER(pstBlc);
memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
memcpy(pstBlc,
&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const OV7251_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astOv7251_mode[pstSnsState->u8ImgMode];
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsState->bSyncInit = CVI_FALSE;
switch (u8Mode) {
case WDR_MODE_NONE:
pstSnsState->u8ImgMode = OV7251_MODE_640X480P120;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astOv7251_mode[pstSnsState->u8ImgMode].u32VtsDef;
syslog(LOG_INFO, "WDR_MODE_NONE\n");
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
return CVI_FAILURE;
}
pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
return CVI_SUCCESS;
}
static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2)
{
CVI_U32 i;
if (pstWdr1->frm_num != pstWdr2->frm_num)
goto _mismatch;
for (i = 0; i < 2; i++) {
if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width)
goto _mismatch;
if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height)
goto _mismatch;
}
return 0;
_mismatch:
return 1;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
CVI_U32 i;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL;
ISP_I2C_DATA_S *pstI2c_data = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg;
pstCfg0 = &pstSnsState->astSyncInfo[0];
pstCfg1 = &pstSnsState->astSyncInfo[1];
pstI2c_data = pstCfg0->snsCfg.astI2cData;
if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) {
pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE;
pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunOv7251_BusInfo[ViPipe].s8I2cDev;
pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
pstI2c_data[i].bUpdate = CVI_TRUE;
pstI2c_data[i].u8DevAddr = ov7251_i2c_addr;
pstI2c_data[i].u32AddrByteNum = ov7251_addr_byte;
pstI2c_data[i].u32DataByteNum = ov7251_data_byte;
}
switch (pstSnsState->enWDRMode) {
case WDR_MODE_NONE:
pstI2c_data[LINEAR_EXP_0].u32RegAddr = OV7251_EXP_ADDR;
pstI2c_data[LINEAR_EXP_1].u32RegAddr = OV7251_EXP_ADDR + 1;
pstI2c_data[LINEAR_EXP_2].u32RegAddr = OV7251_EXP_ADDR + 2;
pstI2c_data[LINEAR_AGAIN0].u32RegAddr = OV7251_AGAIN_ADDR;
pstI2c_data[LINEAR_AGAIN1].u32RegAddr = OV7251_AGAIN_ADDR + 1;
pstI2c_data[LINEAR_VTS_0].u32RegAddr = OV7251_VTS_ADDR;
pstI2c_data[LINEAR_VTS_1].u32RegAddr = OV7251_VTS_ADDR + 1;
break;
default:
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
return CVI_FAILURE;
}
pstSnsState->bSyncInit = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
/* recalcualte WDR size */
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
pstCfg0->ispCfg.need_update = CVI_TRUE;
} else {
pstCfg0->snsCfg.need_update = CVI_FALSE;
for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
} else {
pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
pstCfg0->snsCfg.need_update = CVI_TRUE;
}
}
/* check update isp crop or not */
pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
CVI_TRUE : CVI_FALSE);
}
pstSnsRegsInfo->bConfig = CVI_FALSE;
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
pstSnsState->bSyncInit = CVI_FALSE;
if (pstSensorImageMode->f32Fps <= 120) {
if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
if (OV7251_RES_IS_480P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height))
u8SensorImageMode = OV7251_MODE_640X480P120;
else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
if (pstSnsState->bInit == CVI_TRUE && g_aeOv7251_MirrorFip[ViPipe] != eSnsMirrorFlip) {
ov7251_mirror_flip(ViPipe, eSnsMirrorFlip);
g_aeOv7251_MirrorFip[ViPipe] = eSnsMirrorFlip;
}
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->bSyncInit = CVI_FALSE;
pstSnsState->u8ImgMode = OV7251_MODE_640X480P120;
pstSnsState->enWDRMode = WDR_MODE_NONE;
pstSnsState->u32FLStd = g_astOv7251_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[0] = g_astOv7251_mode[pstSnsState->u8ImgMode].u32VtsDef;
pstSnsState->au32FL[1] = g_astOv7251_mode[pstSnsState->u8ImgMode].u32VtsDef;
memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S));
memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S));
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
OV7251_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
memcpy(pstRxAttr, &ov7251_rx_attr, sizeof(*pstRxAttr));
pstRxAttr->img_size.width = g_astOv7251_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astOv7251_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
if (pstSnsState->enWDRMode == WDR_MODE_NONE)
pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &ov7251_rx_attr;
int i;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
if (pstRxAttr->input_mode == INPUT_MODE_MIPI) {
struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
} else {
struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr;
for (i = 0; i < MIPI_LANE_NUM + 1; i++) {
attr->lane_id[i] = pstRxInitAttr->as16LaneId[i];
attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i];
}
}
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = ov7251_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = ov7251_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode;
pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default;
pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr)
{
if (OV7251_I2C_ADDR_IS_VALID(s32I2cAddr))
ov7251_i2c_addr = s32I2cAddr;
}
static CVI_S32 ov7251_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunOv7251_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
OV7251_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
OV7251_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
OV7251_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
OV7251_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
AE_SENSOR_REGISTER_S stAeRegister;
AWB_SENSOR_REGISTER_S stAwbRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = OV7251_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp);
s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp);
s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
CVI_S32 s32Ret;
CMOS_CHECK_POINTER(pstAeLib);
CMOS_CHECK_POINTER(pstAwbLib);
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, OV7251_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, OV7251_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n");
return s32Ret;
}
s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, OV7251_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr)
{
CMOS_CHECK_POINTER(pstInitAttr);
g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure;
g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms;
g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain;
g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain;
g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain;
g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain;
g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain;
g_au16Ov7251_GainMode[ViPipe] = pstInitAttr->enGainMode;
g_au16Ov7251_L2SMode[ViPipe] = pstInitAttr->enL2SMode;
return CVI_SUCCESS;
}
static CVI_S32 sensor_probe(VI_PIPE ViPipe)
{
return ov7251_probe(ViPipe);
}
ISP_SNS_OBJ_S stSnsOv7251_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = ov7251_standby,
.pfnRestart = ov7251_restart,
.pfnMirrorFlip = sensor_mirror_flip,
.pfnWriteReg = ov7251_write_register,
.pfnReadReg = ov7251_read_register,
.pfnSetBusInfo = ov7251_set_bus_info,
.pfnSetInit = sensor_set_init,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = sensor_patch_i2c_addr,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = cmos_init_ae_exp_function,
.pfnSnsProbe = sensor_probe,
};

86
middleware/v2/component/isp/sensor/cv180x/ov_ov7251/ov7251_cmos_ex.h Normal file
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#ifndef __OV7251_CMOS_EX_H_
#define __OV7251_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
enum ov7251_linear_regs_e {
LINEAR_EXP_0 = 0,
LINEAR_EXP_1,
LINEAR_EXP_2,
LINEAR_AGAIN0,
LINEAR_AGAIN1,
LINEAR_VTS_0,
LINEAR_VTS_1,
LINEAR_REGS_NUM
};
typedef enum _OV7251_MODE_E {
OV7251_MODE_640X480P120 = 0,
OV7251_MODE_LINEAR_NUM,
OV7251_MODE_NUM
} OV7251_MODE_E;
typedef struct _OV7251_STATE_S {
CVI_U32 u32Sexp_MAX;
} OV7251_STATE_S;
typedef struct _OV7251_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
CVI_U16 u16L2sOffset;
CVI_U16 u16TopBoundary;
CVI_U16 u16BotBoundary;
SNS_ATTR_S stExp[2];
SNS_ATTR_S stAgain[2];
SNS_ATTR_S stDgain[2];
CVI_U32 u32L2S_MAX;
char name[64];
} OV7251_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastOv7251[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunOv7251_BusInfo[];
extern CVI_U16 g_au16Ov7251_GainMode[];
extern CVI_U16 g_au16Ov7251_L2SMode[VI_MAX_PIPE_NUM];
extern CVI_U8 ov7251_i2c_addr;
extern const CVI_U32 ov7251_addr_byte;
extern const CVI_U32 ov7251_data_byte;
extern void ov7251_init(VI_PIPE ViPipe);
extern void ov7251_exit(VI_PIPE ViPipe);
extern void ov7251_standby(VI_PIPE ViPipe);
extern void ov7251_restart(VI_PIPE ViPipe);
extern int ov7251_write_register(VI_PIPE ViPipe, int addr, int data);
extern int ov7251_read_register(VI_PIPE ViPipe, int addr);
extern void ov7251_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
extern int ov7251_probe(VI_PIPE ViPipe);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OV7251_CMOS_EX_H_ */

122
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#ifndef __OV7251_CMOS_PARAM_H_
#define __OV7251_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "ov7251_cmos_ex.h"
static const OV7251_MODE_S g_astOv7251_mode[OV7251_MODE_NUM] = {
[OV7251_MODE_640X480P120] = {
.name = "640X480P120",
.astImg[0] = {
.stSnsSize = {
.u32Width = 640,
.u32Height = 480,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 640,
.u32Height = 480,
},
.stMaxSize = {
.u32Width = 640,
.u32Height = 480,
},
},
.f32MaxFps = 120,
.f32MinFps = 0.79, /* 0x20a * 100 / 0xFFFF */
.u32HtsDef = 1522,
.u32VtsDef = 538,
.stExp[0] = {
.u16Min = 2,
.u16Max = 538 - 20,
.u16Def = 100,
.u16Step = 1,
},
.stAgain[0] = {
.u16Min = 1024,
.u16Max = 15872,
.u16Def = 1024,
.u16Step = 1,
},
.stDgain[0] = {
.u16Min = 1024,
.u16Max = 1024,
.u16Def = 1024,
.u16Step = 1,
},
},
};
static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
.bUpdate = CVI_TRUE,
.blcAttr = {
.Enable = 1,
.enOpType = OP_TYPE_AUTO,
.stManual = {64, 64, 64, 64, 0, 0, 0, 0
#ifdef ARCH_CV182X
, 1040, 1040, 1040, 1040
#endif
},
.stAuto = {
{64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64},
{64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64},
{64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64},
{64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#ifdef ARCH_CV182X
{1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040,
/*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040},
{1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040,
/*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040},
{1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040,
/*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040},
{1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040,
/*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040},
#endif
},
},
};
struct combo_dev_attr_s ov7251_rx_attr = {
.input_mode = INPUT_MODE_MIPI,
.mac_clk = RX_MAC_CLK_200M,
.mipi_attr = {
.raw_data_type = RAW_DATA_10BIT,
.lane_id = {1, 0, -1, -1, -1},
.pn_swap = {1, 1, 0, 0, 0},
.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
},
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_24M,
},
.devno = 0,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __OV7251_CMOS_PARAM_H_ */

318
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#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <syslog.h>
#include <fcntl.h>
#include <unistd.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#ifdef ARCH_CV182X
#include <linux/cvi_vip_snsr.h>
#include "cvi_comm_video.h"
#else
#include <linux/vi_snsr.h>
#include <linux/cvi_comm_video.h>
#endif
#include "cvi_sns_ctrl.h"
#include "ov7251_cmos_ex.h"
static void ov7251_linear_480p120_init(VI_PIPE ViPipe);
CVI_U8 ov7251_i2c_addr = 0x60; /* I2C Address of OV7251 */
const CVI_U32 ov7251_addr_byte = 2;
const CVI_U32 ov7251_data_byte = 1;
static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1};
int ov7251_i2c_init(VI_PIPE ViPipe)
{
char acDevFile[16] = {0};
CVI_U8 u8DevNum;
if (g_fd[ViPipe] >= 0)
return CVI_SUCCESS;
int ret;
u8DevNum = g_aunOv7251_BusInfo[ViPipe].s8I2cDev;
snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum);
g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600);
if (g_fd[ViPipe] < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum);
return CVI_FAILURE;
}
ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, ov7251_i2c_addr);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n");
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return ret;
}
return CVI_SUCCESS;
}
int ov7251_i2c_exit(VI_PIPE ViPipe)
{
if (g_fd[ViPipe] >= 0) {
close(g_fd[ViPipe]);
g_fd[ViPipe] = -1;
return CVI_SUCCESS;
}
return CVI_FAILURE;
}
int ov7251_read_register(VI_PIPE ViPipe, int addr)
{
int ret, data;
CVI_U8 buf[8];
CVI_U8 idx = 0;
if (g_fd[ViPipe] < 0)
return CVI_FAILURE;
if (ov7251_addr_byte == 2)
buf[idx++] = (addr >> 8) & 0xff;
// add address byte 0
buf[idx++] = addr & 0xff;
ret = write(g_fd[ViPipe], buf, ov7251_addr_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return 0;
}
buf[0] = 0;
buf[1] = 0;
ret = read(g_fd[ViPipe], buf, ov7251_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n");
return 0;
}
// pack read back data
data = 0;
if (ov7251_data_byte == 2) {
data = buf[0] << 8;
data += buf[1];
} else {
data = buf[0];
}
syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data);
return data;
}
int ov7251_write_register(VI_PIPE ViPipe, int addr, int data)
{
CVI_U8 idx = 0;
int ret;
CVI_U8 buf[8];
if (g_fd[ViPipe] < 0)
return CVI_SUCCESS;
if (ov7251_addr_byte == 2) {
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
if (ov7251_data_byte == 1) {
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, ov7251_addr_byte + ov7251_data_byte);
if (ret < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n");
return CVI_FAILURE;
}
syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data);
return CVI_SUCCESS;
}
static void delay_ms(int ms)
{
usleep(ms * 1000);
}
void ov7251_standby(VI_PIPE ViPipe)
{
ov7251_write_register(ViPipe, 0x0100, 0x00); /* standby */
}
void ov7251_restart(VI_PIPE ViPipe)
{
ov7251_write_register(ViPipe, 0x0100, 0x00);
delay_ms(20);
ov7251_write_register(ViPipe, 0x0100, 0x01); /* restart */
}
void ov7251_default_reg_init(VI_PIPE ViPipe)
{
CVI_U32 i;
for (i = 0; i < g_pastOv7251[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) {
if (g_pastOv7251[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].bUpdate == CVI_TRUE) {
ov7251_write_register(ViPipe,
g_pastOv7251[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr,
g_pastOv7251[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data);
}
}
}
void ov7251_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
{
CVI_U8 flip, mirror;
flip = ov7251_read_register(ViPipe, 0x3820);
mirror = ov7251_read_register(ViPipe, 0x3821);
flip &= ~(0x1 << 2);
mirror &= ~(0x1 << 2);
switch (eSnsMirrorFlip) {
case ISP_SNS_NORMAL:
break;
case ISP_SNS_MIRROR:
mirror |= 0x1 << 2;
break;
case ISP_SNS_FLIP:
flip |= 0x1 << 2;
break;
case ISP_SNS_MIRROR_FLIP:
flip |= 0x1 << 2;
mirror |= 0x1 << 2;
break;
default:
return;
}
ov7251_write_register(ViPipe, 0x3820, flip);
ov7251_write_register(ViPipe, 0x3821, mirror);
}
#define OV7251_CHIP_ID_ADDR_H 0x300A
#define OV7251_CHIP_ID_ADDR_L 0x300B
#define OV7251_CHIP_ID 0x7750
int ov7251_probe(VI_PIPE ViPipe)
{
int nVal, nVal2;
if (ov7251_i2c_init(ViPipe) != CVI_SUCCESS)
return CVI_FAILURE;
delay_ms(5);
nVal = ov7251_read_register(ViPipe, OV7251_CHIP_ID_ADDR_H);
nVal2 = ov7251_read_register(ViPipe, OV7251_CHIP_ID_ADDR_L);
if (nVal < 0 || nVal2 < 0) {
CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n");
return nVal;
}
if ((((nVal & 0xFF) << 8) | ((nVal2 & 0xFF) << 0)) != OV7251_CHIP_ID) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n");
return CVI_FAILURE;
}
return CVI_SUCCESS;
}
void ov7251_init(VI_PIPE ViPipe)
{
ov7251_i2c_init(ViPipe);
ov7251_linear_480p120_init(ViPipe);
g_pastOv7251[ViPipe]->bInit = CVI_TRUE;
}
void ov7251_exit(VI_PIPE ViPipe)
{
ov7251_i2c_exit(ViPipe);
}
/* 1944P30 and 1944P25 */
static void ov7251_linear_480p120_init(VI_PIPE ViPipe)
{
ov7251_write_register(ViPipe, 0x0103, 0x01);
ov7251_write_register(ViPipe, 0x0100, 0x00);
ov7251_write_register(ViPipe, 0x3012, 0xc0);
ov7251_write_register(ViPipe, 0x3013, 0xd2);
ov7251_write_register(ViPipe, 0x3016, 0x10);
ov7251_write_register(ViPipe, 0x3017, 0x00);
ov7251_write_register(ViPipe, 0x3018, 0x00);
ov7251_write_register(ViPipe, 0x301a, 0x00);
ov7251_write_register(ViPipe, 0x301b, 0x00);
ov7251_write_register(ViPipe, 0x301c, 0x00);
ov7251_write_register(ViPipe, 0x3023, 0x05);
ov7251_write_register(ViPipe, 0x3099, 0x32);
ov7251_write_register(ViPipe, 0x30b3, 0x64);
ov7251_write_register(ViPipe, 0x30b4, 0x03);
ov7251_write_register(ViPipe, 0x30b5, 0x05);
ov7251_write_register(ViPipe, 0x3106, 0xda);
ov7251_write_register(ViPipe, 0x3501, 0x1f);
ov7251_write_register(ViPipe, 0x3502, 0x80);
ov7251_write_register(ViPipe, 0x3503, 0x07);
ov7251_write_register(ViPipe, 0x3600, 0x1c);
ov7251_write_register(ViPipe, 0x3602, 0x62);
ov7251_write_register(ViPipe, 0x3620, 0xb7);
ov7251_write_register(ViPipe, 0x3622, 0x04);
ov7251_write_register(ViPipe, 0x3626, 0x21);
ov7251_write_register(ViPipe, 0x3627, 0x30);
ov7251_write_register(ViPipe, 0x3630, 0x44);
ov7251_write_register(ViPipe, 0x3631, 0x35);
ov7251_write_register(ViPipe, 0x3634, 0x60);
ov7251_write_register(ViPipe, 0x3663, 0x70);
ov7251_write_register(ViPipe, 0x3669, 0x1a);
ov7251_write_register(ViPipe, 0x3673, 0x01);
ov7251_write_register(ViPipe, 0x3674, 0xef);
ov7251_write_register(ViPipe, 0x3675, 0x03);
ov7251_write_register(ViPipe, 0x3705, 0xc1);
ov7251_write_register(ViPipe, 0x3757, 0xb3);
ov7251_write_register(ViPipe, 0x37a8, 0x01);
ov7251_write_register(ViPipe, 0x37a9, 0xc0);
ov7251_write_register(ViPipe, 0x380d, 0xa0);
ov7251_write_register(ViPipe, 0x380f, 0x1a);
ov7251_write_register(ViPipe, 0x3811, 0x04);
ov7251_write_register(ViPipe, 0x3813, 0x05);
ov7251_write_register(ViPipe, 0x3820, 0x40);
ov7251_write_register(ViPipe, 0x382f, 0x0e);
ov7251_write_register(ViPipe, 0x3835, 0x0c);
ov7251_write_register(ViPipe, 0x3b80, 0x00);
ov7251_write_register(ViPipe, 0x3c01, 0x63);
ov7251_write_register(ViPipe, 0x3c07, 0x06);
ov7251_write_register(ViPipe, 0x3c0c, 0x01);
ov7251_write_register(ViPipe, 0x3c0d, 0xd0);
ov7251_write_register(ViPipe, 0x3c0e, 0x02);
ov7251_write_register(ViPipe, 0x3c0f, 0x0a);
ov7251_write_register(ViPipe, 0x4001, 0x42);
ov7251_write_register(ViPipe, 0x404e, 0x01);
ov7251_write_register(ViPipe, 0x4501, 0x48);
ov7251_write_register(ViPipe, 0x4601, 0x4e);
ov7251_write_register(ViPipe, 0x4801, 0x0f);
ov7251_write_register(ViPipe, 0x4819, 0xaa);
ov7251_write_register(ViPipe, 0x4823, 0x3e);
ov7251_write_register(ViPipe, 0x4a47, 0x7f);
ov7251_write_register(ViPipe, 0x4a49, 0xf0);
ov7251_write_register(ViPipe, 0x4a4b, 0x30);
ov7251_write_register(ViPipe, 0x5001, 0x80);
ov7251_default_reg_init(ViPipe);
ov7251_write_register(ViPipe, 0x0100, 0x01);
delay_ms(100);
printf("ViPipe:%d,===OV7251 480P 120fps 10bit LINE Init OK!===\n", ViPipe);
}

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middleware/v2/component/isp/sensor/cv180x/pixelplus_pr2020/Makefile Normal file
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SHELL = /bin/bash
ifeq ($(PARAM_FILE), )
PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param
include $(PARAM_FILE)
endif
SDIR = $(PWD)
SRCS = $(wildcard $(SDIR)/*.c)
INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include
OBJS = $(SRCS:.c=.o)
DEPS = $(SRCS:.c=.d)
TARGET_A = $(MW_LIB)/libsns_pr2020.a
TARGET_SO = $(MW_LIB)/libsns_pr2020.so
EXTRA_CFLAGS = $(INCS)
EXTRA_LDFLAGS =
.PHONY : clean all
all : $(TARGET_A) $(TARGET_SO)
$(SDIR)/%.o: $(SDIR)/%.c
@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@
@echo [$(notdir $(CC))] $(notdir $@)
$(TARGET_A): $(OBJS)
@$(AR) $(ARFLAGS) $@ $(OBJS)
@echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A))
$(TARGET_SO): $(OBJS)
@$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group
@echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO))
clean:
@rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO)
-include $(DEPS)

293
middleware/v2/component/isp/sensor/cv180x/pixelplus_pr2020/pr2020_cmos.c Normal file
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <syslog.h>
#include <errno.h>
#ifdef ARCH_CV182X
#include "cvi_type.h"
#include "cvi_comm_video.h"
#include <linux/cvi_vip_snsr.h>
#else
#include <linux/cvi_type.h>
#include <linux/cvi_comm_video.h>
#include <linux/vi_snsr.h>
#endif
#include "cvi_debug.h"
#include "cvi_comm_sns.h"
#include "cvi_sns_ctrl.h"
#include "cvi_isp.h"
#include "pr2020_cmos_ex.h"
#include "pr2020_cmos_param.h"
/****************************************************************************
* global variables *
****************************************************************************/
ISP_SNS_COMMBUS_U g_aunPr2020_BusInfo[VI_MAX_PIPE_NUM] = {
[0] = { .s8I2cDev = 0},
[1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1}
};
ISP_SNS_STATE_S *g_pastPr2020[VI_MAX_PIPE_NUM] = {CVI_NULL};
#define PR2020_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastPr2020[dev])
#define PR2020_SENSOR_SET_CTX(dev, pstCtx) (g_pastPr2020[dev] = pstCtx)
#define PR2020_SENSOR_RESET_CTX(dev) (g_pastPr2020[dev] = CVI_NULL)
#define PR2020_RES_IS_720P(w, h) ((w) <= 1280 && (h) <= 720)
#define PR2020_RES_IS_1080P(w, h) ((w) <= 1920 && (h) <= 1080)
#define PR2020_ID 2020
/****************************************************************************
* local variables and functions *
****************************************************************************/
static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
{
const PR2020_MODE_S *pstMode = CVI_NULL;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
PR2020_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstMode = &g_astPr2020_mode[pstSnsState->u8ImgMode];
pstIspCfg->frm_num = 1;
memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL;
CMOS_CHECK_POINTER(pstSnsSyncInfo);
PR2020_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
pstCfg0 = &pstSnsState->astSyncInfo[0];
cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
return CVI_SUCCESS;
}
static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode)
{
CVI_U8 u8SensorImageMode = 0;
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
CMOS_CHECK_POINTER(pstSensorImageMode);
PR2020_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
u8SensorImageMode = pstSnsState->u8ImgMode;
if (pstSensorImageMode->f32Fps <= 25) {
if (PR2020_RES_IS_720P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
u8SensorImageMode = PR2020_MODE_720P_25;
} else if (PR2020_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
u8SensorImageMode = PR2020_MODE_1080P_25;
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
} else if (pstSensorImageMode->f32Fps <= 30) {
if (PR2020_RES_IS_720P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
u8SensorImageMode = PR2020_MODE_720P_30;
} else if (PR2020_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
u8SensorImageMode = PR2020_MODE_1080P_30;
} else {
CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
pstSensorImageMode->u16Width,
pstSensorImageMode->u16Height,
pstSensorImageMode->f32Fps,
pstSnsState->enWDRMode);
return CVI_FAILURE;
}
}
if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) {
/* Don't need to switch SensorImageMode */
return CVI_FAILURE;
}
pstSnsState->u8ImgMode = u8SensorImageMode;
return CVI_SUCCESS;
}
static CVI_VOID sensor_global_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
PR2020_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER_VOID(pstSnsState);
pstSnsState->bInit = CVI_FALSE;
pstSnsState->u8ImgMode = PR2020_MODE_1080P_25;
pstSnsState->enWDRMode = WDR_MODE_NONE;
}
static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
{
ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
PR2020_SENSOR_GET_CTX(ViPipe, pstSnsState);
CMOS_CHECK_POINTER(pstSnsState);
CMOS_CHECK_POINTER(pstRxAttr);
if (ViPipe == 0) {
memcpy(pstRxAttr, &pr2020_rx_attr, sizeof(*pstRxAttr));
CVI_TRACE_SNS(CVI_DBG_INFO, "get pr2020_rx_attr\n");
} else {
memcpy(pstRxAttr, &pr2020_rx1_attr, sizeof(*pstRxAttr));
CVI_TRACE_SNS(CVI_DBG_INFO, "get pr2020_rx1_attr\n");
}
pstRxAttr->img_size.width = g_astPr2020_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
pstRxAttr->img_size.height = g_astPr2020_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
return CVI_SUCCESS;
}
static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr)
{
SNS_COMBO_DEV_ATTR_S *pstRxAttr = &pr2020_rx_attr;
CMOS_CHECK_POINTER(pstRxInitAttr);
if (pstRxInitAttr->stMclkAttr.bMclkEn)
pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk;
if (pstRxInitAttr->MipiDev >= 2)
return CVI_SUCCESS;
pstRxAttr->devno = pstRxInitAttr->MipiDev;
return CVI_SUCCESS;
}
static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc)
{
CMOS_CHECK_POINTER(pstSensorExpFunc);
memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S));
pstSensorExpFunc->pfn_cmos_sensor_init = pr2020_init;
pstSensorExpFunc->pfn_cmos_sensor_exit = pr2020_exit;
pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init;
pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode;
pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info;
return CVI_SUCCESS;
}
/****************************************************************************
* callback structure *
****************************************************************************/
static CVI_S32 pr2020_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo)
{
g_aunPr2020_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev;
return CVI_SUCCESS;
}
static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
PR2020_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
if (pastSnsStateCtx == CVI_NULL) {
pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S));
if (pastSnsStateCtx == CVI_NULL) {
CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe);
return -ENOMEM;
}
}
memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S));
PR2020_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx);
return CVI_SUCCESS;
}
static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe)
{
ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL;
PR2020_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx);
SENSOR_FREE(pastSnsStateCtx);
PR2020_SENSOR_RESET_CTX(ViPipe);
}
static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
(void) pstAeLib;
(void) pstAwbLib;
CVI_S32 s32Ret;
ISP_SENSOR_REGISTER_S stIspRegister;
ISP_SNS_ATTR_INFO_S stSnsAttrInfo;
s32Ret = sensor_ctx_init(ViPipe);
if (s32Ret != CVI_SUCCESS)
return CVI_FAILURE;
stSnsAttrInfo.eSensorId = PR2020_ID;
s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp);
s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n");
return s32Ret;
}
return CVI_SUCCESS;
}
static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib)
{
(void) pstAeLib;
(void) pstAwbLib;
CVI_S32 s32Ret;
s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, PR2020_ID);
if (s32Ret != CVI_SUCCESS) {
CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n");
return s32Ret;
}
sensor_ctx_exit(ViPipe);
return CVI_SUCCESS;
}
ISP_SNS_OBJ_S stSnsPR2020_Obj = {
.pfnRegisterCallback = sensor_register_callback,
.pfnUnRegisterCallback = sensor_unregister_callback,
.pfnStandby = CVI_NULL,
.pfnRestart = CVI_NULL,
.pfnMirrorFlip = CVI_NULL,
.pfnWriteReg = pr2020_write_register,
.pfnReadReg = pr2020_read_register,
.pfnSetBusInfo = pr2020_set_bus_info,
.pfnSetInit = CVI_NULL,
.pfnPatchRxAttr = sensor_patch_rx_attr,
.pfnPatchI2cAddr = CVI_NULL,
.pfnGetRxAttr = sensor_rx_attr,
.pfnExpSensorCb = cmos_init_sensor_exp_function,
.pfnExpAeCb = CVI_NULL,
.pfnSnsProbe = CVI_NULL,
};

70
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#ifndef __PR2020_CMOS_EX_H_
#define __PR2020_CMOS_EX_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
typedef enum _PR2020_MODE_E {
PR2020_MODE_NONE,
PR2020_MODE_720H_NTSC,
PR2020_MODE_720H_PAL,
PR2020_MODE_720P_25,
PR2020_MODE_720P_30,
PR2020_MODE_720P_50,
PR2020_MODE_720P_60,
PR2020_MODE_1080P_25,
PR2020_MODE_1080P_30,
PR2020_MODE_NUM
} PR2020_MODE_E;
typedef struct _PR2020_MODE_S {
ISP_WDR_SIZE_S astImg[2];
CVI_FLOAT f32MaxFps;
CVI_FLOAT f32MinFps;
CVI_U32 u32HtsDef;
CVI_U32 u32VtsDef;
SNS_ATTR_S stExp[2];
SNS_ATTR_S stAgain[2];
SNS_ATTR_S stDgain[2];
CVI_U8 u8DgainReg;
char name[64];
} PR2020_MODE_S;
/****************************************************************************
* external variables and functions *
****************************************************************************/
extern ISP_SNS_STATE_S *g_pastPr2020[VI_MAX_PIPE_NUM];
extern ISP_SNS_COMMBUS_U g_aunPr2020_BusInfo[];
extern const CVI_U8 pr2020_i2c_addr;
extern const CVI_U32 pr2020_addr_byte;
extern const CVI_U32 pr2020_data_byte;
extern void pr2020_init(VI_PIPE ViPipe);
extern void pr2020_exit(VI_PIPE ViPipe);
extern void pr2020_standby(VI_PIPE ViPipe);
extern void pr2020_restart(VI_PIPE ViPipe);
extern int pr2020_write_register(VI_PIPE ViPipe, int addr, int data);
extern int pr2020_read_register(VI_PIPE ViPipe, int addr);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __PR2020_CMOS_EX_H_ */

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#ifndef __PR2020_CMOS_PARAM_H_
#define __PR2020_CMOS_PARAM_H_
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif
#ifdef ARCH_CV182X
#include <linux/cvi_vip_cif.h>
#include <linux/cvi_vip_snsr.h>
#include "cvi_type.h"
#else
#include <linux/cif_uapi.h>
#include <linux/vi_snsr.h>
#include <linux/cvi_type.h>
#endif
#include "cvi_sns_ctrl.h"
#include "pr2020_cmos_ex.h"
static const PR2020_MODE_S g_astPr2020_mode[PR2020_MODE_NUM] = {
[PR2020_MODE_720P_25] = {
.name = "720p25",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1280,
.u32Height = 720,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1280,
.u32Height = 720,
},
.stMaxSize = {
.u32Width = 1280,
.u32Height = 720,
},
},
},
[PR2020_MODE_720P_30] = {
.name = "720p30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1280,
.u32Height = 720,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1280,
.u32Height = 720,
},
.stMaxSize = {
.u32Width = 1280,
.u32Height = 720,
},
},
},
[PR2020_MODE_1080P_25] = {
.name = "1080p25",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
},
[PR2020_MODE_1080P_30] = {
.name = "1080p30",
.astImg[0] = {
.stSnsSize = {
.u32Width = 1920,
.u32Height = 1080,
},
.stWndRect = {
.s32X = 0,
.s32Y = 0,
.u32Width = 1920,
.u32Height = 1080,
},
.stMaxSize = {
.u32Width = 1920,
.u32Height = 1080,
},
},
},
};
struct combo_dev_attr_s pr2020_rx_attr = {
.input_mode = INPUT_MODE_BT656_9B,
.mac_clk = RX_MAC_CLK_200M,
.mclk = {
.cam = 0,
.freq = CAMPLL_FREQ_NONE,
},
.ttl_attr = {
.vi = TTL_VI_SRC_VI1,
.func = {
-1, -1, -1, -1,
0, 1, 2, 3, 4, 5, 6, 7,
-1, -1, -1, -1,
-1, -1, -1, -1,
},
},
.devno = 0,
};
struct combo_dev_attr_s pr2020_rx1_attr = {
.input_mode = INPUT_MODE_BT656_9B,
.mac_clk = RX_MAC_CLK_200M,
.mclk = {
.cam = 1,
.freq = CAMPLL_FREQ_NONE,
},
.ttl_attr = {
.vi = TTL_VI_SRC_VI1,
.func = {
-1, -1, -1, -1,
0, 1, 2, 3, 4, 5, 6, 7,
-1, -1, -1, -1,
-1, -1, -1, -1,
},
},
.devno = 1,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* __PR2020_CMOS_PARAM_H_ */

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