[opensbi] create opensbi from T-Head official:
repo: https://github.com/T-head-Semi/opensbi commit: 89182b257c8798e15e4c685c1af0c2862d528d2a Change-Id: I7b39d66729e0108661a6f4c9e28acbdb303684ea
This commit is contained in:
sam.xiang
196
opensbi/platform/fpga/openpiton/platform.c
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196
opensbi/platform/fpga/openpiton/platform.c
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// SPDX-License-Identifier: BSD-2-Clause
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/*
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_platform.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/uart8250.h>
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#include <sbi_utils/sys/clint.h>
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#define OPENPITON_DEFAULT_UART_ADDR 0xfff0c2c000
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#define OPENPITON_DEFAULT_UART_FREQ 60000000
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#define OPENPITON_DEFAULT_UART_BAUDRATE 115200
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#define OPENPITON_DEFAULT_UART_REG_SHIFT 0
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#define OPENPITON_DEFAULT_UART_REG_WIDTH 1
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#define OPENPITON_DEFAULT_PLIC_ADDR 0xfff1100000
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#define OPENPITON_DEFAULT_PLIC_NUM_SOURCES 2
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#define OPENPITON_DEFAULT_HART_COUNT 3
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#define OPENPITON_DEFAULT_CLINT_ADDR 0xfff1020000
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static struct platform_uart_data uart = {
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OPENPITON_DEFAULT_UART_ADDR,
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OPENPITON_DEFAULT_UART_FREQ,
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OPENPITON_DEFAULT_UART_BAUDRATE,
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};
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static struct plic_data plic = {
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.addr = OPENPITON_DEFAULT_PLIC_ADDR,
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.num_src = OPENPITON_DEFAULT_PLIC_NUM_SOURCES,
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};
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static struct clint_data clint = {
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.addr = OPENPITON_DEFAULT_CLINT_ADDR,
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.first_hartid = 0,
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.hart_count = OPENPITON_DEFAULT_HART_COUNT,
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.has_64bit_mmio = TRUE,
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};
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/*
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* OpenPiton platform early initialization.
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*/
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static int openpiton_early_init(bool cold_boot)
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{
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void *fdt;
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struct platform_uart_data uart_data;
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struct plic_data plic_data;
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unsigned long clint_addr;
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int rc;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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rc = fdt_parse_uart8250(fdt, &uart_data, "ns16550");
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if (!rc)
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uart = uart_data;
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rc = fdt_parse_plic(fdt, &plic_data, "riscv,plic0");
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if (!rc)
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plic = plic_data;
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rc = fdt_parse_compat_addr(fdt, &clint_addr, "riscv,clint0");
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if (!rc)
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clint.addr = clint_addr;
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return 0;
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}
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/*
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* OpenPiton platform final initialization.
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*/
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static int openpiton_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = sbi_scratch_thishart_arg1_ptr();
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fdt_fixups(fdt);
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return 0;
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}
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/*
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* Initialize the openpiton console.
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*/
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static int openpiton_console_init(void)
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{
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return uart8250_init(uart.addr,
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uart.freq,
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uart.baud,
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OPENPITON_DEFAULT_UART_REG_SHIFT,
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OPENPITON_DEFAULT_UART_REG_WIDTH);
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}
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static int plic_openpiton_warm_irqchip_init(int m_cntx_id, int s_cntx_id)
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{
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size_t i, ie_words = plic.num_src / 32 + 1;
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/* By default, enable all IRQs for M-mode of target HART */
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if (m_cntx_id > -1) {
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for (i = 0; i < ie_words; i++)
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plic_set_ie(&plic, m_cntx_id, i, 1);
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}
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/* Enable all IRQs for S-mode of target HART */
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if (s_cntx_id > -1) {
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for (i = 0; i < ie_words; i++)
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plic_set_ie(&plic, s_cntx_id, i, 1);
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}
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/* By default, enable M-mode threshold */
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if (m_cntx_id > -1)
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plic_set_thresh(&plic, m_cntx_id, 1);
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/* By default, disable S-mode threshold */
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if (s_cntx_id > -1)
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plic_set_thresh(&plic, s_cntx_id, 0);
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return 0;
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}
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/*
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* Initialize the openpiton interrupt controller for current HART.
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*/
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static int openpiton_irqchip_init(bool cold_boot)
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{
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u32 hartid = current_hartid();
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int ret;
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if (cold_boot) {
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ret = plic_cold_irqchip_init(&plic);
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if (ret)
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return ret;
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}
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return plic_openpiton_warm_irqchip_init(2 * hartid, 2 * hartid + 1);
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}
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/*
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* Initialize IPI for current HART.
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*/
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static int openpiton_ipi_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = clint_cold_ipi_init(&clint);
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if (ret)
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return ret;
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}
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return clint_warm_ipi_init();
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}
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/*
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* Initialize openpiton timer for current HART.
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*/
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static int openpiton_timer_init(bool cold_boot)
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{
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int ret;
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if (cold_boot) {
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ret = clint_cold_timer_init(&clint, NULL);
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if (ret)
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return ret;
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}
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return clint_warm_timer_init();
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}
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/*
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* Platform descriptor.
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*/
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const struct sbi_platform_operations platform_ops = {
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.early_init = openpiton_early_init,
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.final_init = openpiton_final_init,
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.console_init = openpiton_console_init,
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.irqchip_init = openpiton_irqchip_init,
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.ipi_init = openpiton_ipi_init,
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.timer_init = openpiton_timer_init,
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "OPENPITON RISC-V",
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.features = SBI_PLATFORM_DEFAULT_FEATURES,
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.hart_count = OPENPITON_DEFAULT_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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