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[build] add cvitek build scripts

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Change-Id: If63ce4a669e5d4d72b8e3b9253336dd99bf74c30
This commit is contained in:
sam.xiang
2023-02-23 11:21:38 +08:00
parent cbb030f19f
commit a4f213ceb0
1219 changed files with 149149 additions and 0 deletions
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33
build/boards/default/u-boot/cv180x_qfn_cvi_board_init.c Normal file
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int cvi_board_init(void)
{
#if defined(CV180X_QFN_88_PIN)
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
PINMUX_CONFIG(PAD_MIPI_TXP0, XGPIOC_13);
PINMUX_CONFIG(PAD_MIPI_TXM0, CAM_MCLK1);
#elif defined(CV180X_QFN_88_PIN_38)
//I2C2
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
//CAM_RST0
PINMUX_CONFIG(PAD_MIPI_TXP2, XGPIOC_17);
PINMUX_CONFIG(PAD_MIPI_TXM2, XGPIOC_16);
//CAM_MCLK0
PINMUX_CONFIG(PAD_MIPI_TXP0, CAM_MCLK0);
PINMUX_CONFIG(PAD_MIPI_TXM0, XGPIOC_12);
//IRCUT
//PINMUX_CONFIG(SD1_D2, PWR_GPIO19);
//PINMUX_CONFIG(SD1_D3, PWR_GPIO18);
#elif defined(CV180X_QFN_68_PIN)
PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA);
PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL);
PINMUX_CONFIG(PAD_MIPIRX1N, XGPIOC_8);
PINMUX_CONFIG(PAD_MIPIRX0P, CAM_MCLK0);
//IRCUT
//PINMUX_CONFIG(SD1_D2, PWR_GPIO19);
//PINMUX_CONFIG(SD1_D3, PWR_GPIO18);
#endif
return 0;
}

44
build/boards/default/u-boot/cv180x_wevb_riscv_spinor_defconfig Normal file
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CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv180x_asic"
CONFIG_IDENT_STRING=" cvitek_cv180x"
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_TARGET_CVITEK_CV180X=y
CONFIG_CVITEK_SPI_FLASH=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="cv180x_c906# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
# CONFIG_PHY_SMSC is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_CVITEK_CV182XA=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

12
build/boards/default/u-boot/cv181x_bga_cvi_board_init.c Normal file
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int cvi_board_init(void)
{
PINMUX_CONFIG(CAM_MCLK0, CAM_MCLK0);
PINMUX_CONFIG(IIC2_SCL, IIC2_SCL);
PINMUX_CONFIG(IIC2_SDA, IIC2_SDA);
PINMUX_CONFIG(IIC3_SCL, IIC3_SCL);
PINMUX_CONFIG(IIC3_SDA, IIC3_SDA);
return 0;
}

12
build/boards/default/u-boot/cv181x_qfn_cvi_board_init.c Normal file
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int cvi_board_init(void)
{
PINMUX_CONFIG(IIC0_SCL, CV_SCL0__CR_4WTDI);
PINMUX_CONFIG(IIC0_SDA, CV_SDA0__CR_4WTDO);
PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL);
PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA);
PINMUX_CONFIG(PAD_MIPI_TXP0, XGPIOC_13);
PINMUX_CONFIG(PAD_MIPI_TXM0, CAM_MCLK1);
return 0;
}

45
build/boards/default/u-boot/cv181x_wevb_arm_emmc_defconfig Normal file
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CONFIG_ARM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARMV8_SET_SMPEN=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="cv181x# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
# CONFIG_PHY_SMSC is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_CVITEK_CV182XA=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
CONFIG_ENV_IS_IN_MMC=y

49
build/boards/default/u-boot/cv181x_wevb_arm_spinand_defconfig Normal file
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CONFIG_ARM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARMV8_SET_SMPEN=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="cv181x# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
# CONFIG_SPI_FLASH is not set
# CONFIG_PHY_SMSC is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_CVITEK_CV182XA=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FLASH_CVSNFC_V3=y
CONFIG_ENV_IS_IN_NAND=y

45
build/boards/default/u-boot/cv181x_wevb_arm_spinor_defconfig Normal file
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CONFIG_ARM=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARMV8_SET_SMPEN=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_CVITEK_SPI_FLASH=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="cv181x# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
# CONFIG_PHY_SMSC is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_CVITEK_CV182XA=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

43
build/boards/default/u-boot/cv181x_wevb_riscv_emmc_defconfig Normal file
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CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="cv181x_c906# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
# CONFIG_PHY_SMSC is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_CVITEK_CV182XA=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
CONFIG_ENV_IS_IN_MMC=y

47
build/boards/default/u-boot/cv181x_wevb_riscv_spinand_defconfig Normal file
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CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="cv181x_c906# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
# CONFIG_SPI_FLASH is not set
# CONFIG_PHY_SMSC is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_CVITEK_CV182XA=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_FLASH_CVSNFC_V3=y
CONFIG_ENV_IS_IN_NAND=y

44
build/boards/default/u-boot/cv181x_wevb_riscv_spinor_defconfig Normal file
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CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="cv181x_asic"
CONFIG_IDENT_STRING=" cvitek_cv181x"
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_TARGET_CVITEK_CV181X=y
CONFIG_CVITEK_SPI_FLASH=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="cv181x_c906# "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_CVI_SD_UPDATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_CVITEK=y
CONFIG_MTD=y
# CONFIG_PHY_SMSC is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_PHY_CVITEK_CV182XA=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_LZ4=y
CONFIG_LZMA=y
# CONFIG_TOOLS_LIBCRYPTO is not set
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set

8
build/boards/default/u-boot/cv182x_bga_cvi_board_init.c Normal file
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int cvi_board_init(void)
{
#if defined(CONFIG_MMC_SDHCI_CVITEK_WIFI)
PINMUX_CONFIG(JTAG_CPU_TCK, XGPIOA_18);
PINMUX_CONFIG(PWR_WAKEUP1, PWR_GPIO_7);
#endif
return 0;
}

8
build/boards/default/u-boot/cv182x_qfn_cvi_board_init.c Normal file
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int cvi_board_init(void)
{
#if defined(CONFIG_MMC_SDHCI_CVITEK_WIFI)
PINMUX_CONFIG(PWR_GPIO2, PWR_GPIO_2);
PINMUX_CONFIG(PWR_WAKEUP0, PWR_GPIO_6);
#endif
return 0;
}

20
build/boards/default/u-boot/cvitek_182x.h Normal file
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/*
*VO control GPIOs
*/
#ifdef CONFIG_DISPLAY_CVITEK_MIPI
#define VO_GPIO_RESET_PORT porte
#define VO_GPIO_RESET_INDEX 2
#define VO_GPIO_RESET_ACTIVE GPIO_ACTIVE_LOW
#define VO_GPIO_PWM_PORT porte
#define VO_GPIO_PWM_INDEX 0
#define VO_GPIO_PWM_ACTIVE GPIO_ACTIVE_HIGH
#define VO_GPIO_POWER_CT_PORT porte
#define VO_GPIO_POWER_CT_INDEX 1
#define VO_GPIO_POWER_CT_ACTIVE GPIO_ACTIVE_HIGH
#elif defined(CONFIG_DISPLAY_CVITEK_LVDS)
#define VO_GPIO_PWM_PORT porte
#define VO_GPIO_PWM_INDEX 2
#define VO_GPIO_PWM_ACTIVE GPIO_ACTIVE_HIGH
#endif

13
build/boards/default/u-boot/cvitek_183x.h Normal file
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/*
*VO control GPIOs
*/
#define VO_GPIO_RESET_PORT portb
#define VO_GPIO_RESET_INDEX 5
#define VO_GPIO_RESET_ACTIVE GPIO_ACTIVE_LOW
#define VO_GPIO_PWM_PORT portb
#define VO_GPIO_PWM_INDEX 4
#define VO_GPIO_PWM_ACTIVE GPIO_ACTIVE_HIGH
#define VO_GPIO_POWER_CT_PORT portb
#define VO_GPIO_POWER_CT_INDEX 3
#define VO_GPIO_POWER_CT_ACTIVE GPIO_ACTIVE_HIGH

13
build/boards/default/u-boot/cvitek_cv180x.h Normal file
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/*
*VO control GPIOs
*/
#define VO_GPIO_RESET_PORT portb
#define VO_GPIO_RESET_INDEX 5
#define VO_GPIO_RESET_ACTIVE GPIO_ACTIVE_LOW
#define VO_GPIO_PWM_PORT portb
#define VO_GPIO_PWM_INDEX 4
#define VO_GPIO_PWM_ACTIVE GPIO_ACTIVE_HIGH
#define VO_GPIO_POWER_CT_PORT portb
#define VO_GPIO_POWER_CT_INDEX 3
#define VO_GPIO_POWER_CT_ACTIVE GPIO_ACTIVE_HIGH

13
build/boards/default/u-boot/cvitek_cv181x.h Normal file
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/*
*VO control GPIOs
*/
#define VO_GPIO_RESET_PORT portb
#define VO_GPIO_RESET_INDEX 5
#define VO_GPIO_RESET_ACTIVE GPIO_ACTIVE_LOW
#define VO_GPIO_PWM_PORT portb
#define VO_GPIO_PWM_INDEX 4
#define VO_GPIO_PWM_ACTIVE GPIO_ACTIVE_HIGH
#define VO_GPIO_POWER_CT_PORT portb
#define VO_GPIO_POWER_CT_INDEX 3
#define VO_GPIO_POWER_CT_ACTIVE GPIO_ACTIVE_HIGH