diff --git a/middleware/v2/component/isp/sensor.mk b/middleware/v2/component/isp/sensor.mk index bb076660b..bb49c9149 100644 --- a/middleware/v2/component/isp/sensor.mk +++ b/middleware/v2/component/isp/sensor.mk @@ -6,6 +6,7 @@ sensor-$(CONFIG_SENSOR_GCORE_GC2093) += gcore_gc2093 sensor-$(CONFIG_SENSOR_GCORE_GC2093_SLAVE) += gcore_gc2093_slave sensor-$(CONFIG_SENSOR_GCORE_GC4653) += gcore_gc4653 sensor-$(CONFIG_SENSOR_GCORE_GC4653_SLAVE) += gcore_gc4653_slave +sensor-$(CONFIG_SENSOR_IMGDS_MIS2008) += imgds_mis2008 sensor-$(CONFIG_SENSOR_NEXTCHIP_N5) += nextchip_n5 sensor-$(CONFIG_SENSOR_OV_OS02D10) += ov_os02d10 sensor-$(CONFIG_SENSOR_OV_OS02D10_SLAVE) += ov_os02d10_slave @@ -45,6 +46,7 @@ sensor-$(CONFIG_SENSOR_SONY_IMX335) += sony_imx335 sensor-$(CONFIG_SENSOR_SONY_IMX347) += sony_imx347 sensor-$(CONFIG_SENSOR_SONY_IMX385) += sony_imx385 sensor-$(CONFIG_SENSOR_TECHPOINT_TP2850) += techpoint_tp2850 +sensor-$(CONFIG_SENSOR_TECHPOINT_TP2863) += techpoint_tp2863 sensor-$(CONFIG_SENSOR_VIVO_MCS369) += vivo_mcs369 sensor-$(CONFIG_SENSOR_VIVO_MCS369Q) += vivo_mcs369q sensor-$(CONFIG_SENSOR_VIVO_MM308M2) += vivo_mm308m2 @@ -52,6 +54,7 @@ sensor-$(CONFIG_SENSOR_TECHPOINT_TP2825) += techpoint_tp2825 else ifeq ($(CHIP_ARCH), $(filter $(CHIP_ARCH), CV180X CV181X CV182X)) sensor-$(CONFIG_SENSOR_BRIGATES_BG0808) += brigates_bg0808 sensor-$(CONFIG_SENSOR_GCORE_GC02M1) += gcore_gc02m1 +sensor-$(CONFIG_SENSOR_GCORE_GC0329) += gcore_gc0329 sensor-$(CONFIG_SENSOR_GCORE_GC1054) += gcore_gc1054 sensor-$(CONFIG_SENSOR_GCORE_GC2053) += gcore_gc2053 sensor-$(CONFIG_SENSOR_GCORE_GC2053_SLAVE) += gcore_gc2053_slave @@ -60,6 +63,7 @@ sensor-$(CONFIG_SENSOR_GCORE_GC2093) += gcore_gc2093 sensor-$(CONFIG_SENSOR_GCORE_GC2145) += gcore_gc2145 sensor-$(CONFIG_SENSOR_GCORE_GC4023) += gcore_gc4023 sensor-$(CONFIG_SENSOR_GCORE_GC4653) += gcore_gc4653 +sensor-$(CONFIG_SENSOR_IMGDS_MIS2008) += imgds_mis2008 sensor-$(CONFIG_SENSOR_NEXTCHIP_N5) += nextchip_n5 sensor-$(CONFIG_SENSOR_NEXTCHIP_N6) += nextchip_n6 sensor-$(CONFIG_SENSOR_OV_OS04A10) += ov_os04a10 @@ -103,6 +107,7 @@ sensor-$(CONFIG_SENSOR_SONY_IMX327_FPGA) += sony_imx327_fpga sensor-$(CONFIG_SENSOR_SONY_IMX327_SUBLVDS) += sony_imx327_sublvds sensor-$(CONFIG_SENSOR_SONY_IMX335) += sony_imx335 sensor-$(CONFIG_SENSOR_TECHPOINT_TP2825) += techpoint_tp2825 +sensor-$(CONFIG_SENSOR_TECHPOINT_TP2863) += techpoint_tp2863 else $(error not supported chip arch cv180x/cv181x/cv182x/cv183x) endif diff --git a/middleware/v2/component/isp/sensor/cv180x/Makefile b/middleware/v2/component/isp/sensor/cv180x/Makefile index df18c95bc..815ace8d6 100644 --- a/middleware/v2/component/isp/sensor/cv180x/Makefile +++ b/middleware/v2/component/isp/sensor/cv180x/Makefile @@ -29,6 +29,9 @@ brigates_bg0808: gcore_gc02m1: $(call MAKE_SENSOR, ${@}) +gcore_gc0329: + $(call MAKE_SENSOR, ${@}) + gcore_gc1054: $(call MAKE_SENSOR, ${@}) @@ -53,6 +56,9 @@ gcore_gc4023: gcore_gc4653: $(call MAKE_SENSOR, ${@}) +imgds_mis2008: + $(call MAKE_SENSOR, ${@}) + nextchip_n5: $(call MAKE_SENSOR, ${@}) @@ -181,6 +187,9 @@ sony_imx335: techpoint_tp2825: $(call MAKE_SENSOR, ${@}) + +techpoint_tp2863: + $(call MAKE_SENSOR, ${@}) all_sensor: @$(MAKE) -f Makefile_full || exit 1; diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/Makefile b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/Makefile new file mode 100644 index 000000000..5bbcfd07f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_gc0329.a +TARGET_SO = $(MW_LIB)/libsns_gc0329.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos.c b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos.c new file mode 100644 index 000000000..5b5a220dd --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos.c @@ -0,0 +1,303 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "gc0329_cmos_ex.h" +#include "gc0329_cmos_param.h" + +#define GC0329_ID 0xc0 +#define GC0329_I2C_ADDR_1 0x31 +#define GC0329_I2C_ADDR_IS_VALID(addr) ((addr) == GC0329_I2C_ADDR_1) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastGc0329[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define GC0329_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc0329[dev]) +#define GC0329_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc0329[dev] = pstCtx) +#define GC0329_SENSOR_RESET_CTX(dev) (g_pastGc0329[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunGc0329_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +#define GC0329_RES_IS_480P(w, h) ((w) == 640 && (h) == 480) + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const GC0329_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astGc0329_mode; + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstCfg0 = &pstSnsState->astSyncInfo[0]; + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 10) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (GC0329_RES_IS_480P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) + u8SensorImageMode = GC0329_MODE_640X480P10; + else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps); + return CVI_FAILURE; + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = GC0329_MODE_640X480P10; + pstSnsState->enWDRMode = WDR_MODE_NONE; +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &gc0329_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astGc0329_mode.stImg.stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astGc0329_mode.stImg.stSnsSize.u32Height; + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc0329_rx_attr; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = gc0329_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = gc0329_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (GC0329_I2C_ADDR_IS_VALID(s32I2cAddr)) + gc0329_i2c_addr = s32I2cAddr; +} + +static CVI_S32 gc0329_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunGc0329_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + GC0329_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + GC0329_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + (void) pstAeLib; + (void) pstAwbLib; + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = GC0329_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + (void) pstAeLib; + (void) pstAwbLib; + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC0329_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return gc0329_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsGc0329_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = CVI_NULL, + .pfnRestart = CVI_NULL, + .pfnWriteReg = gc0329_write_register, + .pfnReadReg = gc0329_read_register, + .pfnSetBusInfo = gc0329_set_bus_info, + .pfnSetInit = CVI_NULL, + .pfnMirrorFlip = CVI_NULL, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = CVI_NULL, + .pfnSnsProbe = sensor_probe, +}; diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos_ex.h new file mode 100644 index 000000000..9ad3c8be1 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos_ex.h @@ -0,0 +1,64 @@ +#ifndef __GC0329_CMOS_EX_H_ +#define __GC0329_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +typedef enum _GC0329_MODE_E { + GC0329_MODE_640X480P10 = 0, + GC0329_MODE_NUM +} GC0329_SLAVE_MODE_E; + +typedef struct _GC0329_MODE_S { + ISP_WDR_SIZE_S stImg; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp; + SNS_ATTR_LARGE_S stAgain; + SNS_ATTR_LARGE_S stDgain; + char name[64]; +} GC0329_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastGc0329[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunGc0329_BusInfo[]; +extern CVI_U8 gc0329_i2c_addr; +extern const CVI_U32 gc0329_addr_byte; +extern const CVI_U32 gc0329_data_byte; +extern void gc0329_init(VI_PIPE ViPipe); +extern void gc0329_exit(VI_PIPE ViPipe); +extern void gc0329_standby(VI_PIPE ViPipe); +extern void gc0329_restart(VI_PIPE ViPipe); +extern int gc0329_write_register(VI_PIPE ViPipe, int addr, int data); +extern int gc0329_read_register(VI_PIPE ViPipe, int addr); +extern void gc0329_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int gc0329_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC0329_CMOS_EX_H_ */ + diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos_param.h new file mode 100644 index 000000000..56a42de3f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_cmos_param.h @@ -0,0 +1,71 @@ +#ifndef __GC0329_CMOS_PARAM_H_ +#define __GC0329_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc0329_cmos_ex.h" + +static const GC0329_MODE_S g_astGc0329_mode = { + .name = "640X480P10", + .stImg = { + .stSnsSize = { + .u32Width = 640, + .u32Height = 480, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 640, + .u32Height = 480, + }, + .stMaxSize = { + .u32Width = 640, + .u32Height = 480, + }, + }, +}; + +struct combo_dev_attr_s gc0329_rx_attr = { + .input_mode = INPUT_MODE_BT601, + .mac_clk = RX_MAC_CLK_200M, + .ttl_attr = { + .vi = TTL_VI_SRC_VI0, + .ttl_fmt = TTL_VSDE_11B, + .raw_data_type = RAW_DATA_8BIT, + .func = { + 8, -1, -1, 12, + 0, 1, 2, 3, + 4, 13, 14, 11, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_24M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC0329_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_sensor_ctl.c new file mode 100644 index 000000000..1bdd8753b --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc0329/gc0329_sensor_ctl.c @@ -0,0 +1,464 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc0329_cmos_ex.h" + +static void gc0329_linear_480p10_init(VI_PIPE ViPipe); + +CVI_U8 gc0329_i2c_addr = 0x31;//0x78 +const CVI_U32 gc0329_addr_byte = 1; +const CVI_U32 gc0329_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int gc0329_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunGc0329_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc0329_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int gc0329_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int gc0329_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (gc0329_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, gc0329_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, gc0329_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (gc0329_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + + +int gc0329_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (gc0329_addr_byte == 1) { + buf[idx] = addr & 0xff; + idx++; + } + if (gc0329_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, gc0329_addr_byte + gc0329_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } +// syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +#define GC0329_CHIP_ID_ADDR 0x00 +#define GC0329_CHIP_ID 0xc0 + +int gc0329_probe(VI_PIPE ViPipe) +{ + int nVal; + + usleep(50); + if (gc0329_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + gc0329_write_register(ViPipe, 0xfc, 0x16); + nVal = gc0329_read_register(ViPipe, GC0329_CHIP_ID_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + + if ((nVal & 0xFF) != GC0329_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + printf("%d\n", ViPipe); + return CVI_SUCCESS; +} + +void gc0329_init(VI_PIPE ViPipe) +{ + gc0329_i2c_init(ViPipe); + + gc0329_linear_480p10_init(ViPipe); + + g_pastGc0329[ViPipe]->bInit = CVI_TRUE; +} + +void gc0329_exit(VI_PIPE ViPipe) +{ + gc0329_i2c_exit(ViPipe); +} + +static void gc0329_linear_480p10_init(VI_PIPE ViPipe) +{ + gc0329_write_register(ViPipe, 0xfe, 0x80); + gc0329_write_register(ViPipe, 0xfc, 0x16); + gc0329_write_register(ViPipe, 0xfc, 0x16); + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0x70, 0x48); + gc0329_write_register(ViPipe, 0x73, 0x90); + gc0329_write_register(ViPipe, 0x74, 0x80); + gc0329_write_register(ViPipe, 0x75, 0x80); + gc0329_write_register(ViPipe, 0x76, 0x94); + gc0329_write_register(ViPipe, 0x77, 0x62); + gc0329_write_register(ViPipe, 0x78, 0x47); + gc0329_write_register(ViPipe, 0x79, 0x40); + + gc0329_write_register(ViPipe, 0x03, 0x02); + gc0329_write_register(ViPipe, 0x04, 0x40); + + gc0329_write_register(ViPipe, 0xfc, 0x16); + gc0329_write_register(ViPipe, 0x09, 0x00); + gc0329_write_register(ViPipe, 0x0a, 0x02); + gc0329_write_register(ViPipe, 0x0b, 0x00); + gc0329_write_register(ViPipe, 0x0c, 0x02); + gc0329_write_register(ViPipe, 0x17, 0x14); + gc0329_write_register(ViPipe, 0x19, 0x05); + gc0329_write_register(ViPipe, 0x1b, 0x24); + gc0329_write_register(ViPipe, 0x1c, 0x04); + gc0329_write_register(ViPipe, 0x1e, 0x08); + gc0329_write_register(ViPipe, 0x1f, 0x08); + gc0329_write_register(ViPipe, 0x20, 0x01); + gc0329_write_register(ViPipe, 0x21, 0x48); + gc0329_write_register(ViPipe, 0x22, 0xba); + gc0329_write_register(ViPipe, 0x23, 0x22); + gc0329_write_register(ViPipe, 0x24, 0x16); + + gc0329_write_register(ViPipe, 0x26, 0xf7); + gc0329_write_register(ViPipe, 0x28, 0x7f); + gc0329_write_register(ViPipe, 0x29, 0x00); + gc0329_write_register(ViPipe, 0x32, 0x00); + gc0329_write_register(ViPipe, 0x33, 0x20); + gc0329_write_register(ViPipe, 0x34, 0x20); + gc0329_write_register(ViPipe, 0x35, 0x20); + gc0329_write_register(ViPipe, 0x36, 0x20); + + gc0329_write_register(ViPipe, 0x3b, 0x04); + gc0329_write_register(ViPipe, 0x3c, 0x04); + gc0329_write_register(ViPipe, 0x3d, 0x04); + gc0329_write_register(ViPipe, 0x3e, 0x04); + + gc0329_write_register(ViPipe, 0x40, 0xff); + gc0329_write_register(ViPipe, 0x41, 0x24); + gc0329_write_register(ViPipe, 0x42, 0xfa); + gc0329_write_register(ViPipe, 0x46, 0x02); + gc0329_write_register(ViPipe, 0x4b, 0xca); + gc0329_write_register(ViPipe, 0x4d, 0x01); + gc0329_write_register(ViPipe, 0x4f, 0x01); + gc0329_write_register(ViPipe, 0x70, 0x48); + + gc0329_write_register(ViPipe, 0x80, 0x07); + gc0329_write_register(ViPipe, 0x81, 0xc2); + gc0329_write_register(ViPipe, 0x82, 0x90); + gc0329_write_register(ViPipe, 0x83, 0x05); + gc0329_write_register(ViPipe, 0x87, 0x40); + + gc0329_write_register(ViPipe, 0x90, 0x8c); + gc0329_write_register(ViPipe, 0x92, 0x05); + gc0329_write_register(ViPipe, 0x94, 0x05); + gc0329_write_register(ViPipe, 0x95, 0x45); + gc0329_write_register(ViPipe, 0x96, 0x88); + + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0x18, 0x22); + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0x9c, 0x0a); + gc0329_write_register(ViPipe, 0xa0, 0xaf); + gc0329_write_register(ViPipe, 0xa2, 0xff); + gc0329_write_register(ViPipe, 0xa4, 0x30); + gc0329_write_register(ViPipe, 0xa5, 0x31); + gc0329_write_register(ViPipe, 0xa7, 0x35); + + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0xbf, 0x0b); + gc0329_write_register(ViPipe, 0xc0, 0x1d); + gc0329_write_register(ViPipe, 0xc1, 0x33); + gc0329_write_register(ViPipe, 0xc2, 0x49); + gc0329_write_register(ViPipe, 0xc3, 0x5d); + gc0329_write_register(ViPipe, 0xc4, 0x6e); + gc0329_write_register(ViPipe, 0xc5, 0x7c); + gc0329_write_register(ViPipe, 0xc6, 0x99); + gc0329_write_register(ViPipe, 0xc7, 0xaf); + gc0329_write_register(ViPipe, 0xc8, 0xc2); + gc0329_write_register(ViPipe, 0xc9, 0xd0); + gc0329_write_register(ViPipe, 0xca, 0xda); + gc0329_write_register(ViPipe, 0xcb, 0xe2); + gc0329_write_register(ViPipe, 0xcc, 0xe7); + gc0329_write_register(ViPipe, 0xcd, 0xf0); + gc0329_write_register(ViPipe, 0xce, 0xf7); + gc0329_write_register(ViPipe, 0xcf, 0xff); + + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0x63, 0x00); + gc0329_write_register(ViPipe, 0x64, 0x06); + gc0329_write_register(ViPipe, 0x65, 0x0d); + gc0329_write_register(ViPipe, 0x66, 0x1b); + gc0329_write_register(ViPipe, 0x67, 0x2b); + gc0329_write_register(ViPipe, 0x68, 0x3d); + gc0329_write_register(ViPipe, 0x69, 0x50); + gc0329_write_register(ViPipe, 0x6a, 0x60); + gc0329_write_register(ViPipe, 0x6b, 0x80); + gc0329_write_register(ViPipe, 0x6c, 0xa0); + gc0329_write_register(ViPipe, 0x6d, 0xc0); + gc0329_write_register(ViPipe, 0x6e, 0xe0); + gc0329_write_register(ViPipe, 0x6f, 0xff); + + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0xb3, 0x44); + gc0329_write_register(ViPipe, 0xb4, 0xfd); + gc0329_write_register(ViPipe, 0xb5, 0x02); + gc0329_write_register(ViPipe, 0xb6, 0xfa); + gc0329_write_register(ViPipe, 0xb7, 0x48); + gc0329_write_register(ViPipe, 0xb8, 0xf0); + gc0329_write_register(ViPipe, 0x50, 0x01); + + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0xd0, 0x40); + gc0329_write_register(ViPipe, 0xd1, 0x28); + gc0329_write_register(ViPipe, 0xd2, 0x28); + gc0329_write_register(ViPipe, 0xd3, 0x40); + gc0329_write_register(ViPipe, 0xd5, 0x00); + gc0329_write_register(ViPipe, 0xdd, 0x14); + gc0329_write_register(ViPipe, 0xde, 0x34); + + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0x10, 0x40); + gc0329_write_register(ViPipe, 0x11, 0x21); + gc0329_write_register(ViPipe, 0x12, 0x13); + gc0329_write_register(ViPipe, 0x13, 0x50); + gc0329_write_register(ViPipe, 0x17, 0xa8); + gc0329_write_register(ViPipe, 0x1a, 0x21); + gc0329_write_register(ViPipe, 0x20, 0x31); + gc0329_write_register(ViPipe, 0x21, 0xc0); + gc0329_write_register(ViPipe, 0x22, 0x60); + gc0329_write_register(ViPipe, 0x3c, 0x50); + gc0329_write_register(ViPipe, 0x3d, 0x40); + gc0329_write_register(ViPipe, 0x3e, 0x45); + + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0x06, 0x12); + gc0329_write_register(ViPipe, 0x07, 0x06); + gc0329_write_register(ViPipe, 0x08, 0x9c); + gc0329_write_register(ViPipe, 0x09, 0xee); + gc0329_write_register(ViPipe, 0x50, 0xfc); + gc0329_write_register(ViPipe, 0x51, 0x28); + gc0329_write_register(ViPipe, 0x52, 0x10); + gc0329_write_register(ViPipe, 0x53, 0x20); + gc0329_write_register(ViPipe, 0x54, 0x12); + gc0329_write_register(ViPipe, 0x55, 0x16); + gc0329_write_register(ViPipe, 0x56, 0x30); + gc0329_write_register(ViPipe, 0x58, 0x60); + gc0329_write_register(ViPipe, 0x59, 0x08); + gc0329_write_register(ViPipe, 0x5a, 0x02); + gc0329_write_register(ViPipe, 0x5b, 0x63); + gc0329_write_register(ViPipe, 0x5c, 0x35); + gc0329_write_register(ViPipe, 0x5d, 0x72); + gc0329_write_register(ViPipe, 0x5e, 0x11); + gc0329_write_register(ViPipe, 0x5f, 0x40); + gc0329_write_register(ViPipe, 0x60, 0x40); + gc0329_write_register(ViPipe, 0x61, 0xc8); + gc0329_write_register(ViPipe, 0x62, 0xa0); + gc0329_write_register(ViPipe, 0x63, 0x40); + gc0329_write_register(ViPipe, 0x64, 0x50); + gc0329_write_register(ViPipe, 0x65, 0x98); + gc0329_write_register(ViPipe, 0x66, 0xfa); + gc0329_write_register(ViPipe, 0x67, 0x80); + gc0329_write_register(ViPipe, 0x68, 0x60); + gc0329_write_register(ViPipe, 0x69, 0x90); + gc0329_write_register(ViPipe, 0x6a, 0x40); + gc0329_write_register(ViPipe, 0x6b, 0x39); + gc0329_write_register(ViPipe, 0x6c, 0x30); + gc0329_write_register(ViPipe, 0x6d, 0x60); + gc0329_write_register(ViPipe, 0x6e, 0x41); + gc0329_write_register(ViPipe, 0x70, 0x10); + gc0329_write_register(ViPipe, 0x71, 0x00); + gc0329_write_register(ViPipe, 0x72, 0x10); + gc0329_write_register(ViPipe, 0x73, 0x40); + gc0329_write_register(ViPipe, 0x80, 0x60); + gc0329_write_register(ViPipe, 0x81, 0x50); + gc0329_write_register(ViPipe, 0x82, 0x42); + gc0329_write_register(ViPipe, 0x83, 0x40); + gc0329_write_register(ViPipe, 0x84, 0x40); + gc0329_write_register(ViPipe, 0x85, 0x40); + gc0329_write_register(ViPipe, 0x74, 0x40); + gc0329_write_register(ViPipe, 0x75, 0x58); + gc0329_write_register(ViPipe, 0x76, 0x24); + gc0329_write_register(ViPipe, 0x77, 0x40); + gc0329_write_register(ViPipe, 0x78, 0x20); + gc0329_write_register(ViPipe, 0x79, 0x60); + gc0329_write_register(ViPipe, 0x7a, 0x58); + gc0329_write_register(ViPipe, 0x7b, 0x20); + gc0329_write_register(ViPipe, 0x7c, 0x30); + gc0329_write_register(ViPipe, 0x7d, 0x35); + gc0329_write_register(ViPipe, 0x7e, 0x10); + gc0329_write_register(ViPipe, 0x7f, 0x08); + + gc0329_write_register(ViPipe, 0x9c, 0x00); + gc0329_write_register(ViPipe, 0x9e, 0xc0); + gc0329_write_register(ViPipe, 0x9f, 0x40); + + gc0329_write_register(ViPipe, 0xd0, 0x00); + gc0329_write_register(ViPipe, 0xd2, 0x2c); + gc0329_write_register(ViPipe, 0xd3, 0x80); + + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0xc0, 0x0b); + gc0329_write_register(ViPipe, 0xc1, 0x07); + gc0329_write_register(ViPipe, 0xc2, 0x05); + gc0329_write_register(ViPipe, 0xc6, 0x0b); + gc0329_write_register(ViPipe, 0xc7, 0x07); + gc0329_write_register(ViPipe, 0xc8, 0x05); + gc0329_write_register(ViPipe, 0xba, 0x39); + gc0329_write_register(ViPipe, 0xbb, 0x24); + gc0329_write_register(ViPipe, 0xbc, 0x23); + gc0329_write_register(ViPipe, 0xb4, 0x39); + gc0329_write_register(ViPipe, 0xb5, 0x24); + gc0329_write_register(ViPipe, 0xb6, 0x23); + gc0329_write_register(ViPipe, 0xc3, 0x00); + gc0329_write_register(ViPipe, 0xc4, 0x00); + gc0329_write_register(ViPipe, 0xc5, 0x00); + gc0329_write_register(ViPipe, 0xc9, 0x00); + gc0329_write_register(ViPipe, 0xca, 0x00); + gc0329_write_register(ViPipe, 0xcb, 0x00); + gc0329_write_register(ViPipe, 0xbd, 0x2b); + gc0329_write_register(ViPipe, 0xbe, 0x00); + gc0329_write_register(ViPipe, 0xbf, 0x00); + gc0329_write_register(ViPipe, 0xb7, 0x09); + gc0329_write_register(ViPipe, 0xb8, 0x00); + gc0329_write_register(ViPipe, 0xb9, 0x00); + gc0329_write_register(ViPipe, 0xa8, 0x31); + gc0329_write_register(ViPipe, 0xa9, 0x23); + gc0329_write_register(ViPipe, 0xaa, 0x20); + gc0329_write_register(ViPipe, 0xab, 0x31); + gc0329_write_register(ViPipe, 0xac, 0x23); + gc0329_write_register(ViPipe, 0xad, 0x20); + gc0329_write_register(ViPipe, 0xae, 0x31); + gc0329_write_register(ViPipe, 0xaf, 0x23); + gc0329_write_register(ViPipe, 0xb0, 0x20); + gc0329_write_register(ViPipe, 0xb1, 0x31); + gc0329_write_register(ViPipe, 0xb2, 0x23); + gc0329_write_register(ViPipe, 0xb3, 0x20); + gc0329_write_register(ViPipe, 0xa4, 0x00); + gc0329_write_register(ViPipe, 0xa5, 0x00); + gc0329_write_register(ViPipe, 0xa6, 0x00); + gc0329_write_register(ViPipe, 0xa7, 0x00); + gc0329_write_register(ViPipe, 0xa1, 0x3c); + gc0329_write_register(ViPipe, 0xa2, 0x50); + gc0329_write_register(ViPipe, 0xfe, 0x00); + + gc0329_write_register(ViPipe, 0x05, 0x02); + gc0329_write_register(ViPipe, 0x06, 0x2c); + gc0329_write_register(ViPipe, 0x07, 0x00); + gc0329_write_register(ViPipe, 0x08, 0xb8); + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0x29, 0x00); + gc0329_write_register(ViPipe, 0x2a, 0x60); + gc0329_write_register(ViPipe, 0x2b, 0x02); + gc0329_write_register(ViPipe, 0x2c, 0xa0); + gc0329_write_register(ViPipe, 0x2d, 0x03); + gc0329_write_register(ViPipe, 0x2e, 0x00); + gc0329_write_register(ViPipe, 0x2f, 0x03); + gc0329_write_register(ViPipe, 0x30, 0xc0); + gc0329_write_register(ViPipe, 0x31, 0x05); + gc0329_write_register(ViPipe, 0x32, 0x40); + gc0329_write_register(ViPipe, 0xfe, 0x00); + + gc0329_write_register(ViPipe, 0x44, 0xa2); + gc0329_write_register(ViPipe, 0xf0, 0x07); + gc0329_write_register(ViPipe, 0xf1, 0x01); + + delay_ms(50); + + printf("ViPipe:%d,===GC0329 480P 10fps YUV Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_cmos.c b/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_cmos.c index 3d21b6093..ae5120a40 100644 --- a/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_cmos.c +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_cmos.c @@ -28,6 +28,10 @@ #define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) #define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) #define GC2093_ID 2093 +#define GC2093_I2C_ADDR_1 0x7e +#define GC2093_I2C_ADDR_2 0x37 +#define GC2093_I2C_ADDR_IS_VALID(addr) ((addr) == GC2093_I2C_ADDR_1 || (addr) == GC2093_I2C_ADDR_2) + /**************************************************************************** * global variables * ***************************************************************************/ @@ -1040,6 +1044,11 @@ static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExp /**************************************************************************** * callback structure * ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (GC2093_I2C_ADDR_IS_VALID(s32I2cAddr)) + gc2093_i2c_addr = s32I2cAddr; +} static CVI_S32 gc2093_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) { @@ -1185,6 +1194,7 @@ ISP_SNS_OBJ_S stSnsGc2093_Obj = { .pfnSetInit = sensor_set_init, .pfnMirrorFlip = sensor_mirror_flip, .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, .pfnGetRxAttr = sensor_rx_attr, .pfnExpSensorCb = cmos_init_sensor_exp_function, .pfnExpAeCb = cmos_init_ae_exp_function, diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_cmos_ex.h index d0f8c9869..eeae66b10 100644 --- a/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_cmos_ex.h +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_cmos_ex.h @@ -93,7 +93,7 @@ typedef struct _GC2093_MODE_S { extern ISP_SNS_STATE_S *g_pastGc2093[VI_MAX_PIPE_NUM]; extern ISP_SNS_COMMBUS_U g_aunGc2093_BusInfo[]; extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2093_MirrorFip[VI_MAX_PIPE_NUM]; -extern const CVI_U8 gc2093_i2c_addr; +extern CVI_U8 gc2093_i2c_addr; extern const CVI_U32 gc2093_addr_byte; extern const CVI_U32 gc2093_data_byte; extern void gc2093_init(VI_PIPE ViPipe); diff --git a/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_sensor_ctl.c index c8ce2cfa2..8b73a2f78 100644 --- a/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_sensor_ctl.c +++ b/middleware/v2/component/isp/sensor/cv180x/gcore_gc2093/gc2093_sensor_ctl.c @@ -20,7 +20,7 @@ static void gc2093_linear_1080p30_init(VI_PIPE ViPipe); static void gc2093_wdr_1080p30_init(VI_PIPE ViPipe); -const CVI_U8 gc2093_i2c_addr = 0x37;//0x6e +CVI_U8 gc2093_i2c_addr = 0x37;//0x6e const CVI_U32 gc2093_addr_byte = 2; const CVI_U32 gc2093_data_byte = 1; static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; diff --git a/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/Makefile b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/Makefile new file mode 100644 index 000000000..f0e1a4748 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_mis2008.a +TARGET_SO = $(MW_LIB)/libsns_mis2008.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos.c b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos.c new file mode 100644 index 000000000..1cec562bb --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos.c @@ -0,0 +1,1042 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "mis2008_cmos_ex.h" +#include "mis2008_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define MIS2008_ID 2008 +#define SENSOR_MIS2008_WIDTH 1920 +#define SENSOR_MIS2008_HEIGHT 1080 +#define MIS2008_I2C_ADDR_1 0x30 +#define MIS2008_I2C_ADDR_2 0x32 +#define MIS2008_I2C_ADDR_IS_VALID(addr) ((addr) == MIS2008_I2C_ADDR_1 || (addr) == MIS2008_I2C_ADDR_2) + +#define MIS2008_EXPACCURACY (1) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastMIS2008[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define MIS2008_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastMIS2008[dev]) +#define MIS2008_SENSOR_SET_CTX(dev, pstCtx) (g_pastMIS2008[dev] = pstCtx) +#define MIS2008_SENSOR_RESET_CTX(dev) (g_pastMIS2008[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunMIS2008_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16MIS2008_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16MIS2008_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +ISP_SNS_MIRRORFLIP_TYPE_E g_aeMis2008_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****MIS2008 Lines Range*****/ +#define MIS2008_FULL_LINES_MAX (0xFFFF) + +/*****MIS2008 Register Address*****/ +#define MIS2008_EXP_ADDR 0x3100 +#define MIS2008_AGAIN_ADDR 0x3102 +#define MIS2008_DGAIN_ADDR 0x3700 +#define MIS2008_VMAX_ADDR 0x3200 +#define MIS2008_FLIP_MIRROR_ADDR 0x3007 + +#define MIS2008_RES_IS_1080P(w, h) ((w) == 1920 && (h) == 1080) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = MIS2008_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = MIS2008_EXPACCURACY; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = g_astMIS2008_mode[pstSnsState->u8ImgMode].f32MaxFps; + pstAeSnsDft->f32MinFps = g_astMIS2008_mode[pstSnsState->u8ImgMode].f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = g_astMIS2008_mode[pstSnsState->u8ImgMode].stAgain[0].u32Max; + pstAeSnsDft->u32MinAgain = g_astMIS2008_mode[pstSnsState->u8ImgMode].stAgain[0].u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = g_astMIS2008_mode[pstSnsState->u8ImgMode].stDgain[0].u32Max; + pstAeSnsDft->u32MinDgain = g_astMIS2008_mode[pstSnsState->u8ImgMode].stDgain[0].u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = g_astMIS2008_mode[pstSnsState->u8ImgMode].stExp[0].u32Max; + pstAeSnsDft->u32MinIntTime = g_astMIS2008_mode[pstSnsState->u8ImgMode].stExp[0].u32Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astMIS2008_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astMIS2008_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astMIS2008_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case MIS2008_MODE_1080P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > MIS2008_FULL_LINES_MAX) ? MIS2008_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + //frame high addr + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_ADDR].u32Data = ((u32VMAX & 0xFF00)>>8);//data[15:8] => [7:0] //h + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_ADDR].u32Data = (u32VMAX & 0xFF);//data[7:0] [7:0] //l + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = (pstSnsState->u32FLStd << 1) - 8; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32TmpIntTime, u32MinTime, u32MaxTime; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + /* linear exposure reg range: + * min : 1 + * max : vts - 1 + * step : 1 + */ + u32MinTime = 1; + u32MaxTime = pstSnsState->au32FL[0] - 1; + u32TmpIntTime = (u32IntTime[0] > u32MaxTime) ? u32MaxTime : u32IntTime[0]; + u32TmpIntTime = (u32TmpIntTime < u32MinTime) ? u32MinTime : u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_ADDR].u32Data = ((u32TmpIntTime & 0xFF00) >> 8); //data[15:8] => [7:0] //h + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_ADDR].u32Data = ((u32TmpIntTime & 0xFF)); //data[7:0] [7:0] //l + + return CVI_SUCCESS; +} + +struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +}; + +static struct gain_tbl_info_s DgainInfo[] = { + { + .gainMax = 1984, + .idxBase = 0, + .regGain = 0x01, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 3008, + .idxBase = 16, + .regGain = 0x02, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x03, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 5056, + .idxBase = 48, + .regGain = 0x04, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 6080, + .idxBase = 64, + .regGain = 0x05, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 7104, + .idxBase = 80, + .regGain = 0x06, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 8128, + .idxBase = 96, + .regGain = 0x07, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 9152, + .idxBase = 112, + .regGain = 0x08, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 10176, + .idxBase = 128, + .regGain = 0x09, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 11200, + .idxBase = 144, + .regGain = 0x0a, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 12224, + .idxBase = 160, + .regGain = 0x0b, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 13248, + .idxBase = 176, + .regGain = 0x0c, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 14272, + .idxBase = 192, + .regGain = 0x0d, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 15296, + .idxBase = 208, + .regGain = 0x0e, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 16320, + .idxBase = 224, + .regGain = 0x0f, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, +}; + +static CVI_U32 Dgain_table[] = { + 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792, 1856, 1920, + 1984, 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, 2880, + 2944, 3008, 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, 3776, 3840, + 3904, 3968, 4032, 4096, 4160, 4224, 4288, 4352, 4416, 4480, 4544, 4608, 4672, 4736, 4800, + 4864, 4928, 4992, 5056, 5120, 5184, 5248, 5312, 5376, 5440, 5504, 5568, 5632, 5696, 5760, + 5824, 5888, 5952, 6016, 6080, 6144, 6208, 6272, 6336, 6400, 6464, 6528, 6592, 6656, 6720, + 6784, 6848, 6912, 6976, 7040, 7104, 7168, 7232, 7296, 7360, 7424, 7488, 7552, 7616, 7680, + 7744, 7808, 7872, 7936, 8000, 8064, 8128, 8192, 8256, 8320, 8384, 8448, 8512, 8576, 8640, + 8704, 8768, 8832, 8896, 8960, 9024, 9088, 9152, 9216, 9280, 9344, 9408, 9472, 9536, 9600, + 9664, 9728, 9792, 9856, 9920, 9984, 10048, 10112, 10176, 10240, 10304, 10368, 10432, 10496, + 10560, 10624, 10688, 10752, 10816, 10880, 10944, 11008, 11072, 11136, 11200, 11264, 11328, + 11392, 11456, 11520, 11584, 11648, 11712, 11776, 11840, 11904, 11968, 12032, 12096, 12160, + 12224, 12288, 12352, 12416, 12480, 12544, 12608, 12672, 12736, 12800, 12864, 12928, 12992, + 13056, 13120, 13184, 13248, 13312, 13376, 13440, 13504, 13568, 13632, 13696, 13760, 13824, + 13888, 13952, 14016, 14080, 14144, 14208, 14272, 14336, 14400, 14464, 14528, 14592, 14656, + 14720, 14784, 14848, 14912, 14976, 15040, 15104, 15168, 15232, 15296, 15360, 15424, 15488, + 15552, 15616, 15680, 15744, 15808, 15872, 15936, 16000, 16064, 16128, 16192, 16256, 16320 +}; + +static CVI_U32 Again_table[] = { + 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, + 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, + 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, + 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, + 4096, 4224, 4352, 4480, 4608, 4736, 4864, 4992, 5120, 5248, 5376, 5504, 5632, 5760, 5888, 6016, + 6144, 6272, 6400, 6528, 6656, 6784, 6912, 7040, 7168, 7296, 7424, 7552, 7680, 7808, 7936, 8064, + 8192, 8448, 8704, 8960, 9216, 9472, 9728, 9984, 10240,10496,10752,11008,11264,11520,11776,12032, + 12288,12544,12800,13056,13312,13568,13824,14080,14336,14592,14848,15104,15360,15616,15872,16128 +}; + +static const CVI_U32 again_table_size = ARRAY_SIZE(Again_table); +static const CVI_U32 dgain_table_size = ARRAY_SIZE(Dgain_table); + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= Again_table[again_table_size - 1]) { + *pu32AgainLin = Again_table[again_table_size - 1]; + *pu32AgainDb = again_table_size - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < again_table_size; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 i; + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[dgain_table_size - 1]) { + *pu32DgainLin = Dgain_table[dgain_table_size - 1]; + *pu32DgainDb = dgain_table_size - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < dgain_table_size; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_ADDR].u32Data = (u32Again & 0x7F); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_ADDR].u32Data = ((info->regGain & 0x0e)>>1); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_D_FINEGAIN_ADDR].u32Data =((info->regGain & 0x01)<<7) | ((u32Dgain & 0x0F)<<3); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + //pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + //pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const MIS2008_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astMIS2008_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = MIS2008_MODE_1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astMIS2008_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunMIS2008_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = mis2008_i2c_addr; + pstI2c_data[i].u32AddrByteNum = mis2008_addr_byte; + pstI2c_data[i].u32DataByteNum = mis2008_data_byte; + } + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + //Linear Mode Regs + pstI2c_data[LINEAR_SHS1_0_ADDR].u32RegAddr = MIS2008_EXP_ADDR; + pstI2c_data[LINEAR_SHS1_1_ADDR].u32RegAddr = MIS2008_EXP_ADDR + 1; + + pstI2c_data[LINEAR_AGAIN_ADDR].u32RegAddr = MIS2008_AGAIN_ADDR; + pstI2c_data[LINEAR_DGAIN_ADDR].u32RegAddr = MIS2008_DGAIN_ADDR; + pstI2c_data[LINEAR_D_FINEGAIN_ADDR].u32RegAddr = MIS2008_DGAIN_ADDR + 1; + + pstI2c_data[LINEAR_VMAX_0_ADDR].u32RegAddr = MIS2008_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1_ADDR].u32RegAddr = MIS2008_VMAX_ADDR + 1; + pstI2c_data[LINEAR_FLIP_MIRROR_ADDR].u32RegAddr = MIS2008_FLIP_MIRROR_ADDR; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR_ADDR].bDropFrm = CVI_FALSE; + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (MIS2008_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = MIS2008_MODE_1080P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_ISP_INFO_S *pstIspCfg0 = CVI_NULL; + CVI_U8 value = 0; + CVI_U8 start_x, start_y; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + pstIspCfg0 = &pstSnsState->astSyncInfo[0].ispCfg; + + if (pstSnsState->bInit == CVI_TRUE && g_aeMis2008_MirrorFip[ViPipe] != eSnsMirrorFlip) { + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + value |= 0; + start_x = 4; + start_y = 4; + break; + case ISP_SNS_MIRROR: + value |= 0x01; + start_x = 5; + start_y = 4; + break; + case ISP_SNS_FLIP: + value |= 0x02; + start_x = 4; + start_y = 5; + break; + case ISP_SNS_MIRROR_FLIP: + value |= 0x03; + start_x = 5; + start_y = 5; + break; + default: + return; + } + + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR_ADDR].u32Data = value; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR_ADDR].bDropFrm = 1; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR_ADDR].u8DropFrmNum = 1; + pstIspCfg0->img_size[0].stWndRect.s32X = start_x; + pstIspCfg0->img_size[0].stWndRect.s32Y = start_y; + g_aeMis2008_MirrorFip[ViPipe] = eSnsMirrorFlip; + } + +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const MIS2008_MODE_S *pstMode = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = MIS2008_MODE_1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astMIS2008_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &mis2008_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astMIS2008_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astMIS2008_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &mis2008_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = mis2008_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = mis2008_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (MIS2008_I2C_ADDR_IS_VALID(s32I2cAddr)) + mis2008_i2c_addr = s32I2cAddr; +} + +static CVI_S32 mis2008_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunMIS2008_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + MIS2008_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + MIS2008_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = MIS2008_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, MIS2008_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, MIS2008_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, MIS2008_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16MIS2008_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16MIS2008_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsMIS2008_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = mis2008_standby, + .pfnRestart = mis2008_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = mis2008_write_register, + .pfnReadReg = mis2008_read_register, + .pfnSetBusInfo = mis2008_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = mis2008_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos_ex.h new file mode 100644 index 000000000..a758d2735 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos_ex.h @@ -0,0 +1,79 @@ +#ifndef __MIS2008_CMOS_EX_H_ +#define __MIS2008_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum mis2008_linear_regs_e { + LINEAR_SHS1_0_ADDR, + LINEAR_SHS1_1_ADDR, + LINEAR_SHS1_2_ADDR, + LINEAR_AGAIN_ADDR, + LINEAR_DGAIN_ADDR, + LINEAR_D_FINEGAIN_ADDR, + LINEAR_VMAX_0_ADDR, + LINEAR_VMAX_1_ADDR, + LINEAR_FLIP_MIRROR_ADDR, + LINEAR_REGS_NUM +}; + +typedef enum _MIS2008_MODE_E { + MIS2008_MODE_1080P30 = 0, + MIS2008_MODE_NUM +} MIS2008_MODE_E; + +typedef struct _MIS2008_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_LARGE_S stExp[2]; + SNS_ATTR_LARGE_S stAgain[2]; + SNS_ATTR_LARGE_S stDgain[2]; + char name[64]; +} MIS2008_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastMIS2008[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunMIS2008_BusInfo[]; +extern CVI_U16 g_au16MIS2008_GainMode[]; +extern CVI_U16 g_au16MIS2008_L2SMode[]; +extern CVI_U8 mis2008_i2c_addr; +extern const CVI_U32 mis2008_addr_byte; +extern const CVI_U32 mis2008_data_byte; +extern void mis2008_init(VI_PIPE ViPipe); +extern void mis2008_exit(VI_PIPE ViPipe); +extern void mis2008_standby(VI_PIPE ViPipe); +extern void mis2008_restart(VI_PIPE ViPipe); +extern int mis2008_write_register(VI_PIPE ViPipe, int addr, int data); +extern int mis2008_read_register(VI_PIPE ViPipe, int addr); +extern void mis2008_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int mis2008_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __MIS2008_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos_param.h new file mode 100644 index 000000000..1de9a7f95 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_cmos_param.h @@ -0,0 +1,126 @@ +#ifndef __MIS2008_CMOS_PARAM_H_ +#define __MIS2008_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "mis2008_cmos_ex.h" + +static const MIS2008_MODE_S g_astMIS2008_mode[MIS2008_MODE_NUM] = { + [MIS2008_MODE_1080P30] = { + .name = "1080p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1928, + .u32Height = 1088, + }, + .stWndRect = { + .s32X = 8, + .s32Y = 8, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1928, + .u32Height = 1088, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 1, /* 1500 * 30 / 0x7FFF*/ + .u32HtsDef = 2200, + .u32VtsDef = 1125, + .stExp[0] = {//exp_time + .u32Min = 1, + .u32Max = 1125 - 1, //exp_max + .u32Def = 128, + .u32Step = 1, + }, + .stAgain[0] = { + .u32Min = 1024, + .u32Max = 16128, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain[0] = { + .u32Min = 1024, + .u32Max = 16320, + .u32Def = 1024, + .u32Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {64, 64, 64, 64, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1040, 1040, 1040, 1040 +#endif + }, + .stAuto = { + {64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + /*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + /*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + /*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + /*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, +#endif + }, + }, +}; + +struct combo_dev_attr_s mis2008_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_12BIT, + .lane_id = {2, 0, 1, -1, -1}, + .pn_swap = {1, 1, 1, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + }, + }, + .mclk = { + .cam = 1, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __MIS2008_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_sensor_ctl.c new file mode 100644 index 000000000..4f2523af4 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/imgds_mis2008/mis2008_sensor_ctl.c @@ -0,0 +1,397 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "mis2008_cmos_ex.h" + +static void mis2008_linear_1080p30_init(VI_PIPE ViPipe); + +CVI_U8 mis2008_i2c_addr = 0x30; /* I2C Address of MIS2008 */ +const CVI_U32 mis2008_addr_byte = 2; +const CVI_U32 mis2008_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int mis2008_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunMIS2008_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, mis2008_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int mis2008_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int mis2008_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (mis2008_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, mis2008_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, mis2008_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (mis2008_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int mis2008_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (mis2008_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (mis2008_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, mis2008_addr_byte + mis2008_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void mis2008_standby(VI_PIPE ViPipe) +{ + mis2008_write_register(ViPipe, 0x3006, 0x02); +} + +void mis2008_restart(VI_PIPE ViPipe) +{ + mis2008_write_register(ViPipe, 0x3006, 0x01); +} + +void mis2008_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastMIS2008[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + mis2008_write_register(ViPipe, + g_pastMIS2008[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastMIS2008[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +#define MIS2008_CHIP_ID_HI_ADDR 0x3000 +#define MIS2008_CHIP_ID_LO_ADDR 0x3001 +#define MIS2008_CHIP_ID 0x2008 + +int mis2008_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + if (mis2008_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + delay_ms(5); + + nVal = mis2008_read_register(ViPipe, MIS2008_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = mis2008_read_register(ViPipe, MIS2008_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != MIS2008_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + + +void mis2008_init(VI_PIPE ViPipe) +{ + mis2008_i2c_init(ViPipe); + + mis2008_linear_1080p30_init(ViPipe); + + g_pastMIS2008[ViPipe]->bInit = CVI_TRUE; +} + +void mis2008_exit(VI_PIPE ViPipe) +{ + mis2008_i2c_exit(ViPipe); +} + +/* 1080p30 */ +static void mis2008_linear_1080p30_init(VI_PIPE ViPipe) +{ + /* [ParaList] */ + mis2008_write_register(ViPipe, 0x300a ,0x01); + mis2008_write_register(ViPipe, 0x3006 ,0x02); + mis2008_write_register(ViPipe, 0x3201 ,0x65); + mis2008_write_register(ViPipe, 0x3200 ,0x04); + mis2008_write_register(ViPipe, 0x3203 ,0x98); + mis2008_write_register(ViPipe, 0x3202 ,0x08); + + mis2008_write_register(ViPipe, 0x3205 ,0x04); + mis2008_write_register(ViPipe, 0x3204 ,0x00); + mis2008_write_register(ViPipe, 0x3207 ,0x43); + mis2008_write_register(ViPipe, 0x3206 ,0x04); + + mis2008_write_register(ViPipe, 0x3209 ,0x04); + mis2008_write_register(ViPipe, 0x3208 ,0x00); + mis2008_write_register(ViPipe, 0x320b ,0x8b); + mis2008_write_register(ViPipe, 0x320a ,0x07); + + //mis2008_write_register(ViPipe, 0x3007 ,0x00); + mis2008_write_register(ViPipe, 0x3007 ,0x00); + mis2008_write_register(ViPipe, 0x3300 ,0x21); + mis2008_write_register(ViPipe, 0x3301 ,0x00); + mis2008_write_register(ViPipe, 0x3302 ,0x02); + mis2008_write_register(ViPipe, 0x3303 ,0x06); + mis2008_write_register(ViPipe, 0x330d ,0x00); + mis2008_write_register(ViPipe, 0x330b ,0x01); + mis2008_write_register(ViPipe, 0x330f ,0x0f); + mis2008_write_register(ViPipe, 0x3013 ,0x00); + mis2008_write_register(ViPipe, 0x3637 ,0x1e); + mis2008_write_register(ViPipe, 0x3900 ,0x07); + mis2008_write_register(ViPipe, 0x2107 ,0x00); + mis2008_write_register(ViPipe, 0x330e ,0x00); + + mis2008_write_register(ViPipe, 0x3900 ,0x07); + mis2008_write_register(ViPipe, 0x2108 ,0x01); + mis2008_write_register(ViPipe, 0x3c40 ,0x8c); + mis2008_write_register(ViPipe, 0x3b01 ,0x3f); + mis2008_write_register(ViPipe, 0x3b03 ,0x3f); + mis2008_write_register(ViPipe, 0x3902 ,0x01); + mis2008_write_register(ViPipe, 0x3904 ,0x00); + mis2008_write_register(ViPipe, 0x3903 ,0x00); + mis2008_write_register(ViPipe, 0x3906 ,0x1e); + mis2008_write_register(ViPipe, 0x3905 ,0x00); + mis2008_write_register(ViPipe, 0x3908 ,0x71); + mis2008_write_register(ViPipe, 0x3907 ,0x10); + mis2008_write_register(ViPipe, 0x390a ,0xff); + mis2008_write_register(ViPipe, 0x3909 ,0x1f); + mis2008_write_register(ViPipe, 0x390c ,0x67); + mis2008_write_register(ViPipe, 0x390b ,0x03); + mis2008_write_register(ViPipe, 0x390e ,0x77); + mis2008_write_register(ViPipe, 0x390d ,0x00); + mis2008_write_register(ViPipe, 0x3910 ,0x71); + mis2008_write_register(ViPipe, 0x390f ,0x10); + mis2008_write_register(ViPipe, 0x3912 ,0xff); + mis2008_write_register(ViPipe, 0x3911 ,0x1f); + mis2008_write_register(ViPipe, 0x3919 ,0x00); + mis2008_write_register(ViPipe, 0x3918 ,0x00); + mis2008_write_register(ViPipe, 0x391b ,0x91); + mis2008_write_register(ViPipe, 0x391a ,0x01); + mis2008_write_register(ViPipe, 0x3983 ,0x5a); + mis2008_write_register(ViPipe, 0x3982 ,0x00); + mis2008_write_register(ViPipe, 0x3985 ,0x0f); + mis2008_write_register(ViPipe, 0x3984 ,0x00); + mis2008_write_register(ViPipe, 0x391d ,0x00); + mis2008_write_register(ViPipe, 0x391c ,0x00); + mis2008_write_register(ViPipe, 0x391f ,0x65); + mis2008_write_register(ViPipe, 0x391e ,0x10); + mis2008_write_register(ViPipe, 0x3921 ,0xff); + mis2008_write_register(ViPipe, 0x3920 ,0x1f); + mis2008_write_register(ViPipe, 0x3923 ,0xff); + mis2008_write_register(ViPipe, 0x3922 ,0x1f); + mis2008_write_register(ViPipe, 0x3932 ,0x00); + mis2008_write_register(ViPipe, 0x3931 ,0x00); + mis2008_write_register(ViPipe, 0x3934 ,0x65); + mis2008_write_register(ViPipe, 0x3933 ,0x01); + mis2008_write_register(ViPipe, 0x393f ,0x6c); + mis2008_write_register(ViPipe, 0x393e ,0x00); + mis2008_write_register(ViPipe, 0x3941 ,0x67); + mis2008_write_register(ViPipe, 0x3940 ,0x00); + mis2008_write_register(ViPipe, 0x3943 ,0x55); + mis2008_write_register(ViPipe, 0x3942 ,0x01); + mis2008_write_register(ViPipe, 0x3945 ,0xc2); + mis2008_write_register(ViPipe, 0x3944 ,0x02); + mis2008_write_register(ViPipe, 0x3925 ,0x95); + mis2008_write_register(ViPipe, 0x3924 ,0x00); + mis2008_write_register(ViPipe, 0x3927 ,0xe1); + mis2008_write_register(ViPipe, 0x3926 ,0x02); + mis2008_write_register(ViPipe, 0x3947 ,0x74); + mis2008_write_register(ViPipe, 0x3946 ,0x01); + mis2008_write_register(ViPipe, 0x3949 ,0xda); + mis2008_write_register(ViPipe, 0x3948 ,0x0e); + mis2008_write_register(ViPipe, 0x394b ,0x42); + mis2008_write_register(ViPipe, 0x394a ,0x03); + mis2008_write_register(ViPipe, 0x394d ,0xf2); + mis2008_write_register(ViPipe, 0x394c ,0x01); + mis2008_write_register(ViPipe, 0x3913 ,0x01); + mis2008_write_register(ViPipe, 0x3915 ,0x0f); + mis2008_write_register(ViPipe, 0x3914 ,0x00); + mis2008_write_register(ViPipe, 0x3917 ,0x67); + mis2008_write_register(ViPipe, 0x3916 ,0x03); + mis2008_write_register(ViPipe, 0x392a ,0x1e); + mis2008_write_register(ViPipe, 0x3929 ,0x00); + mis2008_write_register(ViPipe, 0x392c ,0x0f); + mis2008_write_register(ViPipe, 0x392b ,0x00); + mis2008_write_register(ViPipe, 0x392e ,0x0f); + mis2008_write_register(ViPipe, 0x392d ,0x00); + mis2008_write_register(ViPipe, 0x3930 ,0x6e); + mis2008_write_register(ViPipe, 0x392f ,0x03); + mis2008_write_register(ViPipe, 0x397f ,0x00); + mis2008_write_register(ViPipe, 0x397e ,0x00); + mis2008_write_register(ViPipe, 0x3981 ,0x77); + mis2008_write_register(ViPipe, 0x3980 ,0x00); + mis2008_write_register(ViPipe, 0x395d ,0x80); + mis2008_write_register(ViPipe, 0x395c ,0x10); + mis2008_write_register(ViPipe, 0x3962 ,0x9e); + mis2008_write_register(ViPipe, 0x3961 ,0x10); + mis2008_write_register(ViPipe, 0x3977 ,0x22); + mis2008_write_register(ViPipe, 0x3976 ,0x00); + mis2008_write_register(ViPipe, 0x3978 ,0x00); + mis2008_write_register(ViPipe, 0x3979 ,0x04); + mis2008_write_register(ViPipe, 0x396d ,0xc2); + mis2008_write_register(ViPipe, 0x396c ,0x02); + mis2008_write_register(ViPipe, 0x396f ,0xc2); + mis2008_write_register(ViPipe, 0x396e ,0x02); + mis2008_write_register(ViPipe, 0x3971 ,0xc2); + mis2008_write_register(ViPipe, 0x3970 ,0x02); + mis2008_write_register(ViPipe, 0x3973 ,0xc2); + mis2008_write_register(ViPipe, 0x3972 ,0x02); + + mis2008_write_register(ViPipe, 0x3900 ,0x01); + mis2008_write_register(ViPipe, 0x3600 ,0x00); + mis2008_write_register(ViPipe, 0x3707 ,0x00); + mis2008_write_register(ViPipe, 0x3708 ,0x80); + mis2008_write_register(ViPipe, 0x3709 ,0x00); + mis2008_write_register(ViPipe, 0x370a ,0x80); + mis2008_write_register(ViPipe, 0x370b ,0x00); + mis2008_write_register(ViPipe, 0x370c ,0x80); + mis2008_write_register(ViPipe, 0x370d ,0x00); + mis2008_write_register(ViPipe, 0x370e ,0x80); + mis2008_write_register(ViPipe, 0x3006 ,0x00); + + + mis2008_write_register(ViPipe, 0x3012 ,0x01); + mis2008_write_register(ViPipe, 0x3600 ,0x13); + mis2008_write_register(ViPipe, 0x3601 ,0x02); + mis2008_write_register(ViPipe, 0x360e ,0x00); + mis2008_write_register(ViPipe, 0x360f ,0x00); + mis2008_write_register(ViPipe, 0x3610 ,0x02); + mis2008_write_register(ViPipe, 0x3707 ,0x00); + mis2008_write_register(ViPipe, 0x3708 ,0x40); + mis2008_write_register(ViPipe, 0x3709 ,0x00); + mis2008_write_register(ViPipe, 0x370a ,0x40); + mis2008_write_register(ViPipe, 0x370b ,0x00); + mis2008_write_register(ViPipe, 0x370c ,0x40); + mis2008_write_register(ViPipe, 0x370d ,0x00); + mis2008_write_register(ViPipe, 0x370e ,0x40); + mis2008_write_register(ViPipe, 0x3800 ,0x01); + mis2008_write_register(ViPipe, 0x3a03 ,0x03); + mis2008_write_register(ViPipe, 0x3a02 ,0x0b); + mis2008_write_register(ViPipe, 0x3a08 ,0x34); + mis2008_write_register(ViPipe, 0x3a1b ,0x54); + mis2008_write_register(ViPipe, 0x3a1e ,0x80); + mis2008_write_register(ViPipe, 0x3100 ,0x04); + mis2008_write_register(ViPipe, 0x3101 ,0x64); + mis2008_write_register(ViPipe, 0x3a1c ,0x10); + mis2008_write_register(ViPipe, 0x3a0C ,0x04); + mis2008_write_register(ViPipe, 0x3a0D ,0x12); + mis2008_write_register(ViPipe, 0x3a0E ,0x15); + mis2008_write_register(ViPipe, 0x3a0F ,0x18); + mis2008_write_register(ViPipe, 0x3a10 ,0x20); + mis2008_write_register(ViPipe, 0x3a11 ,0x3c); + + mis2008_default_reg_init(ViPipe); + + + delay_ms(100); + + printf("ViPipe:%d,===MIS2008 1080P 30fps 12bit LINE Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/Makefile b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/Makefile new file mode 100644 index 000000000..3ff418d00 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_tp2863.a +TARGET_SO = $(MW_LIB)/libsns_tp2863.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos.c b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos.c new file mode 100644 index 000000000..43f70486d --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos.c @@ -0,0 +1,336 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "tp2863_cmos_ex.h" +#include "tp2863_cmos_param.h" + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_COMMBUS_U g_aunTP2863_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = {.s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = {.s8I2cDev = -1}}; + +ISP_SNS_STATE_S *g_pastTP2863[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define TP2863_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastTP2863[dev]) +#define TP2863_SENSOR_SET_CTX(dev, pstCtx) (g_pastTP2863[dev] = pstCtx) +#define TP2863_SENSOR_RESET_CTX(dev) (g_pastTP2863[dev] = CVI_NULL) + +#define TP2863_RES_IS_720P_25(w, h, f) ((w) == 1280 && (h) == 720 && (f) == 25) +#define TP2863_RES_IS_720P_30(w, h, f) ((w) == 1280 && (h) == 720 && (f) == 30) +#define TP2863_RES_IS_1080P_25(w, h, f) ((w) == 1920 && (h) == 1080 && (f) == 25) +#define TP2863_RES_IS_1080P_30(w, h, f) ((w) == 1920 && (h) == 1080 && (f) == 30) +#define TP2863_ID 0x2863 +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const TP2863_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astTP2863_mode[pstSnsState->u8ImgMode]; + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstCfg0 = &pstSnsState->astSyncInfo[0]; + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + + if (pstSensorImageMode->f32Fps <= 30) + { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (TP2863_RES_IS_720P_25(pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps)) { + u8SensorImageMode = TP2863_MODE_720P_25P; + } else if (TP2863_RES_IS_720P_30(pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps)) { + u8SensorImageMode = TP2863_MODE_720P_30P; + } else if (TP2863_RES_IS_1080P_25(pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps)) { + u8SensorImageMode = TP2863_MODE_1080P_25P; + } else if (TP2863_RES_IS_1080P_30(pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps)) { + u8SensorImageMode = TP2863_MODE_1080P_30P; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + else + { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) + { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->u8ImgMode = TP2863_MODE_1080P_25P; + pstSnsState->enWDRMode = WDR_MODE_NONE; +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &tp2863_rx_attr, sizeof(*pstRxAttr)); + // CVI_TRACE_SNS(CVI_DBG_INFO, "get tp2863_rx0_attr\n"); + + pstRxAttr->img_size.width = g_astTP2863_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astTP2863_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &tp2863_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) + { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) + { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + else + { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) + { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = tp2863_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = tp2863_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 tp2863_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunTP2863_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) + { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + TP2863_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + TP2863_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + (void)pstAeLib; + (void)pstAwbLib; + + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = TP2863_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + (void)pstAeLib; + (void)pstAwbLib; + + CVI_S32 s32Ret; + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, TP2863_ID); + if (s32Ret != CVI_SUCCESS) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsTP2863_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnMirrorFlip = CVI_NULL, + .pfnStandby = CVI_NULL, + .pfnRestart = CVI_NULL, + .pfnWriteReg = tp2863_write_register, + .pfnReadReg = tp2863_read_register, + .pfnSetBusInfo = tp2863_set_bus_info, + .pfnSetInit = CVI_NULL, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = CVI_NULL, + .pfnSnsProbe = CVI_NULL, +}; diff --git a/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos_ex.h new file mode 100644 index 000000000..b4d6fa844 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos_ex.h @@ -0,0 +1,63 @@ +#ifndef __TP2863_CMOS_EX_H_ +#define __TP2863_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +typedef enum _TP2863_MODE_E +{ + TP2863_MODE_1080P_30P, + TP2863_MODE_1080P_25P, + TP2863_MODE_720P_30P, + TP2863_MODE_720P_25P, + TP2863_MODE_NUM +} TP2863_MODE_E; +typedef struct _TP2863_MODE_S +{ + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + CVI_U8 u8DgainReg; + char name[64]; +} TP2863_MODE_S; +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ +extern ISP_SNS_STATE_S *g_pastTP2863[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunTP2863_BusInfo[]; +extern const CVI_U8 tp2863_i2c_addr; +extern const CVI_U32 tp2863_addr_byte; +extern const CVI_U32 tp2863_data_byte; +extern void tp2863_init(VI_PIPE ViPipe); +extern void tp2863_exit(VI_PIPE ViPipe); +extern void tp2863_standby(VI_PIPE ViPipe); +extern void tp2863_restart(VI_PIPE ViPipe); +extern int tp2863_write_register(VI_PIPE ViPipe, int addr, int data); +extern int tp2863_read_register(VI_PIPE ViPipe, int addr); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + +#endif /* __TP2863_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos_param.h new file mode 100644 index 000000000..a43e22daf --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_cmos_param.h @@ -0,0 +1,123 @@ +#ifndef __TP2863_CMOS_PARAM_H_ +#define __TP2863_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "tp2863_cmos_ex.h" + +static const TP2863_MODE_S g_astTP2863_mode[TP2863_MODE_NUM] = { + [TP2863_MODE_1080P_30P] = { + .name = "1080p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + }, + }, + [TP2863_MODE_1080P_25P] = { + .name = "1080p25", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + }, + }, + [TP2863_MODE_720P_30P] = { + .name = "720p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1280, + .u32Height = 720, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1280, + .u32Height = 720, + }, + .stMaxSize = { + .u32Width = 1280, + .u32Height = 720, + }, + }, + }, + [TP2863_MODE_720P_25P] = { + .name = "720p25", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1280, + .u32Height = 720, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1280, + .u32Height = 720, + }, + .stMaxSize = { + .u32Width = 1280, + .u32Height = 720, + }, + }, + }, +}; + +struct combo_dev_attr_s tp2863_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_400M, + .mipi_attr = { + .raw_data_type = YUV422_8BIT, + .lane_id = {0, 2, 1, -1, -1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_NONE, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __TP2863_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_sensor_ctrl.c b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_sensor_ctrl.c new file mode 100644 index 000000000..e57d9187c --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv180x/techpoint_tp2863/tp2863_sensor_ctrl.c @@ -0,0 +1,593 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "tp2863_cmos_ex.h" + +const CVI_U8 tp2863_i2c_addr = 0x44; /* I2C slave address of TP2863, SA0=0:0x44, SA0=1:0x45*/ +const CVI_U32 tp2863_addr_byte = 1; +const CVI_U32 tp2863_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ...(VI_MAX_PIPE_NUM - 1)] = -1}; + +#define TP2863_BLUE_SCREEN 0 + +enum +{ + CH_1 = 0, + CH_2 = 1, + CH_ALL = 4, + MIPI_PAGE = 8, +}; + +enum +{ + STD_TVI, // TVI + STD_HDA, // AHD +}; + +enum +{ + HD25, + HD30, // 1280x720 + FHD25, + FHD30, // 1920x1080 +}; + +enum +{ + MIPI_1CH2LANE_297M, + MIPI_1CH2LANE_594M, + MIPI_2CH2LANE_594M, + MIPI_2CH2LANE_297M, +}; + +int tp2863_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + int ret; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + + u8DevNum = g_aunTP2863_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + syslog(LOG_DEBUG, "open %s\n", acDevFile); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, tp2863_i2c_addr); + if (ret < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int tp2863_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) + { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int tp2863_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return 0; + + if (tp2863_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, tp2863_addr_byte); + if (ret < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return 0; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, tp2863_data_byte); + if (ret < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return 0; + } + + // pack read back data + data = 0; + if (tp2863_data_byte == 2) + { + data = buf[0] << 8; + data += buf[1]; + } + else + { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int tp2863_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (tp2863_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + if (tp2863_data_byte == 2) + buf[idx++] = (data >> 8) & 0xff; + + // add data byte 0 + buf[idx++] = data & 0xff; + + ret = write(g_fd[ViPipe], buf, tp2863_addr_byte + tp2863_data_byte); + if (ret < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + +#if 0 // read back checing + ret = tp2863_read_register(ViPipe, addr); + if (ret != data) + syslog(LOG_DEBUG, "i2c readback-check fail, 0x%x != 0x%x\n", ret, data); +#endif + return CVI_SUCCESS; +} + +void TP2863_decoder_init(VI_PIPE ViPipe, unsigned char ch, unsigned char fmt, unsigned char std) +{ + unsigned char tmp; + const unsigned char REG42_43[] = {0x01, 0x02, 0x00, 0x00, 0x03}; + const unsigned char MASK42_43[] = {0xfe, 0xfd, 0xff, 0xff, 0xfc}; + + tp2863_write_register(ViPipe, 0x40, ch); + tp2863_write_register(ViPipe, 0x06, 0x12); // default value + tp2863_write_register(ViPipe, 0x50, 0x00); // VIN1/3 + tp2863_write_register(ViPipe, 0x51, 0x00); + tp2863_write_register(ViPipe, 0x54, 0x03); + + if (HD25 == fmt) + { + tmp = tp2863_read_register(ViPipe, 0x42); + tmp |= REG42_43[ch]; + tp2863_write_register(ViPipe, 0x42, tmp); + + tmp = tp2863_read_register(ViPipe, 0x43); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x43, tmp); + + tp2863_write_register(ViPipe, 0x02, 0x42); + tp2863_write_register(ViPipe, 0x07, 0xc0); + tp2863_write_register(ViPipe, 0x0b, 0xc0); + tp2863_write_register(ViPipe, 0x0c, 0x13); + tp2863_write_register(ViPipe, 0x0d, 0x50); + + tp2863_write_register(ViPipe, 0x15, 0x13); + tp2863_write_register(ViPipe, 0x16, 0x15); + tp2863_write_register(ViPipe, 0x17, 0x00); + tp2863_write_register(ViPipe, 0x18, 0x19); + tp2863_write_register(ViPipe, 0x19, 0xd0); + tp2863_write_register(ViPipe, 0x1a, 0x25); + tp2863_write_register(ViPipe, 0x1c, 0x07); // 1280*720, 25fps + tp2863_write_register(ViPipe, 0x1d, 0xbc); // 1280*720, 25fps + + tp2863_write_register(ViPipe, 0x20, 0x30); + tp2863_write_register(ViPipe, 0x21, 0x84); + tp2863_write_register(ViPipe, 0x22, 0x36); + tp2863_write_register(ViPipe, 0x23, 0x3c); + + tp2863_write_register(ViPipe, 0x2b, 0x60); + tp2863_write_register(ViPipe, 0x2c, 0x0a); + tp2863_write_register(ViPipe, 0x2d, 0x30); + tp2863_write_register(ViPipe, 0x2e, 0x70); + + tp2863_write_register(ViPipe, 0x30, 0x48); + tp2863_write_register(ViPipe, 0x31, 0xbb); + tp2863_write_register(ViPipe, 0x32, 0x2e); + tp2863_write_register(ViPipe, 0x33, 0x90); + + tp2863_write_register(ViPipe, 0x35, 0x25); + tp2863_write_register(ViPipe, 0x39, 0x08); + + if (STD_HDA == std) + { + tp2863_write_register(ViPipe, 0x02, 0x46); + + tp2863_write_register(ViPipe, 0x0d, 0x71); + + tp2863_write_register(ViPipe, 0x20, 0x40); + tp2863_write_register(ViPipe, 0x21, 0x46); + + tp2863_write_register(ViPipe, 0x25, 0xfe); + tp2863_write_register(ViPipe, 0x26, 0x01); + + tp2863_write_register(ViPipe, 0x2c, 0x3a); + tp2863_write_register(ViPipe, 0x2d, 0x5a); + tp2863_write_register(ViPipe, 0x2e, 0x40); + + tp2863_write_register(ViPipe, 0x30, 0x9e); + tp2863_write_register(ViPipe, 0x31, 0x20); + tp2863_write_register(ViPipe, 0x32, 0x10); + tp2863_write_register(ViPipe, 0x33, 0x90); + } + } + else if (HD30 == fmt) + { + tmp = tp2863_read_register(ViPipe, 0x42); + tmp |= REG42_43[ch]; + tp2863_write_register(ViPipe, 0x42, tmp); + + tmp = tp2863_read_register(ViPipe, 0x43); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x43, tmp); + + tp2863_write_register(ViPipe, 0x02, 0x42); + tp2863_write_register(ViPipe, 0x07, 0xc0); + tp2863_write_register(ViPipe, 0x0b, 0xc0); + tp2863_write_register(ViPipe, 0x0c, 0x13); + tp2863_write_register(ViPipe, 0x0d, 0x50); + + tp2863_write_register(ViPipe, 0x15, 0x13); + tp2863_write_register(ViPipe, 0x16, 0x15); + tp2863_write_register(ViPipe, 0x17, 0x00); + tp2863_write_register(ViPipe, 0x18, 0x19); + tp2863_write_register(ViPipe, 0x19, 0xd0); + tp2863_write_register(ViPipe, 0x1a, 0x25); + tp2863_write_register(ViPipe, 0x1c, 0x06); // 1280*720, 30fps + tp2863_write_register(ViPipe, 0x1d, 0x72); // 1280*720, 30fps + + tp2863_write_register(ViPipe, 0x20, 0x30); + tp2863_write_register(ViPipe, 0x21, 0x84); + tp2863_write_register(ViPipe, 0x22, 0x36); + tp2863_write_register(ViPipe, 0x23, 0x3c); + + tp2863_write_register(ViPipe, 0x2b, 0x60); + tp2863_write_register(ViPipe, 0x2c, 0x0a); + tp2863_write_register(ViPipe, 0x2d, 0x30); + tp2863_write_register(ViPipe, 0x2e, 0x70); + + tp2863_write_register(ViPipe, 0x30, 0x48); + tp2863_write_register(ViPipe, 0x31, 0xbb); + tp2863_write_register(ViPipe, 0x32, 0x2e); + tp2863_write_register(ViPipe, 0x33, 0x90); + + tp2863_write_register(ViPipe, 0x35, 0x25); + tp2863_write_register(ViPipe, 0x39, 0x08); + + if (STD_HDA == std) + { + tp2863_write_register(ViPipe, 0x02, 0x46); + + tp2863_write_register(ViPipe, 0x0d, 0x70); + + tp2863_write_register(ViPipe, 0x20, 0x40); + tp2863_write_register(ViPipe, 0x21, 0x46); + + tp2863_write_register(ViPipe, 0x25, 0xfe); + tp2863_write_register(ViPipe, 0x26, 0x01); + + tp2863_write_register(ViPipe, 0x2c, 0x3a); + tp2863_write_register(ViPipe, 0x2d, 0x5a); + tp2863_write_register(ViPipe, 0x2e, 0x40); + + tp2863_write_register(ViPipe, 0x30, 0x9d); + tp2863_write_register(ViPipe, 0x31, 0xca); + tp2863_write_register(ViPipe, 0x32, 0x01); + tp2863_write_register(ViPipe, 0x33, 0xd0); + } + } + else if (FHD25 == fmt) + { + tmp = tp2863_read_register(ViPipe, 0x42); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x42, tmp); + + tmp = tp2863_read_register(ViPipe, 0x43); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x43, tmp); + + tp2863_write_register(ViPipe, 0x02, 0x40); + tp2863_write_register(ViPipe, 0x07, 0xc0); + tp2863_write_register(ViPipe, 0x0b, 0xc0); + tp2863_write_register(ViPipe, 0x0c, 0x03); + tp2863_write_register(ViPipe, 0x0d, 0x50); + + tp2863_write_register(ViPipe, 0x15, 0x03); + tp2863_write_register(ViPipe, 0x16, 0xd2); + tp2863_write_register(ViPipe, 0x17, 0x80); + tp2863_write_register(ViPipe, 0x18, 0x29); + tp2863_write_register(ViPipe, 0x19, 0x38); + tp2863_write_register(ViPipe, 0x1a, 0x47); + + tp2863_write_register(ViPipe, 0x1c, 0x0a); // 1920*1080, 25fps + tp2863_write_register(ViPipe, 0x1d, 0x50); // + + tp2863_write_register(ViPipe, 0x20, 0x30); + tp2863_write_register(ViPipe, 0x21, 0x84); + tp2863_write_register(ViPipe, 0x22, 0x36); + tp2863_write_register(ViPipe, 0x23, 0x3c); + + tp2863_write_register(ViPipe, 0x2b, 0x60); + tp2863_write_register(ViPipe, 0x2c, 0x0a); + tp2863_write_register(ViPipe, 0x2d, 0x30); + tp2863_write_register(ViPipe, 0x2e, 0x70); + + tp2863_write_register(ViPipe, 0x30, 0x48); + tp2863_write_register(ViPipe, 0x31, 0xbb); + tp2863_write_register(ViPipe, 0x32, 0x2e); + tp2863_write_register(ViPipe, 0x33, 0x90); + + tp2863_write_register(ViPipe, 0x35, 0x05); + tp2863_write_register(ViPipe, 0x39, 0x0C); + + if (STD_HDA == std) + { + tp2863_write_register(ViPipe, 0x02, 0x44); + + tp2863_write_register(ViPipe, 0x0d, 0x73); + + tp2863_write_register(ViPipe, 0x15, 0x01); + tp2863_write_register(ViPipe, 0x16, 0xf0); + tp2863_write_register(ViPipe, 0x18, 0x2a); + tp2863_write_register(ViPipe, 0x20, 0x3c); + tp2863_write_register(ViPipe, 0x21, 0x46); + + tp2863_write_register(ViPipe, 0x25, 0xfe); + tp2863_write_register(ViPipe, 0x26, 0x0d); + + tp2863_write_register(ViPipe, 0x2c, 0x3a); + tp2863_write_register(ViPipe, 0x2d, 0x54); + tp2863_write_register(ViPipe, 0x2e, 0x40); + + tp2863_write_register(ViPipe, 0x30, 0xa5); + tp2863_write_register(ViPipe, 0x31, 0x86); + tp2863_write_register(ViPipe, 0x32, 0xfb); + tp2863_write_register(ViPipe, 0x33, 0x60); + } + } + else if (FHD30 == fmt) + { + tmp = tp2863_read_register(ViPipe, 0x42); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x42, tmp); + + tmp = tp2863_read_register(ViPipe, 0x43); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x43, tmp); + + tp2863_write_register(ViPipe, 0x02, 0x40); + tp2863_write_register(ViPipe, 0x07, 0xc0); + tp2863_write_register(ViPipe, 0x0b, 0xc0); + tp2863_write_register(ViPipe, 0x0c, 0x03); + tp2863_write_register(ViPipe, 0x0d, 0x50); + + tp2863_write_register(ViPipe, 0x15, 0x03); + tp2863_write_register(ViPipe, 0x16, 0xd2); + tp2863_write_register(ViPipe, 0x17, 0x80); + tp2863_write_register(ViPipe, 0x18, 0x29); + tp2863_write_register(ViPipe, 0x19, 0x38); + tp2863_write_register(ViPipe, 0x1a, 0x47); + tp2863_write_register(ViPipe, 0x1c, 0x08); // 1920*1080, 30fps + tp2863_write_register(ViPipe, 0x1d, 0x98); // + + tp2863_write_register(ViPipe, 0x20, 0x30); + tp2863_write_register(ViPipe, 0x21, 0x84); + tp2863_write_register(ViPipe, 0x22, 0x36); + tp2863_write_register(ViPipe, 0x23, 0x3c); + + tp2863_write_register(ViPipe, 0x2b, 0x60); + tp2863_write_register(ViPipe, 0x2c, 0x0a); + tp2863_write_register(ViPipe, 0x2d, 0x30); + tp2863_write_register(ViPipe, 0x2e, 0x70); + + tp2863_write_register(ViPipe, 0x30, 0x48); + tp2863_write_register(ViPipe, 0x31, 0xbb); + tp2863_write_register(ViPipe, 0x32, 0x2e); + tp2863_write_register(ViPipe, 0x33, 0x90); + + tp2863_write_register(ViPipe, 0x35, 0x05); + tp2863_write_register(ViPipe, 0x39, 0x0C); + + if (STD_HDA == std) + { + tp2863_write_register(ViPipe, 0x02, 0x44); + + tp2863_write_register(ViPipe, 0x0d, 0x72); + + tp2863_write_register(ViPipe, 0x15, 0x01); + tp2863_write_register(ViPipe, 0x16, 0xf0); + tp2863_write_register(ViPipe, 0x18, 0x2a); + + tp2863_write_register(ViPipe, 0x20, 0x38); + tp2863_write_register(ViPipe, 0x21, 0x46); + + tp2863_write_register(ViPipe, 0x25, 0xfe); + tp2863_write_register(ViPipe, 0x26, 0x0d); + + tp2863_write_register(ViPipe, 0x2c, 0x3a); + tp2863_write_register(ViPipe, 0x2d, 0x54); + tp2863_write_register(ViPipe, 0x2e, 0x40); + + tp2863_write_register(ViPipe, 0x30, 0xa5); + tp2863_write_register(ViPipe, 0x31, 0x95); + tp2863_write_register(ViPipe, 0x32, 0xe0); + tp2863_write_register(ViPipe, 0x33, 0x60); + } + } +} + +void TP2863_mipi_out(VI_PIPE ViPipe, unsigned char output) +{ + // mipi setting + tp2863_write_register(ViPipe, 0x40, MIPI_PAGE); // MIPI page + tp2863_write_register(ViPipe, 0x02, 0x78); + tp2863_write_register(ViPipe, 0x03, 0x70); + tp2863_write_register(ViPipe, 0x04, 0x70); + tp2863_write_register(ViPipe, 0x05, 0x70); + tp2863_write_register(ViPipe, 0x06, 0x70); + + tp2863_write_register(ViPipe, 0x13, 0xef); + tp2863_write_register(ViPipe, 0x20, 0x00); + tp2863_write_register(ViPipe, 0x21, 0x22); + tp2863_write_register(ViPipe, 0x22, 0x20); + tp2863_write_register(ViPipe, 0x23, 0x9e); + + if (MIPI_1CH2LANE_297M == output) + { + tp2863_write_register(ViPipe, 0x21, 0x12); + tp2863_write_register(ViPipe, 0x14, 0x41); + tp2863_write_register(ViPipe, 0x15, 0x02); + tp2863_write_register(ViPipe, 0x2a, 0x04); + tp2863_write_register(ViPipe, 0x2b, 0x03); + tp2863_write_register(ViPipe, 0x2c, 0x09); + tp2863_write_register(ViPipe, 0x2e, 0x02); + tp2863_write_register(ViPipe, 0x10, 0xa0); + tp2863_write_register(ViPipe, 0x10, 0x20); + } + else if (MIPI_1CH2LANE_594M == output) + { + tp2863_write_register(ViPipe, 0x21, 0x12); + tp2863_write_register(ViPipe, 0x14, 0x00); // clk + tp2863_write_register(ViPipe, 0x15, 0x01); // clk + tp2863_write_register(ViPipe, 0x2a, 0x08); // LPX + tp2863_write_register(ViPipe, 0x2b, 0x08); // PREP + tp2863_write_register(ViPipe, 0x2c, 0x10); // TRAIL/HS ZERO + tp2863_write_register(ViPipe, 0x2e, 0x0a); + tp2863_write_register(ViPipe, 0x10, 0xa0); + tp2863_write_register(ViPipe, 0x10, 0x20); + } + else if (MIPI_2CH2LANE_297M == output) + { + tp2863_write_register(ViPipe, 0x21, 0x22); + tp2863_write_register(ViPipe, 0x14, 0x41); + tp2863_write_register(ViPipe, 0x15, 0x02); + tp2863_write_register(ViPipe, 0x2a, 0x04); + tp2863_write_register(ViPipe, 0x2b, 0x03); + tp2863_write_register(ViPipe, 0x2c, 0x09); + tp2863_write_register(ViPipe, 0x2e, 0x02); + tp2863_write_register(ViPipe, 0x10, 0xa0); + tp2863_write_register(ViPipe, 0x10, 0x20); + } + else if (MIPI_2CH2LANE_594M == output) + { + tp2863_write_register(ViPipe, 0x21, 0x22); + tp2863_write_register(ViPipe, 0x14, 0x00); + tp2863_write_register(ViPipe, 0x15, 0x01); + tp2863_write_register(ViPipe, 0x2a, 0x08); + tp2863_write_register(ViPipe, 0x2b, 0x08); + tp2863_write_register(ViPipe, 0x2c, 0x10); + tp2863_write_register(ViPipe, 0x2e, 0x0a); + tp2863_write_register(ViPipe, 0x10, 0xa0); + tp2863_write_register(ViPipe, 0x10, 0x20); + } + + /* Enable MIPI CSI2 output */ + tp2863_write_register(ViPipe, 0x28, 0x02); + tp2863_write_register(ViPipe, 0x28, 0x00); +} + +void TP2863_reg_init(VI_PIPE ViPipe, CVI_U8 u8ImgMode) +{ + if (u8ImgMode == TP2863_MODE_1080P_30P) + { + TP2863_decoder_init(ViPipe, CH_1, FHD30, STD_HDA); + TP2863_mipi_out(ViPipe, MIPI_1CH2LANE_297M); + printf("Techpoint TP2863 1080 FHD30\n"); + } + else if (u8ImgMode == TP2863_MODE_1080P_25P) + { + TP2863_decoder_init(ViPipe, CH_1, FHD25, STD_HDA); + TP2863_mipi_out(ViPipe, MIPI_1CH2LANE_297M); + printf("Techpoint TP2863 720 FHD25\n"); + } + else if (u8ImgMode == TP2863_MODE_720P_30P) + { + TP2863_decoder_init(ViPipe, CH_1, HD30, STD_HDA); + TP2863_mipi_out(ViPipe, MIPI_1CH2LANE_297M); + printf("Techpoint TP2863 720 HD30\n"); + } + else if (u8ImgMode == TP2863_MODE_720P_25P) + { + TP2863_decoder_init(ViPipe, CH_1, HD25, STD_HDA); + TP2863_mipi_out(ViPipe, MIPI_1CH2LANE_297M); + printf("Techpoint TP2863 720 HD25\n"); + } +} + +void tp2863_init(VI_PIPE ViPipe) +{ + tp2863_i2c_init(ViPipe); + + syslog(LOG_DEBUG, "Loading Techpoint TP2863 sensor\n"); + + // check sensor chip id + tp2863_write_register(ViPipe, 0x40, 0x0); + if (tp2863_read_register(ViPipe, 0xfe) != 0x28 || + tp2863_read_register(ViPipe, 0xff) != 0x63) + { + syslog(LOG_DEBUG, "read TP2863 chip id fail\n"); + return; + } + + TP2863_reg_init(ViPipe, g_pastTP2863[ViPipe]->u8ImgMode); + + usleep(500 * 1000); + +#if TP2863_BLUE_SCREEN + tp2863_write_register(ViPipe, 0x40, 0x00); + tp2863_write_register(ViPipe, 0x2A, 0x3C); +#endif +} + +void tp2863_exit(VI_PIPE ViPipe) +{ + tp2863_i2c_exit(ViPipe); +} \ No newline at end of file diff --git a/middleware/v2/component/isp/sensor/cv181x/Makefile b/middleware/v2/component/isp/sensor/cv181x/Makefile index df18c95bc..815ace8d6 100644 --- a/middleware/v2/component/isp/sensor/cv181x/Makefile +++ b/middleware/v2/component/isp/sensor/cv181x/Makefile @@ -29,6 +29,9 @@ brigates_bg0808: gcore_gc02m1: $(call MAKE_SENSOR, ${@}) +gcore_gc0329: + $(call MAKE_SENSOR, ${@}) + gcore_gc1054: $(call MAKE_SENSOR, ${@}) @@ -53,6 +56,9 @@ gcore_gc4023: gcore_gc4653: $(call MAKE_SENSOR, ${@}) +imgds_mis2008: + $(call MAKE_SENSOR, ${@}) + nextchip_n5: $(call MAKE_SENSOR, ${@}) @@ -181,6 +187,9 @@ sony_imx335: techpoint_tp2825: $(call MAKE_SENSOR, ${@}) + +techpoint_tp2863: + $(call MAKE_SENSOR, ${@}) all_sensor: @$(MAKE) -f Makefile_full || exit 1; diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/Makefile b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/Makefile new file mode 100644 index 000000000..5bbcfd07f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_gc0329.a +TARGET_SO = $(MW_LIB)/libsns_gc0329.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos.c b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos.c new file mode 100644 index 000000000..5b5a220dd --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos.c @@ -0,0 +1,303 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "gc0329_cmos_ex.h" +#include "gc0329_cmos_param.h" + +#define GC0329_ID 0xc0 +#define GC0329_I2C_ADDR_1 0x31 +#define GC0329_I2C_ADDR_IS_VALID(addr) ((addr) == GC0329_I2C_ADDR_1) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastGc0329[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define GC0329_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastGc0329[dev]) +#define GC0329_SENSOR_SET_CTX(dev, pstCtx) (g_pastGc0329[dev] = pstCtx) +#define GC0329_SENSOR_RESET_CTX(dev) (g_pastGc0329[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunGc0329_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +#define GC0329_RES_IS_480P(w, h) ((w) == 640 && (h) == 480) + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const GC0329_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astGc0329_mode; + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->stImg, sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstCfg0 = &pstSnsState->astSyncInfo[0]; + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 10) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (GC0329_RES_IS_480P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) + u8SensorImageMode = GC0329_MODE_640X480P10; + else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support this Fps:%f\n", pstSensorImageMode->f32Fps); + return CVI_FAILURE; + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = GC0329_MODE_640X480P10; + pstSnsState->enWDRMode = WDR_MODE_NONE; +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &gc0329_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astGc0329_mode.stImg.stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astGc0329_mode.stImg.stSnsSize.u32Height; + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &gc0329_rx_attr; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = gc0329_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = gc0329_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (GC0329_I2C_ADDR_IS_VALID(s32I2cAddr)) + gc0329_i2c_addr = s32I2cAddr; +} + +static CVI_S32 gc0329_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunGc0329_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + GC0329_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + GC0329_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + GC0329_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + (void) pstAeLib; + (void) pstAwbLib; + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = GC0329_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + (void) pstAeLib; + (void) pstAwbLib; + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, GC0329_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_probe(VI_PIPE ViPipe) +{ + return gc0329_probe(ViPipe); +} + +ISP_SNS_OBJ_S stSnsGc0329_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = CVI_NULL, + .pfnRestart = CVI_NULL, + .pfnWriteReg = gc0329_write_register, + .pfnReadReg = gc0329_read_register, + .pfnSetBusInfo = gc0329_set_bus_info, + .pfnSetInit = CVI_NULL, + .pfnMirrorFlip = CVI_NULL, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = CVI_NULL, + .pfnSnsProbe = sensor_probe, +}; diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos_ex.h new file mode 100644 index 000000000..9ad3c8be1 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos_ex.h @@ -0,0 +1,64 @@ +#ifndef __GC0329_CMOS_EX_H_ +#define __GC0329_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +typedef enum _GC0329_MODE_E { + GC0329_MODE_640X480P10 = 0, + GC0329_MODE_NUM +} GC0329_SLAVE_MODE_E; + +typedef struct _GC0329_MODE_S { + ISP_WDR_SIZE_S stImg; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp; + SNS_ATTR_LARGE_S stAgain; + SNS_ATTR_LARGE_S stDgain; + char name[64]; +} GC0329_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastGc0329[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunGc0329_BusInfo[]; +extern CVI_U8 gc0329_i2c_addr; +extern const CVI_U32 gc0329_addr_byte; +extern const CVI_U32 gc0329_data_byte; +extern void gc0329_init(VI_PIPE ViPipe); +extern void gc0329_exit(VI_PIPE ViPipe); +extern void gc0329_standby(VI_PIPE ViPipe); +extern void gc0329_restart(VI_PIPE ViPipe); +extern int gc0329_write_register(VI_PIPE ViPipe, int addr, int data); +extern int gc0329_read_register(VI_PIPE ViPipe, int addr); +extern void gc0329_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int gc0329_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC0329_CMOS_EX_H_ */ + diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos_param.h new file mode 100644 index 000000000..56a42de3f --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_cmos_param.h @@ -0,0 +1,71 @@ +#ifndef __GC0329_CMOS_PARAM_H_ +#define __GC0329_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc0329_cmos_ex.h" + +static const GC0329_MODE_S g_astGc0329_mode = { + .name = "640X480P10", + .stImg = { + .stSnsSize = { + .u32Width = 640, + .u32Height = 480, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 640, + .u32Height = 480, + }, + .stMaxSize = { + .u32Width = 640, + .u32Height = 480, + }, + }, +}; + +struct combo_dev_attr_s gc0329_rx_attr = { + .input_mode = INPUT_MODE_BT601, + .mac_clk = RX_MAC_CLK_200M, + .ttl_attr = { + .vi = TTL_VI_SRC_VI0, + .ttl_fmt = TTL_VSDE_11B, + .raw_data_type = RAW_DATA_8BIT, + .func = { + 8, -1, -1, 12, + 0, 1, 2, 3, + 4, 13, 14, 11, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_24M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __GC0329_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_sensor_ctl.c new file mode 100644 index 000000000..1bdd8753b --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc0329/gc0329_sensor_ctl.c @@ -0,0 +1,464 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "gc0329_cmos_ex.h" + +static void gc0329_linear_480p10_init(VI_PIPE ViPipe); + +CVI_U8 gc0329_i2c_addr = 0x31;//0x78 +const CVI_U32 gc0329_addr_byte = 1; +const CVI_U32 gc0329_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int gc0329_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunGc0329_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/i2c-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, gc0329_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int gc0329_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int gc0329_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (gc0329_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, gc0329_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, gc0329_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (gc0329_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + + +int gc0329_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (gc0329_addr_byte == 1) { + buf[idx] = addr & 0xff; + idx++; + } + if (gc0329_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, gc0329_addr_byte + gc0329_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } +// syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +#define GC0329_CHIP_ID_ADDR 0x00 +#define GC0329_CHIP_ID 0xc0 + +int gc0329_probe(VI_PIPE ViPipe) +{ + int nVal; + + usleep(50); + if (gc0329_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + gc0329_write_register(ViPipe, 0xfc, 0x16); + nVal = gc0329_read_register(ViPipe, GC0329_CHIP_ID_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + + if ((nVal & 0xFF) != GC0329_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + printf("%d\n", ViPipe); + return CVI_SUCCESS; +} + +void gc0329_init(VI_PIPE ViPipe) +{ + gc0329_i2c_init(ViPipe); + + gc0329_linear_480p10_init(ViPipe); + + g_pastGc0329[ViPipe]->bInit = CVI_TRUE; +} + +void gc0329_exit(VI_PIPE ViPipe) +{ + gc0329_i2c_exit(ViPipe); +} + +static void gc0329_linear_480p10_init(VI_PIPE ViPipe) +{ + gc0329_write_register(ViPipe, 0xfe, 0x80); + gc0329_write_register(ViPipe, 0xfc, 0x16); + gc0329_write_register(ViPipe, 0xfc, 0x16); + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0x70, 0x48); + gc0329_write_register(ViPipe, 0x73, 0x90); + gc0329_write_register(ViPipe, 0x74, 0x80); + gc0329_write_register(ViPipe, 0x75, 0x80); + gc0329_write_register(ViPipe, 0x76, 0x94); + gc0329_write_register(ViPipe, 0x77, 0x62); + gc0329_write_register(ViPipe, 0x78, 0x47); + gc0329_write_register(ViPipe, 0x79, 0x40); + + gc0329_write_register(ViPipe, 0x03, 0x02); + gc0329_write_register(ViPipe, 0x04, 0x40); + + gc0329_write_register(ViPipe, 0xfc, 0x16); + gc0329_write_register(ViPipe, 0x09, 0x00); + gc0329_write_register(ViPipe, 0x0a, 0x02); + gc0329_write_register(ViPipe, 0x0b, 0x00); + gc0329_write_register(ViPipe, 0x0c, 0x02); + gc0329_write_register(ViPipe, 0x17, 0x14); + gc0329_write_register(ViPipe, 0x19, 0x05); + gc0329_write_register(ViPipe, 0x1b, 0x24); + gc0329_write_register(ViPipe, 0x1c, 0x04); + gc0329_write_register(ViPipe, 0x1e, 0x08); + gc0329_write_register(ViPipe, 0x1f, 0x08); + gc0329_write_register(ViPipe, 0x20, 0x01); + gc0329_write_register(ViPipe, 0x21, 0x48); + gc0329_write_register(ViPipe, 0x22, 0xba); + gc0329_write_register(ViPipe, 0x23, 0x22); + gc0329_write_register(ViPipe, 0x24, 0x16); + + gc0329_write_register(ViPipe, 0x26, 0xf7); + gc0329_write_register(ViPipe, 0x28, 0x7f); + gc0329_write_register(ViPipe, 0x29, 0x00); + gc0329_write_register(ViPipe, 0x32, 0x00); + gc0329_write_register(ViPipe, 0x33, 0x20); + gc0329_write_register(ViPipe, 0x34, 0x20); + gc0329_write_register(ViPipe, 0x35, 0x20); + gc0329_write_register(ViPipe, 0x36, 0x20); + + gc0329_write_register(ViPipe, 0x3b, 0x04); + gc0329_write_register(ViPipe, 0x3c, 0x04); + gc0329_write_register(ViPipe, 0x3d, 0x04); + gc0329_write_register(ViPipe, 0x3e, 0x04); + + gc0329_write_register(ViPipe, 0x40, 0xff); + gc0329_write_register(ViPipe, 0x41, 0x24); + gc0329_write_register(ViPipe, 0x42, 0xfa); + gc0329_write_register(ViPipe, 0x46, 0x02); + gc0329_write_register(ViPipe, 0x4b, 0xca); + gc0329_write_register(ViPipe, 0x4d, 0x01); + gc0329_write_register(ViPipe, 0x4f, 0x01); + gc0329_write_register(ViPipe, 0x70, 0x48); + + gc0329_write_register(ViPipe, 0x80, 0x07); + gc0329_write_register(ViPipe, 0x81, 0xc2); + gc0329_write_register(ViPipe, 0x82, 0x90); + gc0329_write_register(ViPipe, 0x83, 0x05); + gc0329_write_register(ViPipe, 0x87, 0x40); + + gc0329_write_register(ViPipe, 0x90, 0x8c); + gc0329_write_register(ViPipe, 0x92, 0x05); + gc0329_write_register(ViPipe, 0x94, 0x05); + gc0329_write_register(ViPipe, 0x95, 0x45); + gc0329_write_register(ViPipe, 0x96, 0x88); + + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0x18, 0x22); + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0x9c, 0x0a); + gc0329_write_register(ViPipe, 0xa0, 0xaf); + gc0329_write_register(ViPipe, 0xa2, 0xff); + gc0329_write_register(ViPipe, 0xa4, 0x30); + gc0329_write_register(ViPipe, 0xa5, 0x31); + gc0329_write_register(ViPipe, 0xa7, 0x35); + + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0xbf, 0x0b); + gc0329_write_register(ViPipe, 0xc0, 0x1d); + gc0329_write_register(ViPipe, 0xc1, 0x33); + gc0329_write_register(ViPipe, 0xc2, 0x49); + gc0329_write_register(ViPipe, 0xc3, 0x5d); + gc0329_write_register(ViPipe, 0xc4, 0x6e); + gc0329_write_register(ViPipe, 0xc5, 0x7c); + gc0329_write_register(ViPipe, 0xc6, 0x99); + gc0329_write_register(ViPipe, 0xc7, 0xaf); + gc0329_write_register(ViPipe, 0xc8, 0xc2); + gc0329_write_register(ViPipe, 0xc9, 0xd0); + gc0329_write_register(ViPipe, 0xca, 0xda); + gc0329_write_register(ViPipe, 0xcb, 0xe2); + gc0329_write_register(ViPipe, 0xcc, 0xe7); + gc0329_write_register(ViPipe, 0xcd, 0xf0); + gc0329_write_register(ViPipe, 0xce, 0xf7); + gc0329_write_register(ViPipe, 0xcf, 0xff); + + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0x63, 0x00); + gc0329_write_register(ViPipe, 0x64, 0x06); + gc0329_write_register(ViPipe, 0x65, 0x0d); + gc0329_write_register(ViPipe, 0x66, 0x1b); + gc0329_write_register(ViPipe, 0x67, 0x2b); + gc0329_write_register(ViPipe, 0x68, 0x3d); + gc0329_write_register(ViPipe, 0x69, 0x50); + gc0329_write_register(ViPipe, 0x6a, 0x60); + gc0329_write_register(ViPipe, 0x6b, 0x80); + gc0329_write_register(ViPipe, 0x6c, 0xa0); + gc0329_write_register(ViPipe, 0x6d, 0xc0); + gc0329_write_register(ViPipe, 0x6e, 0xe0); + gc0329_write_register(ViPipe, 0x6f, 0xff); + + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0xb3, 0x44); + gc0329_write_register(ViPipe, 0xb4, 0xfd); + gc0329_write_register(ViPipe, 0xb5, 0x02); + gc0329_write_register(ViPipe, 0xb6, 0xfa); + gc0329_write_register(ViPipe, 0xb7, 0x48); + gc0329_write_register(ViPipe, 0xb8, 0xf0); + gc0329_write_register(ViPipe, 0x50, 0x01); + + gc0329_write_register(ViPipe, 0xfe, 0x00); + gc0329_write_register(ViPipe, 0xd0, 0x40); + gc0329_write_register(ViPipe, 0xd1, 0x28); + gc0329_write_register(ViPipe, 0xd2, 0x28); + gc0329_write_register(ViPipe, 0xd3, 0x40); + gc0329_write_register(ViPipe, 0xd5, 0x00); + gc0329_write_register(ViPipe, 0xdd, 0x14); + gc0329_write_register(ViPipe, 0xde, 0x34); + + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0x10, 0x40); + gc0329_write_register(ViPipe, 0x11, 0x21); + gc0329_write_register(ViPipe, 0x12, 0x13); + gc0329_write_register(ViPipe, 0x13, 0x50); + gc0329_write_register(ViPipe, 0x17, 0xa8); + gc0329_write_register(ViPipe, 0x1a, 0x21); + gc0329_write_register(ViPipe, 0x20, 0x31); + gc0329_write_register(ViPipe, 0x21, 0xc0); + gc0329_write_register(ViPipe, 0x22, 0x60); + gc0329_write_register(ViPipe, 0x3c, 0x50); + gc0329_write_register(ViPipe, 0x3d, 0x40); + gc0329_write_register(ViPipe, 0x3e, 0x45); + + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0x06, 0x12); + gc0329_write_register(ViPipe, 0x07, 0x06); + gc0329_write_register(ViPipe, 0x08, 0x9c); + gc0329_write_register(ViPipe, 0x09, 0xee); + gc0329_write_register(ViPipe, 0x50, 0xfc); + gc0329_write_register(ViPipe, 0x51, 0x28); + gc0329_write_register(ViPipe, 0x52, 0x10); + gc0329_write_register(ViPipe, 0x53, 0x20); + gc0329_write_register(ViPipe, 0x54, 0x12); + gc0329_write_register(ViPipe, 0x55, 0x16); + gc0329_write_register(ViPipe, 0x56, 0x30); + gc0329_write_register(ViPipe, 0x58, 0x60); + gc0329_write_register(ViPipe, 0x59, 0x08); + gc0329_write_register(ViPipe, 0x5a, 0x02); + gc0329_write_register(ViPipe, 0x5b, 0x63); + gc0329_write_register(ViPipe, 0x5c, 0x35); + gc0329_write_register(ViPipe, 0x5d, 0x72); + gc0329_write_register(ViPipe, 0x5e, 0x11); + gc0329_write_register(ViPipe, 0x5f, 0x40); + gc0329_write_register(ViPipe, 0x60, 0x40); + gc0329_write_register(ViPipe, 0x61, 0xc8); + gc0329_write_register(ViPipe, 0x62, 0xa0); + gc0329_write_register(ViPipe, 0x63, 0x40); + gc0329_write_register(ViPipe, 0x64, 0x50); + gc0329_write_register(ViPipe, 0x65, 0x98); + gc0329_write_register(ViPipe, 0x66, 0xfa); + gc0329_write_register(ViPipe, 0x67, 0x80); + gc0329_write_register(ViPipe, 0x68, 0x60); + gc0329_write_register(ViPipe, 0x69, 0x90); + gc0329_write_register(ViPipe, 0x6a, 0x40); + gc0329_write_register(ViPipe, 0x6b, 0x39); + gc0329_write_register(ViPipe, 0x6c, 0x30); + gc0329_write_register(ViPipe, 0x6d, 0x60); + gc0329_write_register(ViPipe, 0x6e, 0x41); + gc0329_write_register(ViPipe, 0x70, 0x10); + gc0329_write_register(ViPipe, 0x71, 0x00); + gc0329_write_register(ViPipe, 0x72, 0x10); + gc0329_write_register(ViPipe, 0x73, 0x40); + gc0329_write_register(ViPipe, 0x80, 0x60); + gc0329_write_register(ViPipe, 0x81, 0x50); + gc0329_write_register(ViPipe, 0x82, 0x42); + gc0329_write_register(ViPipe, 0x83, 0x40); + gc0329_write_register(ViPipe, 0x84, 0x40); + gc0329_write_register(ViPipe, 0x85, 0x40); + gc0329_write_register(ViPipe, 0x74, 0x40); + gc0329_write_register(ViPipe, 0x75, 0x58); + gc0329_write_register(ViPipe, 0x76, 0x24); + gc0329_write_register(ViPipe, 0x77, 0x40); + gc0329_write_register(ViPipe, 0x78, 0x20); + gc0329_write_register(ViPipe, 0x79, 0x60); + gc0329_write_register(ViPipe, 0x7a, 0x58); + gc0329_write_register(ViPipe, 0x7b, 0x20); + gc0329_write_register(ViPipe, 0x7c, 0x30); + gc0329_write_register(ViPipe, 0x7d, 0x35); + gc0329_write_register(ViPipe, 0x7e, 0x10); + gc0329_write_register(ViPipe, 0x7f, 0x08); + + gc0329_write_register(ViPipe, 0x9c, 0x00); + gc0329_write_register(ViPipe, 0x9e, 0xc0); + gc0329_write_register(ViPipe, 0x9f, 0x40); + + gc0329_write_register(ViPipe, 0xd0, 0x00); + gc0329_write_register(ViPipe, 0xd2, 0x2c); + gc0329_write_register(ViPipe, 0xd3, 0x80); + + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0xc0, 0x0b); + gc0329_write_register(ViPipe, 0xc1, 0x07); + gc0329_write_register(ViPipe, 0xc2, 0x05); + gc0329_write_register(ViPipe, 0xc6, 0x0b); + gc0329_write_register(ViPipe, 0xc7, 0x07); + gc0329_write_register(ViPipe, 0xc8, 0x05); + gc0329_write_register(ViPipe, 0xba, 0x39); + gc0329_write_register(ViPipe, 0xbb, 0x24); + gc0329_write_register(ViPipe, 0xbc, 0x23); + gc0329_write_register(ViPipe, 0xb4, 0x39); + gc0329_write_register(ViPipe, 0xb5, 0x24); + gc0329_write_register(ViPipe, 0xb6, 0x23); + gc0329_write_register(ViPipe, 0xc3, 0x00); + gc0329_write_register(ViPipe, 0xc4, 0x00); + gc0329_write_register(ViPipe, 0xc5, 0x00); + gc0329_write_register(ViPipe, 0xc9, 0x00); + gc0329_write_register(ViPipe, 0xca, 0x00); + gc0329_write_register(ViPipe, 0xcb, 0x00); + gc0329_write_register(ViPipe, 0xbd, 0x2b); + gc0329_write_register(ViPipe, 0xbe, 0x00); + gc0329_write_register(ViPipe, 0xbf, 0x00); + gc0329_write_register(ViPipe, 0xb7, 0x09); + gc0329_write_register(ViPipe, 0xb8, 0x00); + gc0329_write_register(ViPipe, 0xb9, 0x00); + gc0329_write_register(ViPipe, 0xa8, 0x31); + gc0329_write_register(ViPipe, 0xa9, 0x23); + gc0329_write_register(ViPipe, 0xaa, 0x20); + gc0329_write_register(ViPipe, 0xab, 0x31); + gc0329_write_register(ViPipe, 0xac, 0x23); + gc0329_write_register(ViPipe, 0xad, 0x20); + gc0329_write_register(ViPipe, 0xae, 0x31); + gc0329_write_register(ViPipe, 0xaf, 0x23); + gc0329_write_register(ViPipe, 0xb0, 0x20); + gc0329_write_register(ViPipe, 0xb1, 0x31); + gc0329_write_register(ViPipe, 0xb2, 0x23); + gc0329_write_register(ViPipe, 0xb3, 0x20); + gc0329_write_register(ViPipe, 0xa4, 0x00); + gc0329_write_register(ViPipe, 0xa5, 0x00); + gc0329_write_register(ViPipe, 0xa6, 0x00); + gc0329_write_register(ViPipe, 0xa7, 0x00); + gc0329_write_register(ViPipe, 0xa1, 0x3c); + gc0329_write_register(ViPipe, 0xa2, 0x50); + gc0329_write_register(ViPipe, 0xfe, 0x00); + + gc0329_write_register(ViPipe, 0x05, 0x02); + gc0329_write_register(ViPipe, 0x06, 0x2c); + gc0329_write_register(ViPipe, 0x07, 0x00); + gc0329_write_register(ViPipe, 0x08, 0xb8); + gc0329_write_register(ViPipe, 0xfe, 0x01); + gc0329_write_register(ViPipe, 0x29, 0x00); + gc0329_write_register(ViPipe, 0x2a, 0x60); + gc0329_write_register(ViPipe, 0x2b, 0x02); + gc0329_write_register(ViPipe, 0x2c, 0xa0); + gc0329_write_register(ViPipe, 0x2d, 0x03); + gc0329_write_register(ViPipe, 0x2e, 0x00); + gc0329_write_register(ViPipe, 0x2f, 0x03); + gc0329_write_register(ViPipe, 0x30, 0xc0); + gc0329_write_register(ViPipe, 0x31, 0x05); + gc0329_write_register(ViPipe, 0x32, 0x40); + gc0329_write_register(ViPipe, 0xfe, 0x00); + + gc0329_write_register(ViPipe, 0x44, 0xa2); + gc0329_write_register(ViPipe, 0xf0, 0x07); + gc0329_write_register(ViPipe, 0xf1, 0x01); + + delay_ms(50); + + printf("ViPipe:%d,===GC0329 480P 10fps YUV Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_cmos.c b/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_cmos.c index 3d21b6093..ae5120a40 100644 --- a/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_cmos.c +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_cmos.c @@ -28,6 +28,10 @@ #define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) #define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) #define GC2093_ID 2093 +#define GC2093_I2C_ADDR_1 0x7e +#define GC2093_I2C_ADDR_2 0x37 +#define GC2093_I2C_ADDR_IS_VALID(addr) ((addr) == GC2093_I2C_ADDR_1 || (addr) == GC2093_I2C_ADDR_2) + /**************************************************************************** * global variables * ***************************************************************************/ @@ -1040,6 +1044,11 @@ static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExp /**************************************************************************** * callback structure * ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (GC2093_I2C_ADDR_IS_VALID(s32I2cAddr)) + gc2093_i2c_addr = s32I2cAddr; +} static CVI_S32 gc2093_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) { @@ -1185,6 +1194,7 @@ ISP_SNS_OBJ_S stSnsGc2093_Obj = { .pfnSetInit = sensor_set_init, .pfnMirrorFlip = sensor_mirror_flip, .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, .pfnGetRxAttr = sensor_rx_attr, .pfnExpSensorCb = cmos_init_sensor_exp_function, .pfnExpAeCb = cmos_init_ae_exp_function, diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_cmos_ex.h index d0f8c9869..eeae66b10 100644 --- a/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_cmos_ex.h +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_cmos_ex.h @@ -93,7 +93,7 @@ typedef struct _GC2093_MODE_S { extern ISP_SNS_STATE_S *g_pastGc2093[VI_MAX_PIPE_NUM]; extern ISP_SNS_COMMBUS_U g_aunGc2093_BusInfo[]; extern ISP_SNS_MIRRORFLIP_TYPE_E g_aeGc2093_MirrorFip[VI_MAX_PIPE_NUM]; -extern const CVI_U8 gc2093_i2c_addr; +extern CVI_U8 gc2093_i2c_addr; extern const CVI_U32 gc2093_addr_byte; extern const CVI_U32 gc2093_data_byte; extern void gc2093_init(VI_PIPE ViPipe); diff --git a/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_sensor_ctl.c index c8ce2cfa2..8b73a2f78 100644 --- a/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_sensor_ctl.c +++ b/middleware/v2/component/isp/sensor/cv181x/gcore_gc2093/gc2093_sensor_ctl.c @@ -20,7 +20,7 @@ static void gc2093_linear_1080p30_init(VI_PIPE ViPipe); static void gc2093_wdr_1080p30_init(VI_PIPE ViPipe); -const CVI_U8 gc2093_i2c_addr = 0x37;//0x6e +CVI_U8 gc2093_i2c_addr = 0x37;//0x6e const CVI_U32 gc2093_addr_byte = 2; const CVI_U32 gc2093_data_byte = 1; static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; diff --git a/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/Makefile b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/Makefile new file mode 100644 index 000000000..f0e1a4748 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_mis2008.a +TARGET_SO = $(MW_LIB)/libsns_mis2008.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $(TARGET_A)) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $(TARGET_SO)) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos.c b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos.c new file mode 100644 index 000000000..1cec562bb --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos.c @@ -0,0 +1,1042 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "mis2008_cmos_ex.h" +#include "mis2008_cmos_param.h" + +#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) +#define DIV_0_TO_1_FLOAT(a) ((((a) < 1E-10) && ((a) > -1E-10)) ? 1 : (a)) +#define MIS2008_ID 2008 +#define SENSOR_MIS2008_WIDTH 1920 +#define SENSOR_MIS2008_HEIGHT 1080 +#define MIS2008_I2C_ADDR_1 0x30 +#define MIS2008_I2C_ADDR_2 0x32 +#define MIS2008_I2C_ADDR_IS_VALID(addr) ((addr) == MIS2008_I2C_ADDR_1 || (addr) == MIS2008_I2C_ADDR_2) + +#define MIS2008_EXPACCURACY (1) + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_STATE_S *g_pastMIS2008[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define MIS2008_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastMIS2008[dev]) +#define MIS2008_SENSOR_SET_CTX(dev, pstCtx) (g_pastMIS2008[dev] = pstCtx) +#define MIS2008_SENSOR_RESET_CTX(dev) (g_pastMIS2008[dev] = CVI_NULL) + +ISP_SNS_COMMBUS_U g_aunMIS2008_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = { .s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = { .s8I2cDev = -1} +}; + +CVI_U16 g_au16MIS2008_GainMode[VI_MAX_PIPE_NUM] = {0}; +CVI_U16 g_au16MIS2008_L2SMode[VI_MAX_PIPE_NUM] = {0}; + +ISP_SNS_MIRRORFLIP_TYPE_E g_aeMis2008_MirrorFip[VI_MAX_PIPE_NUM] = {0}; + +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_U32 g_au32InitExposure[VI_MAX_PIPE_NUM] = {0}; +static CVI_U32 g_au32LinesPer500ms[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16InitWBGain[VI_MAX_PIPE_NUM][3] = {{0} }; +static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0}; +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg); +/*****MIS2008 Lines Range*****/ +#define MIS2008_FULL_LINES_MAX (0xFFFF) + +/*****MIS2008 Register Address*****/ +#define MIS2008_EXP_ADDR 0x3100 +#define MIS2008_AGAIN_ADDR 0x3102 +#define MIS2008_DGAIN_ADDR 0x3700 +#define MIS2008_VMAX_ADDR 0x3200 +#define MIS2008_FLIP_MIRROR_ADDR 0x3007 + +#define MIS2008_RES_IS_1080P(w, h) ((w) == 1920 && (h) == 1080) + +static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32FlickerFreq = 50 * 256; + pstAeSnsDft->u32FullLinesMax = MIS2008_FULL_LINES_MAX; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 30); + + pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR; + pstAeSnsDft->stIntTimeAccu.f32Accuracy = MIS2008_EXPACCURACY; + pstAeSnsDft->stIntTimeAccu.f32Offset = 0; + + pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stAgainAccu.f32Accuracy = 1; + + pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE; + pstAeSnsDft->stDgainAccu.f32Accuracy = 1; + + pstAeSnsDft->u32ISPDgainShift = 8; + pstAeSnsDft->u32MinISPDgainTarget = 1 << pstAeSnsDft->u32ISPDgainShift; + pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift; + + if (g_au32LinesPer500ms[ViPipe] == 0) + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 30 / 2; + else + pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe]; + pstAeSnsDft->u32SnsStableFrame = 0; + + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: /*linear mode*/ + pstAeSnsDft->f32Fps = g_astMIS2008_mode[pstSnsState->u8ImgMode].f32MaxFps; + pstAeSnsDft->f32MinFps = g_astMIS2008_mode[pstSnsState->u8ImgMode].f32MinFps; + pstAeSnsDft->au8HistThresh[0] = 0xd; + pstAeSnsDft->au8HistThresh[1] = 0x28; + pstAeSnsDft->au8HistThresh[2] = 0x60; + pstAeSnsDft->au8HistThresh[3] = 0x80; + + pstAeSnsDft->u32MaxAgain = g_astMIS2008_mode[pstSnsState->u8ImgMode].stAgain[0].u32Max; + pstAeSnsDft->u32MinAgain = g_astMIS2008_mode[pstSnsState->u8ImgMode].stAgain[0].u32Min; + pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain; + pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain; + + pstAeSnsDft->u32MaxDgain = g_astMIS2008_mode[pstSnsState->u8ImgMode].stDgain[0].u32Max; + pstAeSnsDft->u32MinDgain = g_astMIS2008_mode[pstSnsState->u8ImgMode].stDgain[0].u32Min; + pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain; + pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain; + + pstAeSnsDft->u8AeCompensation = 40; + pstAeSnsDft->u32InitAESpeed = 64; + pstAeSnsDft->u32InitAETolerance = 5; + pstAeSnsDft->u32AEResponseFrame = 4; + pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR; + pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ? g_au32InitExposure[ViPipe] : 76151; + + pstAeSnsDft->u32MaxIntTime = g_astMIS2008_mode[pstSnsState->u8ImgMode].stExp[0].u32Max; + pstAeSnsDft->u32MinIntTime = g_astMIS2008_mode[pstSnsState->u8ImgMode].stExp[0].u32Min; + pstAeSnsDft->u32MaxIntTimeTarget = 65535; + pstAeSnsDft->u32MinIntTimeTarget = 1; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + +/* the function of sensor set fps */ +static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + CVI_U32 u32VMAX; + CVI_FLOAT f32MaxFps = 0; + CVI_FLOAT f32MinFps = 0; + CVI_U32 u32Vts = 0; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + + CMOS_CHECK_POINTER(pstAeSnsDft); + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u32Vts = g_astMIS2008_mode[pstSnsState->u8ImgMode].u32VtsDef; + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + f32MaxFps = g_astMIS2008_mode[pstSnsState->u8ImgMode].f32MaxFps; + f32MinFps = g_astMIS2008_mode[pstSnsState->u8ImgMode].f32MinFps; + + switch (pstSnsState->u8ImgMode) { + case MIS2008_MODE_1080P30: + if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) { + u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps); + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support Fps: %f\n", f32Fps); + return CVI_FAILURE; + } + u32VMAX = (u32VMAX > MIS2008_FULL_LINES_MAX) ? MIS2008_FULL_LINES_MAX : u32VMAX; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support sensor mode: %d\n", pstSnsState->u8ImgMode); + return CVI_FAILURE; + } + + pstSnsState->u32FLStd = u32VMAX; + //frame high addr + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_0_ADDR].u32Data = ((u32VMAX & 0xFF00)>>8);//data[15:8] => [7:0] //h + pstSnsRegsInfo->astI2cData[LINEAR_VMAX_1_ADDR].u32Data = (u32VMAX & 0xFF);//data[7:0] [7:0] //l + + pstAeSnsDft->f32Fps = f32Fps; + pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * f32Fps / 2; + pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd; + pstAeSnsDft->u32MaxIntTime = (pstSnsState->u32FLStd << 1) - 8; + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstAeSnsDft->u32FullLines = pstSnsState->au32FL[0]; + pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * DIV_0_TO_1_FLOAT(f32Fps)); + + return CVI_SUCCESS; +} + +/* while isp notify ae to update sensor regs, ae call these funcs. */ +static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32TmpIntTime, u32MinTime, u32MaxTime; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(u32IntTime); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + /* linear exposure reg range: + * min : 1 + * max : vts - 1 + * step : 1 + */ + u32MinTime = 1; + u32MaxTime = pstSnsState->au32FL[0] - 1; + u32TmpIntTime = (u32IntTime[0] > u32MaxTime) ? u32MaxTime : u32IntTime[0]; + u32TmpIntTime = (u32TmpIntTime < u32MinTime) ? u32MinTime : u32TmpIntTime; + + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_0_ADDR].u32Data = ((u32TmpIntTime & 0xFF00) >> 8); //data[15:8] => [7:0] //h + pstSnsRegsInfo->astI2cData[LINEAR_SHS1_1_ADDR].u32Data = ((u32TmpIntTime & 0xFF)); //data[7:0] [7:0] //l + + return CVI_SUCCESS; +} + +struct gain_tbl_info_s { + CVI_U16 gainMax; + CVI_U16 idxBase; + CVI_U8 regGain; + CVI_U8 regGainFineBase; + CVI_U8 regGainFineStep; +}; + +static struct gain_tbl_info_s DgainInfo[] = { + { + .gainMax = 1984, + .idxBase = 0, + .regGain = 0x01, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 3008, + .idxBase = 16, + .regGain = 0x02, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 4032, + .idxBase = 32, + .regGain = 0x03, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 5056, + .idxBase = 48, + .regGain = 0x04, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 6080, + .idxBase = 64, + .regGain = 0x05, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 7104, + .idxBase = 80, + .regGain = 0x06, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 8128, + .idxBase = 96, + .regGain = 0x07, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 9152, + .idxBase = 112, + .regGain = 0x08, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 10176, + .idxBase = 128, + .regGain = 0x09, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 11200, + .idxBase = 144, + .regGain = 0x0a, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 12224, + .idxBase = 160, + .regGain = 0x0b, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 13248, + .idxBase = 176, + .regGain = 0x0c, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 14272, + .idxBase = 192, + .regGain = 0x0d, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 15296, + .idxBase = 208, + .regGain = 0x0e, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, + { + .gainMax = 16320, + .idxBase = 224, + .regGain = 0x0f, + .regGainFineBase = 0x10, + .regGainFineStep = 1, + }, +}; + +static CVI_U32 Dgain_table[] = { + 1024, 1088, 1152, 1216, 1280, 1344, 1408, 1472, 1536, 1600, 1664, 1728, 1792, 1856, 1920, + 1984, 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, 2880, + 2944, 3008, 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, 3776, 3840, + 3904, 3968, 4032, 4096, 4160, 4224, 4288, 4352, 4416, 4480, 4544, 4608, 4672, 4736, 4800, + 4864, 4928, 4992, 5056, 5120, 5184, 5248, 5312, 5376, 5440, 5504, 5568, 5632, 5696, 5760, + 5824, 5888, 5952, 6016, 6080, 6144, 6208, 6272, 6336, 6400, 6464, 6528, 6592, 6656, 6720, + 6784, 6848, 6912, 6976, 7040, 7104, 7168, 7232, 7296, 7360, 7424, 7488, 7552, 7616, 7680, + 7744, 7808, 7872, 7936, 8000, 8064, 8128, 8192, 8256, 8320, 8384, 8448, 8512, 8576, 8640, + 8704, 8768, 8832, 8896, 8960, 9024, 9088, 9152, 9216, 9280, 9344, 9408, 9472, 9536, 9600, + 9664, 9728, 9792, 9856, 9920, 9984, 10048, 10112, 10176, 10240, 10304, 10368, 10432, 10496, + 10560, 10624, 10688, 10752, 10816, 10880, 10944, 11008, 11072, 11136, 11200, 11264, 11328, + 11392, 11456, 11520, 11584, 11648, 11712, 11776, 11840, 11904, 11968, 12032, 12096, 12160, + 12224, 12288, 12352, 12416, 12480, 12544, 12608, 12672, 12736, 12800, 12864, 12928, 12992, + 13056, 13120, 13184, 13248, 13312, 13376, 13440, 13504, 13568, 13632, 13696, 13760, 13824, + 13888, 13952, 14016, 14080, 14144, 14208, 14272, 14336, 14400, 14464, 14528, 14592, 14656, + 14720, 14784, 14848, 14912, 14976, 15040, 15104, 15168, 15232, 15296, 15360, 15424, 15488, + 15552, 15616, 15680, 15744, 15808, 15872, 15936, 16000, 16064, 16128, 16192, 16256, 16320 +}; + +static CVI_U32 Again_table[] = { + 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, + 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, + 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, + 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, + 4096, 4224, 4352, 4480, 4608, 4736, 4864, 4992, 5120, 5248, 5376, 5504, 5632, 5760, 5888, 6016, + 6144, 6272, 6400, 6528, 6656, 6784, 6912, 7040, 7168, 7296, 7424, 7552, 7680, 7808, 7936, 8064, + 8192, 8448, 8704, 8960, 9216, 9472, 9728, 9984, 10240,10496,10752,11008,11264,11520,11776,12032, + 12288,12544,12800,13056,13312,13568,13824,14080,14336,14592,14848,15104,15360,15616,15872,16128 +}; + +static const CVI_U32 again_table_size = ARRAY_SIZE(Again_table); +static const CVI_U32 dgain_table_size = ARRAY_SIZE(Dgain_table); + +static CVI_S32 cmos_again_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32AgainLin, CVI_U32 *pu32AgainDb) +{ + CVI_U32 i; + + (void) ViPipe; + + CMOS_CHECK_POINTER(pu32AgainLin); + CMOS_CHECK_POINTER(pu32AgainDb); + + if (*pu32AgainLin >= Again_table[again_table_size - 1]) { + *pu32AgainLin = Again_table[again_table_size - 1]; + *pu32AgainDb = again_table_size - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < again_table_size; i++) { + if (*pu32AgainLin < Again_table[i]) { + *pu32AgainLin = Again_table[i - 1]; + *pu32AgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_dgain_calc_table(VI_PIPE ViPipe, CVI_U32 *pu32DgainLin, CVI_U32 *pu32DgainDb) +{ + CVI_U32 i; + + (void)ViPipe; + + CMOS_CHECK_POINTER(pu32DgainLin); + CMOS_CHECK_POINTER(pu32DgainDb); + + if (*pu32DgainLin >= Dgain_table[dgain_table_size - 1]) { + *pu32DgainLin = Dgain_table[dgain_table_size - 1]; + *pu32DgainDb = dgain_table_size - 1; + return CVI_SUCCESS; + } + + for (i = 1; i < dgain_table_size; i++) { + if (*pu32DgainLin < Dgain_table[i]) { + *pu32DgainLin = Dgain_table[i - 1]; + *pu32DgainDb = i - 1; + break; + } + } + return CVI_SUCCESS; +} + +static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu32Dgain) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + CVI_U32 u32Again; + CVI_U32 u32Dgain; + struct gain_tbl_info_s *info; + int i, tbl_num; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pu32Again); + CMOS_CHECK_POINTER(pu32Dgain); + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + + u32Again = pu32Again[0]; + u32Dgain = pu32Dgain[0]; + + pstSnsRegsInfo->astI2cData[LINEAR_AGAIN_ADDR].u32Data = (u32Again & 0x7F); + + /* find Dgain register setting. */ + tbl_num = sizeof(DgainInfo)/sizeof(struct gain_tbl_info_s); + for (i = tbl_num - 1; i >= 0; i--) { + info = &DgainInfo[i]; + + if (u32Dgain >= info->idxBase) + break; + } + + pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_ADDR].u32Data = ((info->regGain & 0x0e)>>1); + u32Dgain = info->regGainFineBase + (u32Dgain - info->idxBase) * info->regGainFineStep; + pstSnsRegsInfo->astI2cData[LINEAR_D_FINEGAIN_ADDR].u32Data =((info->regGain & 0x01)<<7) | ((u32Dgain & 0x0F)<<3); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AE_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_ae_default = cmos_get_ae_default; + pstExpFuncs->pfn_cmos_fps_set = cmos_fps_set; + //pstExpFuncs->pfn_cmos_slow_framerate_set = cmos_slow_framerate_set; + pstExpFuncs->pfn_cmos_inttime_update = cmos_inttime_update; + pstExpFuncs->pfn_cmos_gains_update = cmos_gains_update; + pstExpFuncs->pfn_cmos_again_calc_table = cmos_again_calc_table; + pstExpFuncs->pfn_cmos_dgain_calc_table = cmos_dgain_calc_table; + //pstExpFuncs->pfn_cmos_get_inttime_max = cmos_get_inttime_max; + //pstExpFuncs->pfn_cmos_ae_fswdr_attr_set = cmos_ae_fswdr_attr_set; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstAwbSnsDft); + + memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S)); + + pstAwbSnsDft->u16InitGgain = 1024; + pstAwbSnsDft->u8AWBRunInterval = 1; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs) +{ + CMOS_CHECK_POINTER(pstExpFuncs); + + memset(pstExpFuncs, 0, sizeof(AWB_SENSOR_EXP_FUNC_S)); + + pstExpFuncs->pfn_cmos_get_awb_default = cmos_get_awb_default; + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef) +{ + (void) ViPipe; + + memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc) +{ + (void) ViPipe; + + CMOS_CHECK_POINTER(pstBlc); + + memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + + memcpy(pstBlc, + &g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S)); + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const MIS2008_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstMode = &g_astMIS2008_mode[pstSnsState->u8ImgMode]; + + if (pstSnsState->enWDRMode != WDR_MODE_NONE) { + pstIspCfg->frm_num = 2; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S)); + } else { + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstSnsState->bSyncInit = CVI_FALSE; + + switch (u8Mode) { + case WDR_MODE_NONE: + pstSnsState->u8ImgMode = MIS2008_MODE_1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstSnsState->u32FLStd = g_astMIS2008_mode[pstSnsState->u8ImgMode].u32VtsDef; + syslog(LOG_INFO, "linear mode\n"); + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + + pstSnsState->au32FL[0] = pstSnsState->u32FLStd; + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime)); + + return CVI_SUCCESS; +} + +static CVI_U32 sensor_cmp_wdr_size(ISP_SNS_ISP_INFO_S *pstWdr1, ISP_SNS_ISP_INFO_S *pstWdr2) +{ + CVI_U32 i; + + if (pstWdr1->frm_num != pstWdr2->frm_num) + goto _mismatch; + for (i = 0; i < 2; i++) { + if (pstWdr1->img_size[i].stSnsSize.u32Width != pstWdr2->img_size[i].stSnsSize.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stSnsSize.u32Height != pstWdr2->img_size[i].stSnsSize.u32Height) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32X != pstWdr2->img_size[i].stWndRect.s32X) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.s32Y != pstWdr2->img_size[i].stWndRect.s32Y) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Width != pstWdr2->img_size[i].stWndRect.u32Width) + goto _mismatch; + if (pstWdr1->img_size[i].stWndRect.u32Height != pstWdr2->img_size[i].stWndRect.u32Height) + goto _mismatch; + } + + return 0; +_mismatch: + return 1; +} + +static CVI_U32 sensor_cmp_cif_wdr(ISP_SNS_CIF_INFO_S *pstWdr1, ISP_SNS_CIF_INFO_S *pstWdr2) +{ + if (pstWdr1->wdr_manual.l2s_distance != pstWdr2->wdr_manual.l2s_distance) + goto _mismatch; + if (pstWdr1->wdr_manual.lsef_length != pstWdr2->wdr_manual.lsef_length) + goto _mismatch; + + return 0; +_mismatch: + return 1; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + CVI_U32 i; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg1 = CVI_NULL; + ISP_I2C_DATA_S *pstI2c_data = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + pstSnsRegsInfo = &pstSnsSyncInfo->snsCfg; + pstCfg0 = &pstSnsState->astSyncInfo[0]; + pstCfg1 = &pstSnsState->astSyncInfo[1]; + pstI2c_data = pstCfg0->snsCfg.astI2cData; + + if ((pstSnsState->bSyncInit == CVI_FALSE) || (pstSnsRegsInfo->bConfig == CVI_FALSE)) { + pstCfg0->snsCfg.enSnsType = SNS_I2C_TYPE; + pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunMIS2008_BusInfo[ViPipe].s8I2cDev; + pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0; + pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE; + pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM; + + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + pstI2c_data[i].bUpdate = CVI_TRUE; + pstI2c_data[i].u8DevAddr = mis2008_i2c_addr; + pstI2c_data[i].u32AddrByteNum = mis2008_addr_byte; + pstI2c_data[i].u32DataByteNum = mis2008_data_byte; + } + switch (pstSnsState->enWDRMode) { + case WDR_MODE_NONE: + //Linear Mode Regs + pstI2c_data[LINEAR_SHS1_0_ADDR].u32RegAddr = MIS2008_EXP_ADDR; + pstI2c_data[LINEAR_SHS1_1_ADDR].u32RegAddr = MIS2008_EXP_ADDR + 1; + + pstI2c_data[LINEAR_AGAIN_ADDR].u32RegAddr = MIS2008_AGAIN_ADDR; + pstI2c_data[LINEAR_DGAIN_ADDR].u32RegAddr = MIS2008_DGAIN_ADDR; + pstI2c_data[LINEAR_D_FINEGAIN_ADDR].u32RegAddr = MIS2008_DGAIN_ADDR + 1; + + pstI2c_data[LINEAR_VMAX_0_ADDR].u32RegAddr = MIS2008_VMAX_ADDR; + pstI2c_data[LINEAR_VMAX_1_ADDR].u32RegAddr = MIS2008_VMAX_ADDR + 1; + pstI2c_data[LINEAR_FLIP_MIRROR_ADDR].u32RegAddr = MIS2008_FLIP_MIRROR_ADDR; + break; + default: + CVI_TRACE_SNS(CVI_DBG_ERR, "NOT support this mode!\n"); + return CVI_FAILURE; + } + pstSnsState->bSyncInit = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + /* recalcualte WDR size */ + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + pstCfg0->ispCfg.need_update = CVI_TRUE; + } else { + pstCfg0->snsCfg.need_update = CVI_FALSE; + for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) { + if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE; + } else { + pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE; + pstCfg0->snsCfg.need_update = CVI_TRUE; + } + } + /* check update isp crop or not */ + pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ? + CVI_TRUE : CVI_FALSE); + + /* check update cif wdr manual or not */ + pstCfg0->cifCfg.need_update = (sensor_cmp_cif_wdr(&pstCfg0->cifCfg, &pstCfg1->cifCfg) ? + CVI_TRUE : CVI_FALSE); + } + + pstSnsRegsInfo->bConfig = CVI_FALSE; + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + pstSnsState->au32FL[1] = pstSnsState->au32FL[0]; + pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR_ADDR].bDropFrm = CVI_FALSE; + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + pstSnsState->bSyncInit = CVI_FALSE; + + if (pstSensorImageMode->f32Fps <= 30) { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (MIS2008_RES_IS_1080P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) { + u8SensorImageMode = MIS2008_MODE_1080P30; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } else { + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL; + ISP_SNS_ISP_INFO_S *pstIspCfg0 = CVI_NULL; + CVI_U8 value = 0; + CVI_U8 start_x, start_y; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg; + pstIspCfg0 = &pstSnsState->astSyncInfo[0].ispCfg; + + if (pstSnsState->bInit == CVI_TRUE && g_aeMis2008_MirrorFip[ViPipe] != eSnsMirrorFlip) { + switch (eSnsMirrorFlip) { + case ISP_SNS_NORMAL: + value |= 0; + start_x = 4; + start_y = 4; + break; + case ISP_SNS_MIRROR: + value |= 0x01; + start_x = 5; + start_y = 4; + break; + case ISP_SNS_FLIP: + value |= 0x02; + start_x = 4; + start_y = 5; + break; + case ISP_SNS_MIRROR_FLIP: + value |= 0x03; + start_x = 5; + start_y = 5; + break; + default: + return; + } + + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR_ADDR].u32Data = value; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR_ADDR].bDropFrm = 1; + pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR_ADDR].u8DropFrmNum = 1; + pstIspCfg0->img_size[0].stWndRect.s32X = start_x; + pstIspCfg0->img_size[0].stWndRect.s32Y = start_y; + g_aeMis2008_MirrorFip[ViPipe] = eSnsMirrorFlip; + } + +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + const MIS2008_MODE_S *pstMode = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->bSyncInit = CVI_FALSE; + pstSnsState->u8ImgMode = MIS2008_MODE_1080P30; + pstSnsState->enWDRMode = WDR_MODE_NONE; + pstMode = &g_astMIS2008_mode[pstSnsState->u8ImgMode]; + pstSnsState->u32FLStd = pstMode->u32VtsDef; + pstSnsState->au32FL[0] = pstMode->u32VtsDef; + pstSnsState->au32FL[1] = pstMode->u32VtsDef; + + memset(&pstSnsState->astSyncInfo[0], 0, sizeof(ISP_SNS_SYNC_INFO_S)); + memset(&pstSnsState->astSyncInfo[1], 0, sizeof(ISP_SNS_SYNC_INFO_S)); +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &mis2008_rx_attr, sizeof(*pstRxAttr)); + + pstRxAttr->img_size.width = g_astMIS2008_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astMIS2008_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE; + } + + return CVI_SUCCESS; + +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &mis2008_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->stMclkAttr.bMclkEn) + pstRxAttr->mclk.cam = pstRxInitAttr->stMclkAttr.u8Mclk; + + if (pstRxInitAttr->MipiDev >= 2) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } else { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = mis2008_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = mis2008_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_set_wdr_mode = cmos_set_wdr_mode; + + pstSensorExpFunc->pfn_cmos_get_isp_default = cmos_get_isp_default; + pstSensorExpFunc->pfn_cmos_get_isp_black_level = cmos_get_blc_default; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ +static CVI_VOID sensor_patch_i2c_addr(CVI_S32 s32I2cAddr) +{ + if (MIS2008_I2C_ADDR_IS_VALID(s32I2cAddr)) + mis2008_i2c_addr = s32I2cAddr; +} + +static CVI_S32 mis2008_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunMIS2008_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + MIS2008_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + MIS2008_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + MIS2008_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + AE_SENSOR_REGISTER_S stAeRegister; + AWB_SENSOR_REGISTER_S stAwbRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = MIS2008_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_ae_exp_function(&stAeRegister.stAeExp); + s32Ret |= CVI_AE_SensorRegCallBack(ViPipe, pstAeLib, &stSnsAttrInfo, &stAeRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = cmos_init_awb_exp_function(&stAwbRegister.stAwbExp); + s32Ret |= CVI_AWB_SensorRegCallBack(ViPipe, pstAwbLib, &stSnsAttrInfo, &stAwbRegister); + + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function to awb lib failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + CVI_S32 s32Ret; + + CMOS_CHECK_POINTER(pstAeLib); + CMOS_CHECK_POINTER(pstAwbLib); + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, MIS2008_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AE_SensorUnRegCallBack(ViPipe, pstAeLib, MIS2008_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to ae lib failed!\n"); + return s32Ret; + } + + s32Ret = CVI_AWB_SensorUnRegCallBack(ViPipe, pstAwbLib, MIS2008_ID); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function to awb lib failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_set_init(VI_PIPE ViPipe, ISP_INIT_ATTR_S *pstInitAttr) +{ + CMOS_CHECK_POINTER(pstInitAttr); + + g_au32InitExposure[ViPipe] = pstInitAttr->u32Exposure; + g_au32LinesPer500ms[ViPipe] = pstInitAttr->u32LinesPer500ms; + g_au16InitWBGain[ViPipe][0] = pstInitAttr->u16WBRgain; + g_au16InitWBGain[ViPipe][1] = pstInitAttr->u16WBGgain; + g_au16InitWBGain[ViPipe][2] = pstInitAttr->u16WBBgain; + g_au16SampleRgain[ViPipe] = pstInitAttr->u16SampleRgain; + g_au16SampleBgain[ViPipe] = pstInitAttr->u16SampleBgain; + g_au16MIS2008_GainMode[ViPipe] = pstInitAttr->enGainMode; + g_au16MIS2008_L2SMode[ViPipe] = pstInitAttr->enL2SMode; + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsMIS2008_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnStandby = mis2008_standby, + .pfnRestart = mis2008_restart, + .pfnMirrorFlip = sensor_mirror_flip, + .pfnWriteReg = mis2008_write_register, + .pfnReadReg = mis2008_read_register, + .pfnSetBusInfo = mis2008_set_bus_info, + .pfnSetInit = sensor_set_init, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = sensor_patch_i2c_addr, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = cmos_init_ae_exp_function, + .pfnSnsProbe = mis2008_probe, +}; + diff --git a/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos_ex.h new file mode 100644 index 000000000..a758d2735 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos_ex.h @@ -0,0 +1,79 @@ +#ifndef __MIS2008_CMOS_EX_H_ +#define __MIS2008_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + + +enum mis2008_linear_regs_e { + LINEAR_SHS1_0_ADDR, + LINEAR_SHS1_1_ADDR, + LINEAR_SHS1_2_ADDR, + LINEAR_AGAIN_ADDR, + LINEAR_DGAIN_ADDR, + LINEAR_D_FINEGAIN_ADDR, + LINEAR_VMAX_0_ADDR, + LINEAR_VMAX_1_ADDR, + LINEAR_FLIP_MIRROR_ADDR, + LINEAR_REGS_NUM +}; + +typedef enum _MIS2008_MODE_E { + MIS2008_MODE_1080P30 = 0, + MIS2008_MODE_NUM +} MIS2008_MODE_E; + +typedef struct _MIS2008_MODE_S { + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_LARGE_S stExp[2]; + SNS_ATTR_LARGE_S stAgain[2]; + SNS_ATTR_LARGE_S stDgain[2]; + char name[64]; +} MIS2008_MODE_S; + +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ + +extern ISP_SNS_STATE_S *g_pastMIS2008[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunMIS2008_BusInfo[]; +extern CVI_U16 g_au16MIS2008_GainMode[]; +extern CVI_U16 g_au16MIS2008_L2SMode[]; +extern CVI_U8 mis2008_i2c_addr; +extern const CVI_U32 mis2008_addr_byte; +extern const CVI_U32 mis2008_data_byte; +extern void mis2008_init(VI_PIPE ViPipe); +extern void mis2008_exit(VI_PIPE ViPipe); +extern void mis2008_standby(VI_PIPE ViPipe); +extern void mis2008_restart(VI_PIPE ViPipe); +extern int mis2008_write_register(VI_PIPE ViPipe, int addr, int data); +extern int mis2008_read_register(VI_PIPE ViPipe, int addr); +extern void mis2008_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip); +extern int mis2008_probe(VI_PIPE ViPipe); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __MIS2008_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos_param.h new file mode 100644 index 000000000..1de9a7f95 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_cmos_param.h @@ -0,0 +1,126 @@ +#ifndef __MIS2008_CMOS_PARAM_H_ +#define __MIS2008_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "mis2008_cmos_ex.h" + +static const MIS2008_MODE_S g_astMIS2008_mode[MIS2008_MODE_NUM] = { + [MIS2008_MODE_1080P30] = { + .name = "1080p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1928, + .u32Height = 1088, + }, + .stWndRect = { + .s32X = 8, + .s32Y = 8, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1928, + .u32Height = 1088, + }, + }, + .f32MaxFps = 30, + .f32MinFps = 1, /* 1500 * 30 / 0x7FFF*/ + .u32HtsDef = 2200, + .u32VtsDef = 1125, + .stExp[0] = {//exp_time + .u32Min = 1, + .u32Max = 1125 - 1, //exp_max + .u32Def = 128, + .u32Step = 1, + }, + .stAgain[0] = { + .u32Min = 1024, + .u32Max = 16128, + .u32Def = 1024, + .u32Step = 1, + }, + .stDgain[0] = { + .u32Min = 1024, + .u32Max = 16320, + .u32Def = 1024, + .u32Step = 1, + }, + }, +}; + +static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = { + .bUpdate = CVI_TRUE, + .blcAttr = { + .Enable = 1, + .enOpType = OP_TYPE_AUTO, + .stManual = {64, 64, 64, 64, 0, 0, 0, 0 +#ifdef ARCH_CV182X + , 1040, 1040, 1040, 1040 +#endif + }, + .stAuto = { + {64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64}, + {64, 64, 64, 64, 64, 64, 64, 64, /*8*/64, 64, 64, 64, 64, 64, 64, 64}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +#ifdef ARCH_CV182X + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + /*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + /*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + /*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, + {1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040, + /*8*/1040, 1040, 1040, 1040, 1040, 1040, 1040, 1040}, +#endif + }, + }, +}; + +struct combo_dev_attr_s mis2008_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_200M, + .mipi_attr = { + .raw_data_type = RAW_DATA_12BIT, + .lane_id = {2, 0, 1, -1, -1}, + .pn_swap = {1, 1, 1, 0, 0}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + .dphy = { + .enable = 1, + .hs_settle = 8, + }, + }, + .mclk = { + .cam = 1, + .freq = CAMPLL_FREQ_27M, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __MIS2008_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_sensor_ctl.c new file mode 100644 index 000000000..4f2523af4 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/imgds_mis2008/mis2008_sensor_ctl.c @@ -0,0 +1,397 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "mis2008_cmos_ex.h" + +static void mis2008_linear_1080p30_init(VI_PIPE ViPipe); + +CVI_U8 mis2008_i2c_addr = 0x30; /* I2C Address of MIS2008 */ +const CVI_U32 mis2008_addr_byte = 2; +const CVI_U32 mis2008_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ... (VI_MAX_PIPE_NUM - 1)] = -1}; + +int mis2008_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + int ret; + + u8DevNum = g_aunMIS2008_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, mis2008_i2c_addr); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int mis2008_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int mis2008_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return CVI_FAILURE; + + if (mis2008_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, mis2008_addr_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return ret; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, mis2008_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return ret; + } + + // pack read back data + data = 0; + if (mis2008_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int mis2008_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (mis2008_addr_byte == 2) { + buf[idx] = (addr >> 8) & 0xff; + idx++; + buf[idx] = addr & 0xff; + idx++; + } + + if (mis2008_data_byte == 1) { + buf[idx] = data & 0xff; + idx++; + } + + ret = write(g_fd[ViPipe], buf, mis2008_addr_byte + mis2008_data_byte); + if (ret < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + return CVI_SUCCESS; +} + +static void delay_ms(int ms) +{ + usleep(ms * 1000); +} + +void mis2008_standby(VI_PIPE ViPipe) +{ + mis2008_write_register(ViPipe, 0x3006, 0x02); +} + +void mis2008_restart(VI_PIPE ViPipe) +{ + mis2008_write_register(ViPipe, 0x3006, 0x01); +} + +void mis2008_default_reg_init(VI_PIPE ViPipe) +{ + CVI_U32 i; + + for (i = 0; i < g_pastMIS2008[ViPipe]->astSyncInfo[0].snsCfg.u32RegNum; i++) { + mis2008_write_register(ViPipe, + g_pastMIS2008[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32RegAddr, + g_pastMIS2008[ViPipe]->astSyncInfo[0].snsCfg.astI2cData[i].u32Data); + } +} + +#define MIS2008_CHIP_ID_HI_ADDR 0x3000 +#define MIS2008_CHIP_ID_LO_ADDR 0x3001 +#define MIS2008_CHIP_ID 0x2008 + +int mis2008_probe(VI_PIPE ViPipe) +{ + int nVal; + CVI_U16 chip_id; + + if (mis2008_i2c_init(ViPipe) != CVI_SUCCESS) + return CVI_FAILURE; + + delay_ms(5); + + nVal = mis2008_read_register(ViPipe, MIS2008_CHIP_ID_HI_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id = (nVal & 0xFF) << 8; + nVal = mis2008_read_register(ViPipe, MIS2008_CHIP_ID_LO_ADDR); + if (nVal < 0) { + CVI_TRACE_SNS(CVI_DBG_ERR, "read sensor id error.\n"); + return nVal; + } + chip_id |= (nVal & 0xFF); + + if (chip_id != MIS2008_CHIP_ID) { + CVI_TRACE_SNS(CVI_DBG_ERR, "Sensor ID Mismatch! Use the wrong sensor??\n"); + return CVI_FAILURE; + } + + return CVI_SUCCESS; +} + + +void mis2008_init(VI_PIPE ViPipe) +{ + mis2008_i2c_init(ViPipe); + + mis2008_linear_1080p30_init(ViPipe); + + g_pastMIS2008[ViPipe]->bInit = CVI_TRUE; +} + +void mis2008_exit(VI_PIPE ViPipe) +{ + mis2008_i2c_exit(ViPipe); +} + +/* 1080p30 */ +static void mis2008_linear_1080p30_init(VI_PIPE ViPipe) +{ + /* [ParaList] */ + mis2008_write_register(ViPipe, 0x300a ,0x01); + mis2008_write_register(ViPipe, 0x3006 ,0x02); + mis2008_write_register(ViPipe, 0x3201 ,0x65); + mis2008_write_register(ViPipe, 0x3200 ,0x04); + mis2008_write_register(ViPipe, 0x3203 ,0x98); + mis2008_write_register(ViPipe, 0x3202 ,0x08); + + mis2008_write_register(ViPipe, 0x3205 ,0x04); + mis2008_write_register(ViPipe, 0x3204 ,0x00); + mis2008_write_register(ViPipe, 0x3207 ,0x43); + mis2008_write_register(ViPipe, 0x3206 ,0x04); + + mis2008_write_register(ViPipe, 0x3209 ,0x04); + mis2008_write_register(ViPipe, 0x3208 ,0x00); + mis2008_write_register(ViPipe, 0x320b ,0x8b); + mis2008_write_register(ViPipe, 0x320a ,0x07); + + //mis2008_write_register(ViPipe, 0x3007 ,0x00); + mis2008_write_register(ViPipe, 0x3007 ,0x00); + mis2008_write_register(ViPipe, 0x3300 ,0x21); + mis2008_write_register(ViPipe, 0x3301 ,0x00); + mis2008_write_register(ViPipe, 0x3302 ,0x02); + mis2008_write_register(ViPipe, 0x3303 ,0x06); + mis2008_write_register(ViPipe, 0x330d ,0x00); + mis2008_write_register(ViPipe, 0x330b ,0x01); + mis2008_write_register(ViPipe, 0x330f ,0x0f); + mis2008_write_register(ViPipe, 0x3013 ,0x00); + mis2008_write_register(ViPipe, 0x3637 ,0x1e); + mis2008_write_register(ViPipe, 0x3900 ,0x07); + mis2008_write_register(ViPipe, 0x2107 ,0x00); + mis2008_write_register(ViPipe, 0x330e ,0x00); + + mis2008_write_register(ViPipe, 0x3900 ,0x07); + mis2008_write_register(ViPipe, 0x2108 ,0x01); + mis2008_write_register(ViPipe, 0x3c40 ,0x8c); + mis2008_write_register(ViPipe, 0x3b01 ,0x3f); + mis2008_write_register(ViPipe, 0x3b03 ,0x3f); + mis2008_write_register(ViPipe, 0x3902 ,0x01); + mis2008_write_register(ViPipe, 0x3904 ,0x00); + mis2008_write_register(ViPipe, 0x3903 ,0x00); + mis2008_write_register(ViPipe, 0x3906 ,0x1e); + mis2008_write_register(ViPipe, 0x3905 ,0x00); + mis2008_write_register(ViPipe, 0x3908 ,0x71); + mis2008_write_register(ViPipe, 0x3907 ,0x10); + mis2008_write_register(ViPipe, 0x390a ,0xff); + mis2008_write_register(ViPipe, 0x3909 ,0x1f); + mis2008_write_register(ViPipe, 0x390c ,0x67); + mis2008_write_register(ViPipe, 0x390b ,0x03); + mis2008_write_register(ViPipe, 0x390e ,0x77); + mis2008_write_register(ViPipe, 0x390d ,0x00); + mis2008_write_register(ViPipe, 0x3910 ,0x71); + mis2008_write_register(ViPipe, 0x390f ,0x10); + mis2008_write_register(ViPipe, 0x3912 ,0xff); + mis2008_write_register(ViPipe, 0x3911 ,0x1f); + mis2008_write_register(ViPipe, 0x3919 ,0x00); + mis2008_write_register(ViPipe, 0x3918 ,0x00); + mis2008_write_register(ViPipe, 0x391b ,0x91); + mis2008_write_register(ViPipe, 0x391a ,0x01); + mis2008_write_register(ViPipe, 0x3983 ,0x5a); + mis2008_write_register(ViPipe, 0x3982 ,0x00); + mis2008_write_register(ViPipe, 0x3985 ,0x0f); + mis2008_write_register(ViPipe, 0x3984 ,0x00); + mis2008_write_register(ViPipe, 0x391d ,0x00); + mis2008_write_register(ViPipe, 0x391c ,0x00); + mis2008_write_register(ViPipe, 0x391f ,0x65); + mis2008_write_register(ViPipe, 0x391e ,0x10); + mis2008_write_register(ViPipe, 0x3921 ,0xff); + mis2008_write_register(ViPipe, 0x3920 ,0x1f); + mis2008_write_register(ViPipe, 0x3923 ,0xff); + mis2008_write_register(ViPipe, 0x3922 ,0x1f); + mis2008_write_register(ViPipe, 0x3932 ,0x00); + mis2008_write_register(ViPipe, 0x3931 ,0x00); + mis2008_write_register(ViPipe, 0x3934 ,0x65); + mis2008_write_register(ViPipe, 0x3933 ,0x01); + mis2008_write_register(ViPipe, 0x393f ,0x6c); + mis2008_write_register(ViPipe, 0x393e ,0x00); + mis2008_write_register(ViPipe, 0x3941 ,0x67); + mis2008_write_register(ViPipe, 0x3940 ,0x00); + mis2008_write_register(ViPipe, 0x3943 ,0x55); + mis2008_write_register(ViPipe, 0x3942 ,0x01); + mis2008_write_register(ViPipe, 0x3945 ,0xc2); + mis2008_write_register(ViPipe, 0x3944 ,0x02); + mis2008_write_register(ViPipe, 0x3925 ,0x95); + mis2008_write_register(ViPipe, 0x3924 ,0x00); + mis2008_write_register(ViPipe, 0x3927 ,0xe1); + mis2008_write_register(ViPipe, 0x3926 ,0x02); + mis2008_write_register(ViPipe, 0x3947 ,0x74); + mis2008_write_register(ViPipe, 0x3946 ,0x01); + mis2008_write_register(ViPipe, 0x3949 ,0xda); + mis2008_write_register(ViPipe, 0x3948 ,0x0e); + mis2008_write_register(ViPipe, 0x394b ,0x42); + mis2008_write_register(ViPipe, 0x394a ,0x03); + mis2008_write_register(ViPipe, 0x394d ,0xf2); + mis2008_write_register(ViPipe, 0x394c ,0x01); + mis2008_write_register(ViPipe, 0x3913 ,0x01); + mis2008_write_register(ViPipe, 0x3915 ,0x0f); + mis2008_write_register(ViPipe, 0x3914 ,0x00); + mis2008_write_register(ViPipe, 0x3917 ,0x67); + mis2008_write_register(ViPipe, 0x3916 ,0x03); + mis2008_write_register(ViPipe, 0x392a ,0x1e); + mis2008_write_register(ViPipe, 0x3929 ,0x00); + mis2008_write_register(ViPipe, 0x392c ,0x0f); + mis2008_write_register(ViPipe, 0x392b ,0x00); + mis2008_write_register(ViPipe, 0x392e ,0x0f); + mis2008_write_register(ViPipe, 0x392d ,0x00); + mis2008_write_register(ViPipe, 0x3930 ,0x6e); + mis2008_write_register(ViPipe, 0x392f ,0x03); + mis2008_write_register(ViPipe, 0x397f ,0x00); + mis2008_write_register(ViPipe, 0x397e ,0x00); + mis2008_write_register(ViPipe, 0x3981 ,0x77); + mis2008_write_register(ViPipe, 0x3980 ,0x00); + mis2008_write_register(ViPipe, 0x395d ,0x80); + mis2008_write_register(ViPipe, 0x395c ,0x10); + mis2008_write_register(ViPipe, 0x3962 ,0x9e); + mis2008_write_register(ViPipe, 0x3961 ,0x10); + mis2008_write_register(ViPipe, 0x3977 ,0x22); + mis2008_write_register(ViPipe, 0x3976 ,0x00); + mis2008_write_register(ViPipe, 0x3978 ,0x00); + mis2008_write_register(ViPipe, 0x3979 ,0x04); + mis2008_write_register(ViPipe, 0x396d ,0xc2); + mis2008_write_register(ViPipe, 0x396c ,0x02); + mis2008_write_register(ViPipe, 0x396f ,0xc2); + mis2008_write_register(ViPipe, 0x396e ,0x02); + mis2008_write_register(ViPipe, 0x3971 ,0xc2); + mis2008_write_register(ViPipe, 0x3970 ,0x02); + mis2008_write_register(ViPipe, 0x3973 ,0xc2); + mis2008_write_register(ViPipe, 0x3972 ,0x02); + + mis2008_write_register(ViPipe, 0x3900 ,0x01); + mis2008_write_register(ViPipe, 0x3600 ,0x00); + mis2008_write_register(ViPipe, 0x3707 ,0x00); + mis2008_write_register(ViPipe, 0x3708 ,0x80); + mis2008_write_register(ViPipe, 0x3709 ,0x00); + mis2008_write_register(ViPipe, 0x370a ,0x80); + mis2008_write_register(ViPipe, 0x370b ,0x00); + mis2008_write_register(ViPipe, 0x370c ,0x80); + mis2008_write_register(ViPipe, 0x370d ,0x00); + mis2008_write_register(ViPipe, 0x370e ,0x80); + mis2008_write_register(ViPipe, 0x3006 ,0x00); + + + mis2008_write_register(ViPipe, 0x3012 ,0x01); + mis2008_write_register(ViPipe, 0x3600 ,0x13); + mis2008_write_register(ViPipe, 0x3601 ,0x02); + mis2008_write_register(ViPipe, 0x360e ,0x00); + mis2008_write_register(ViPipe, 0x360f ,0x00); + mis2008_write_register(ViPipe, 0x3610 ,0x02); + mis2008_write_register(ViPipe, 0x3707 ,0x00); + mis2008_write_register(ViPipe, 0x3708 ,0x40); + mis2008_write_register(ViPipe, 0x3709 ,0x00); + mis2008_write_register(ViPipe, 0x370a ,0x40); + mis2008_write_register(ViPipe, 0x370b ,0x00); + mis2008_write_register(ViPipe, 0x370c ,0x40); + mis2008_write_register(ViPipe, 0x370d ,0x00); + mis2008_write_register(ViPipe, 0x370e ,0x40); + mis2008_write_register(ViPipe, 0x3800 ,0x01); + mis2008_write_register(ViPipe, 0x3a03 ,0x03); + mis2008_write_register(ViPipe, 0x3a02 ,0x0b); + mis2008_write_register(ViPipe, 0x3a08 ,0x34); + mis2008_write_register(ViPipe, 0x3a1b ,0x54); + mis2008_write_register(ViPipe, 0x3a1e ,0x80); + mis2008_write_register(ViPipe, 0x3100 ,0x04); + mis2008_write_register(ViPipe, 0x3101 ,0x64); + mis2008_write_register(ViPipe, 0x3a1c ,0x10); + mis2008_write_register(ViPipe, 0x3a0C ,0x04); + mis2008_write_register(ViPipe, 0x3a0D ,0x12); + mis2008_write_register(ViPipe, 0x3a0E ,0x15); + mis2008_write_register(ViPipe, 0x3a0F ,0x18); + mis2008_write_register(ViPipe, 0x3a10 ,0x20); + mis2008_write_register(ViPipe, 0x3a11 ,0x3c); + + mis2008_default_reg_init(ViPipe); + + + delay_ms(100); + + printf("ViPipe:%d,===MIS2008 1080P 30fps 12bit LINE Init OK!===\n", ViPipe); +} + diff --git a/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/Makefile b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/Makefile new file mode 100644 index 000000000..3ff418d00 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/Makefile @@ -0,0 +1,36 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE=../../../../../../$(shell echo $(MW_VER))/Makefile.param + include $(PARAM_FILE) +endif + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I./include +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) +TARGET_A = $(MW_LIB)/libsns_tp2863.a +TARGET_SO = $(MW_LIB)/libsns_tp2863.so + +EXTRA_CFLAGS = $(INCS) +EXTRA_LDFLAGS = + +.PHONY : clean all +all : $(TARGET_A) $(TARGET_SO) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET_A): $(OBJS) + @$(AR) $(ARFLAGS) $@ $(OBJS) + @echo -e $(YELLOW)[LINK]$(END)[$(notdir $(AR))] $(notdir $@) + +$(TARGET_SO): $(OBJS) + @$(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) -o $@ --start-group $(OBJS) --end-group + @echo -e $(GREEN)[LINK]$(END)[$(notdir $(LD))] $(notdir $@) + +clean: + @rm -f $(OBJS) $(DEPS) $(TARGET_A) $(TARGET_SO) + +-include $(DEPS) diff --git a/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos.c b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos.c new file mode 100644 index 000000000..43f70486d --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos.c @@ -0,0 +1,336 @@ +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include "cvi_type.h" +#include "cvi_comm_video.h" +#include +#else +#include +#include +#include +#endif +#include "cvi_debug.h" +#include "cvi_comm_sns.h" +#include "cvi_sns_ctrl.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_ae.h" +#include "cvi_awb.h" +#include "cvi_isp.h" + +#include "tp2863_cmos_ex.h" +#include "tp2863_cmos_param.h" + +/**************************************************************************** + * global variables * + ****************************************************************************/ + +ISP_SNS_COMMBUS_U g_aunTP2863_BusInfo[VI_MAX_PIPE_NUM] = { + [0] = {.s8I2cDev = 0}, + [1 ... VI_MAX_PIPE_NUM - 1] = {.s8I2cDev = -1}}; + +ISP_SNS_STATE_S *g_pastTP2863[VI_MAX_PIPE_NUM] = {CVI_NULL}; + +#define TP2863_SENSOR_GET_CTX(dev, pstCtx) (pstCtx = g_pastTP2863[dev]) +#define TP2863_SENSOR_SET_CTX(dev, pstCtx) (g_pastTP2863[dev] = pstCtx) +#define TP2863_SENSOR_RESET_CTX(dev) (g_pastTP2863[dev] = CVI_NULL) + +#define TP2863_RES_IS_720P_25(w, h, f) ((w) == 1280 && (h) == 720 && (f) == 25) +#define TP2863_RES_IS_720P_30(w, h, f) ((w) == 1280 && (h) == 720 && (f) == 30) +#define TP2863_RES_IS_1080P_25(w, h, f) ((w) == 1920 && (h) == 1080 && (f) == 25) +#define TP2863_RES_IS_1080P_30(w, h, f) ((w) == 1920 && (h) == 1080 && (f) == 30) +#define TP2863_ID 0x2863 +/**************************************************************************** + * local variables and functions * + ****************************************************************************/ +static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg) +{ + const TP2863_MODE_S *pstMode = CVI_NULL; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstMode = &g_astTP2863_mode[pstSnsState->u8ImgMode]; + pstIspCfg->frm_num = 1; + memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSnsSyncInfo) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + ISP_SNS_SYNC_INFO_S *pstCfg0 = CVI_NULL; + + CMOS_CHECK_POINTER(pstSnsSyncInfo); + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + pstCfg0 = &pstSnsState->astSyncInfo[0]; + cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg); + memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S)); + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S *pstSensorImageMode) +{ + CVI_U8 u8SensorImageMode = 0; + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + CMOS_CHECK_POINTER(pstSensorImageMode); + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + + u8SensorImageMode = pstSnsState->u8ImgMode; + + if (pstSensorImageMode->f32Fps <= 30) + { + if (pstSnsState->enWDRMode == WDR_MODE_NONE) { + if (TP2863_RES_IS_720P_25(pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps)) { + u8SensorImageMode = TP2863_MODE_720P_25P; + } else if (TP2863_RES_IS_720P_30(pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps)) { + u8SensorImageMode = TP2863_MODE_720P_30P; + } else if (TP2863_RES_IS_1080P_25(pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps)) { + u8SensorImageMode = TP2863_MODE_1080P_25P; + } else if (TP2863_RES_IS_1080P_30(pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps)) { + u8SensorImageMode = TP2863_MODE_1080P_30P; + } else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + else { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + } + else + { + CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n", + pstSensorImageMode->u16Width, + pstSensorImageMode->u16Height, + pstSensorImageMode->f32Fps, + pstSnsState->enWDRMode); + return CVI_FAILURE; + } + + if ((pstSnsState->bInit == CVI_TRUE) && (u8SensorImageMode == pstSnsState->u8ImgMode)) + { + /* Don't need to switch SensorImageMode */ + return CVI_FAILURE; + } + + pstSnsState->u8ImgMode = u8SensorImageMode; + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_global_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER_VOID(pstSnsState); + + pstSnsState->bInit = CVI_FALSE; + pstSnsState->u8ImgMode = TP2863_MODE_1080P_25P; + pstSnsState->enWDRMode = WDR_MODE_NONE; +} + +static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr) +{ + ISP_SNS_STATE_S *pstSnsState = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pstSnsState); + CMOS_CHECK_POINTER(pstSnsState); + CMOS_CHECK_POINTER(pstRxAttr); + + memcpy(pstRxAttr, &tp2863_rx_attr, sizeof(*pstRxAttr)); + // CVI_TRACE_SNS(CVI_DBG_INFO, "get tp2863_rx0_attr\n"); + + pstRxAttr->img_size.width = g_astTP2863_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width; + pstRxAttr->img_size.height = g_astTP2863_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_patch_rx_attr(RX_INIT_ATTR_S *pstRxInitAttr) +{ + SNS_COMBO_DEV_ATTR_S *pstRxAttr = &tp2863_rx_attr; + int i; + + CMOS_CHECK_POINTER(pstRxInitAttr); + + if (pstRxInitAttr->MipiDev >= VI_MAX_DEV_NUM) + return CVI_SUCCESS; + + pstRxAttr->devno = pstRxInitAttr->MipiDev; + + if (pstRxAttr->input_mode == INPUT_MODE_MIPI) + { + struct mipi_dev_attr_s *attr = &pstRxAttr->mipi_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) + { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + else + { + struct lvds_dev_attr_s *attr = &pstRxAttr->lvds_attr; + + for (i = 0; i < MIPI_LANE_NUM + 1; i++) + { + attr->lane_id[i] = pstRxInitAttr->as16LaneId[i]; + attr->pn_swap[i] = pstRxInitAttr->as8PNSwap[i]; + } + } + + return CVI_SUCCESS; +} + +static CVI_S32 cmos_init_sensor_exp_function(ISP_SENSOR_EXP_FUNC_S *pstSensorExpFunc) +{ + CMOS_CHECK_POINTER(pstSensorExpFunc); + + memset(pstSensorExpFunc, 0, sizeof(ISP_SENSOR_EXP_FUNC_S)); + + pstSensorExpFunc->pfn_cmos_sensor_init = tp2863_init; + pstSensorExpFunc->pfn_cmos_sensor_exit = tp2863_exit; + pstSensorExpFunc->pfn_cmos_sensor_global_init = sensor_global_init; + pstSensorExpFunc->pfn_cmos_set_image_mode = cmos_set_image_mode; + pstSensorExpFunc->pfn_cmos_get_sns_reg_info = cmos_get_sns_regs_info; + + return CVI_SUCCESS; +} + +/**************************************************************************** + * callback structure * + ****************************************************************************/ + +static CVI_S32 tp2863_set_bus_info(VI_PIPE ViPipe, ISP_SNS_COMMBUS_U unSNSBusInfo) +{ + g_aunTP2863_BusInfo[ViPipe].s8I2cDev = unSNSBusInfo.s8I2cDev; + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_ctx_init(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + + if (pastSnsStateCtx == CVI_NULL) + { + pastSnsStateCtx = (ISP_SNS_STATE_S *)malloc(sizeof(ISP_SNS_STATE_S)); + if (pastSnsStateCtx == CVI_NULL) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "Isp[%d] SnsCtx malloc memory failed!\n", ViPipe); + return -ENOMEM; + } + } + + memset(pastSnsStateCtx, 0, sizeof(ISP_SNS_STATE_S)); + + TP2863_SENSOR_SET_CTX(ViPipe, pastSnsStateCtx); + + return CVI_SUCCESS; +} + +static CVI_VOID sensor_ctx_exit(VI_PIPE ViPipe) +{ + ISP_SNS_STATE_S *pastSnsStateCtx = CVI_NULL; + + TP2863_SENSOR_GET_CTX(ViPipe, pastSnsStateCtx); + SENSOR_FREE(pastSnsStateCtx); + TP2863_SENSOR_RESET_CTX(ViPipe); +} + +static CVI_S32 sensor_register_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + (void)pstAeLib; + (void)pstAwbLib; + + CVI_S32 s32Ret; + ISP_SENSOR_REGISTER_S stIspRegister; + ISP_SNS_ATTR_INFO_S stSnsAttrInfo; + + s32Ret = sensor_ctx_init(ViPipe); + + if (s32Ret != CVI_SUCCESS) + return CVI_FAILURE; + + stSnsAttrInfo.eSensorId = TP2863_ID; + + s32Ret = cmos_init_sensor_exp_function(&stIspRegister.stSnsExp); + s32Ret |= CVI_ISP_SensorRegCallBack(ViPipe, &stSnsAttrInfo, &stIspRegister); + + if (s32Ret != CVI_SUCCESS) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor register callback function failed!\n"); + return s32Ret; + } + + return CVI_SUCCESS; +} + +static CVI_S32 sensor_unregister_callback(VI_PIPE ViPipe, ALG_LIB_S *pstAeLib, ALG_LIB_S *pstAwbLib) +{ + (void)pstAeLib; + (void)pstAwbLib; + + CVI_S32 s32Ret; + + s32Ret = CVI_ISP_SensorUnRegCallBack(ViPipe, TP2863_ID); + if (s32Ret != CVI_SUCCESS) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "sensor unregister callback function failed!\n"); + return s32Ret; + } + + sensor_ctx_exit(ViPipe); + + return CVI_SUCCESS; +} + +ISP_SNS_OBJ_S stSnsTP2863_Obj = { + .pfnRegisterCallback = sensor_register_callback, + .pfnUnRegisterCallback = sensor_unregister_callback, + .pfnMirrorFlip = CVI_NULL, + .pfnStandby = CVI_NULL, + .pfnRestart = CVI_NULL, + .pfnWriteReg = tp2863_write_register, + .pfnReadReg = tp2863_read_register, + .pfnSetBusInfo = tp2863_set_bus_info, + .pfnSetInit = CVI_NULL, + .pfnPatchRxAttr = sensor_patch_rx_attr, + .pfnPatchI2cAddr = CVI_NULL, + .pfnGetRxAttr = sensor_rx_attr, + .pfnExpSensorCb = cmos_init_sensor_exp_function, + .pfnExpAeCb = CVI_NULL, + .pfnSnsProbe = CVI_NULL, +}; diff --git a/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos_ex.h new file mode 100644 index 000000000..b4d6fa844 --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos_ex.h @@ -0,0 +1,63 @@ +#ifndef __TP2863_CMOS_EX_H_ +#define __TP2863_CMOS_EX_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" + +typedef enum _TP2863_MODE_E +{ + TP2863_MODE_1080P_30P, + TP2863_MODE_1080P_25P, + TP2863_MODE_720P_30P, + TP2863_MODE_720P_25P, + TP2863_MODE_NUM +} TP2863_MODE_E; +typedef struct _TP2863_MODE_S +{ + ISP_WDR_SIZE_S astImg[2]; + CVI_FLOAT f32MaxFps; + CVI_FLOAT f32MinFps; + CVI_U32 u32HtsDef; + CVI_U32 u32VtsDef; + SNS_ATTR_S stExp[2]; + SNS_ATTR_S stAgain[2]; + SNS_ATTR_S stDgain[2]; + CVI_U8 u8DgainReg; + char name[64]; +} TP2863_MODE_S; +/**************************************************************************** + * external variables and functions * + ****************************************************************************/ +extern ISP_SNS_STATE_S *g_pastTP2863[VI_MAX_PIPE_NUM]; +extern ISP_SNS_COMMBUS_U g_aunTP2863_BusInfo[]; +extern const CVI_U8 tp2863_i2c_addr; +extern const CVI_U32 tp2863_addr_byte; +extern const CVI_U32 tp2863_data_byte; +extern void tp2863_init(VI_PIPE ViPipe); +extern void tp2863_exit(VI_PIPE ViPipe); +extern void tp2863_standby(VI_PIPE ViPipe); +extern void tp2863_restart(VI_PIPE ViPipe); +extern int tp2863_write_register(VI_PIPE ViPipe, int addr, int data); +extern int tp2863_read_register(VI_PIPE ViPipe, int addr); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + +#endif /* __TP2863_CMOS_EX_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos_param.h new file mode 100644 index 000000000..a43e22daf --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_cmos_param.h @@ -0,0 +1,123 @@ +#ifndef __TP2863_CMOS_PARAM_H_ +#define __TP2863_CMOS_PARAM_H_ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif + +#ifdef ARCH_CV182X +#include +#include +#include "cvi_type.h" +#else +#include +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "tp2863_cmos_ex.h" + +static const TP2863_MODE_S g_astTP2863_mode[TP2863_MODE_NUM] = { + [TP2863_MODE_1080P_30P] = { + .name = "1080p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + }, + }, + [TP2863_MODE_1080P_25P] = { + .name = "1080p25", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1920, + .u32Height = 1080, + }, + .stMaxSize = { + .u32Width = 1920, + .u32Height = 1080, + }, + }, + }, + [TP2863_MODE_720P_30P] = { + .name = "720p30", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1280, + .u32Height = 720, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1280, + .u32Height = 720, + }, + .stMaxSize = { + .u32Width = 1280, + .u32Height = 720, + }, + }, + }, + [TP2863_MODE_720P_25P] = { + .name = "720p25", + .astImg[0] = { + .stSnsSize = { + .u32Width = 1280, + .u32Height = 720, + }, + .stWndRect = { + .s32X = 0, + .s32Y = 0, + .u32Width = 1280, + .u32Height = 720, + }, + .stMaxSize = { + .u32Width = 1280, + .u32Height = 720, + }, + }, + }, +}; + +struct combo_dev_attr_s tp2863_rx_attr = { + .input_mode = INPUT_MODE_MIPI, + .mac_clk = RX_MAC_CLK_400M, + .mipi_attr = { + .raw_data_type = YUV422_8BIT, + .lane_id = {0, 2, 1, -1, -1}, + .wdr_mode = CVI_MIPI_WDR_MODE_NONE, + }, + .mclk = { + .cam = 0, + .freq = CAMPLL_FREQ_NONE, + }, + .devno = 0, +}; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + + +#endif /* __TP2863_CMOS_PARAM_H_ */ diff --git a/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_sensor_ctrl.c b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_sensor_ctrl.c new file mode 100644 index 000000000..e57d9187c --- /dev/null +++ b/middleware/v2/component/isp/sensor/cv181x/techpoint_tp2863/tp2863_sensor_ctrl.c @@ -0,0 +1,593 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ARCH_CV182X +#include +#include "cvi_comm_video.h" +#else +#include +#include +#endif +#include "cvi_sns_ctrl.h" +#include "tp2863_cmos_ex.h" + +const CVI_U8 tp2863_i2c_addr = 0x44; /* I2C slave address of TP2863, SA0=0:0x44, SA0=1:0x45*/ +const CVI_U32 tp2863_addr_byte = 1; +const CVI_U32 tp2863_data_byte = 1; +static int g_fd[VI_MAX_PIPE_NUM] = {[0 ...(VI_MAX_PIPE_NUM - 1)] = -1}; + +#define TP2863_BLUE_SCREEN 0 + +enum +{ + CH_1 = 0, + CH_2 = 1, + CH_ALL = 4, + MIPI_PAGE = 8, +}; + +enum +{ + STD_TVI, // TVI + STD_HDA, // AHD +}; + +enum +{ + HD25, + HD30, // 1280x720 + FHD25, + FHD30, // 1920x1080 +}; + +enum +{ + MIPI_1CH2LANE_297M, + MIPI_1CH2LANE_594M, + MIPI_2CH2LANE_594M, + MIPI_2CH2LANE_297M, +}; + +int tp2863_i2c_init(VI_PIPE ViPipe) +{ + char acDevFile[16] = {0}; + CVI_U8 u8DevNum; + int ret; + + if (g_fd[ViPipe] >= 0) + return CVI_SUCCESS; + + u8DevNum = g_aunTP2863_BusInfo[ViPipe].s8I2cDev; + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + syslog(LOG_DEBUG, "open %s\n", acDevFile); + + g_fd[ViPipe] = open(acDevFile, O_RDWR, 0600); + + if (g_fd[ViPipe] < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(g_fd[ViPipe], I2C_SLAVE_FORCE, tp2863_i2c_addr); + if (ret < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_SLAVE_FORCE error!\n"); + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int tp2863_i2c_exit(VI_PIPE ViPipe) +{ + if (g_fd[ViPipe] >= 0) + { + close(g_fd[ViPipe]); + g_fd[ViPipe] = -1; + return CVI_SUCCESS; + } + return CVI_FAILURE; +} + +int tp2863_read_register(VI_PIPE ViPipe, int addr) +{ + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (g_fd[ViPipe] < 0) + return 0; + + if (tp2863_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(g_fd[ViPipe], buf, tp2863_addr_byte); + if (ret < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return 0; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(g_fd[ViPipe], buf, tp2863_data_byte); + if (ret < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_READ error!\n"); + return 0; + } + + // pack read back data + data = 0; + if (tp2863_data_byte == 2) + { + data = buf[0] << 8; + data += buf[1]; + } + else + { + data = buf[0]; + } + + syslog(LOG_DEBUG, "i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int tp2863_write_register(VI_PIPE ViPipe, int addr, int data) +{ + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (g_fd[ViPipe] < 0) + return CVI_SUCCESS; + + if (tp2863_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + if (tp2863_data_byte == 2) + buf[idx++] = (data >> 8) & 0xff; + + // add data byte 0 + buf[idx++] = data & 0xff; + + ret = write(g_fd[ViPipe], buf, tp2863_addr_byte + tp2863_data_byte); + if (ret < 0) + { + CVI_TRACE_SNS(CVI_DBG_ERR, "I2C_WRITE error!\n"); + return CVI_FAILURE; + } + syslog(LOG_DEBUG, "i2c w 0x%x 0x%x\n", addr, data); + +#if 0 // read back checing + ret = tp2863_read_register(ViPipe, addr); + if (ret != data) + syslog(LOG_DEBUG, "i2c readback-check fail, 0x%x != 0x%x\n", ret, data); +#endif + return CVI_SUCCESS; +} + +void TP2863_decoder_init(VI_PIPE ViPipe, unsigned char ch, unsigned char fmt, unsigned char std) +{ + unsigned char tmp; + const unsigned char REG42_43[] = {0x01, 0x02, 0x00, 0x00, 0x03}; + const unsigned char MASK42_43[] = {0xfe, 0xfd, 0xff, 0xff, 0xfc}; + + tp2863_write_register(ViPipe, 0x40, ch); + tp2863_write_register(ViPipe, 0x06, 0x12); // default value + tp2863_write_register(ViPipe, 0x50, 0x00); // VIN1/3 + tp2863_write_register(ViPipe, 0x51, 0x00); + tp2863_write_register(ViPipe, 0x54, 0x03); + + if (HD25 == fmt) + { + tmp = tp2863_read_register(ViPipe, 0x42); + tmp |= REG42_43[ch]; + tp2863_write_register(ViPipe, 0x42, tmp); + + tmp = tp2863_read_register(ViPipe, 0x43); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x43, tmp); + + tp2863_write_register(ViPipe, 0x02, 0x42); + tp2863_write_register(ViPipe, 0x07, 0xc0); + tp2863_write_register(ViPipe, 0x0b, 0xc0); + tp2863_write_register(ViPipe, 0x0c, 0x13); + tp2863_write_register(ViPipe, 0x0d, 0x50); + + tp2863_write_register(ViPipe, 0x15, 0x13); + tp2863_write_register(ViPipe, 0x16, 0x15); + tp2863_write_register(ViPipe, 0x17, 0x00); + tp2863_write_register(ViPipe, 0x18, 0x19); + tp2863_write_register(ViPipe, 0x19, 0xd0); + tp2863_write_register(ViPipe, 0x1a, 0x25); + tp2863_write_register(ViPipe, 0x1c, 0x07); // 1280*720, 25fps + tp2863_write_register(ViPipe, 0x1d, 0xbc); // 1280*720, 25fps + + tp2863_write_register(ViPipe, 0x20, 0x30); + tp2863_write_register(ViPipe, 0x21, 0x84); + tp2863_write_register(ViPipe, 0x22, 0x36); + tp2863_write_register(ViPipe, 0x23, 0x3c); + + tp2863_write_register(ViPipe, 0x2b, 0x60); + tp2863_write_register(ViPipe, 0x2c, 0x0a); + tp2863_write_register(ViPipe, 0x2d, 0x30); + tp2863_write_register(ViPipe, 0x2e, 0x70); + + tp2863_write_register(ViPipe, 0x30, 0x48); + tp2863_write_register(ViPipe, 0x31, 0xbb); + tp2863_write_register(ViPipe, 0x32, 0x2e); + tp2863_write_register(ViPipe, 0x33, 0x90); + + tp2863_write_register(ViPipe, 0x35, 0x25); + tp2863_write_register(ViPipe, 0x39, 0x08); + + if (STD_HDA == std) + { + tp2863_write_register(ViPipe, 0x02, 0x46); + + tp2863_write_register(ViPipe, 0x0d, 0x71); + + tp2863_write_register(ViPipe, 0x20, 0x40); + tp2863_write_register(ViPipe, 0x21, 0x46); + + tp2863_write_register(ViPipe, 0x25, 0xfe); + tp2863_write_register(ViPipe, 0x26, 0x01); + + tp2863_write_register(ViPipe, 0x2c, 0x3a); + tp2863_write_register(ViPipe, 0x2d, 0x5a); + tp2863_write_register(ViPipe, 0x2e, 0x40); + + tp2863_write_register(ViPipe, 0x30, 0x9e); + tp2863_write_register(ViPipe, 0x31, 0x20); + tp2863_write_register(ViPipe, 0x32, 0x10); + tp2863_write_register(ViPipe, 0x33, 0x90); + } + } + else if (HD30 == fmt) + { + tmp = tp2863_read_register(ViPipe, 0x42); + tmp |= REG42_43[ch]; + tp2863_write_register(ViPipe, 0x42, tmp); + + tmp = tp2863_read_register(ViPipe, 0x43); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x43, tmp); + + tp2863_write_register(ViPipe, 0x02, 0x42); + tp2863_write_register(ViPipe, 0x07, 0xc0); + tp2863_write_register(ViPipe, 0x0b, 0xc0); + tp2863_write_register(ViPipe, 0x0c, 0x13); + tp2863_write_register(ViPipe, 0x0d, 0x50); + + tp2863_write_register(ViPipe, 0x15, 0x13); + tp2863_write_register(ViPipe, 0x16, 0x15); + tp2863_write_register(ViPipe, 0x17, 0x00); + tp2863_write_register(ViPipe, 0x18, 0x19); + tp2863_write_register(ViPipe, 0x19, 0xd0); + tp2863_write_register(ViPipe, 0x1a, 0x25); + tp2863_write_register(ViPipe, 0x1c, 0x06); // 1280*720, 30fps + tp2863_write_register(ViPipe, 0x1d, 0x72); // 1280*720, 30fps + + tp2863_write_register(ViPipe, 0x20, 0x30); + tp2863_write_register(ViPipe, 0x21, 0x84); + tp2863_write_register(ViPipe, 0x22, 0x36); + tp2863_write_register(ViPipe, 0x23, 0x3c); + + tp2863_write_register(ViPipe, 0x2b, 0x60); + tp2863_write_register(ViPipe, 0x2c, 0x0a); + tp2863_write_register(ViPipe, 0x2d, 0x30); + tp2863_write_register(ViPipe, 0x2e, 0x70); + + tp2863_write_register(ViPipe, 0x30, 0x48); + tp2863_write_register(ViPipe, 0x31, 0xbb); + tp2863_write_register(ViPipe, 0x32, 0x2e); + tp2863_write_register(ViPipe, 0x33, 0x90); + + tp2863_write_register(ViPipe, 0x35, 0x25); + tp2863_write_register(ViPipe, 0x39, 0x08); + + if (STD_HDA == std) + { + tp2863_write_register(ViPipe, 0x02, 0x46); + + tp2863_write_register(ViPipe, 0x0d, 0x70); + + tp2863_write_register(ViPipe, 0x20, 0x40); + tp2863_write_register(ViPipe, 0x21, 0x46); + + tp2863_write_register(ViPipe, 0x25, 0xfe); + tp2863_write_register(ViPipe, 0x26, 0x01); + + tp2863_write_register(ViPipe, 0x2c, 0x3a); + tp2863_write_register(ViPipe, 0x2d, 0x5a); + tp2863_write_register(ViPipe, 0x2e, 0x40); + + tp2863_write_register(ViPipe, 0x30, 0x9d); + tp2863_write_register(ViPipe, 0x31, 0xca); + tp2863_write_register(ViPipe, 0x32, 0x01); + tp2863_write_register(ViPipe, 0x33, 0xd0); + } + } + else if (FHD25 == fmt) + { + tmp = tp2863_read_register(ViPipe, 0x42); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x42, tmp); + + tmp = tp2863_read_register(ViPipe, 0x43); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x43, tmp); + + tp2863_write_register(ViPipe, 0x02, 0x40); + tp2863_write_register(ViPipe, 0x07, 0xc0); + tp2863_write_register(ViPipe, 0x0b, 0xc0); + tp2863_write_register(ViPipe, 0x0c, 0x03); + tp2863_write_register(ViPipe, 0x0d, 0x50); + + tp2863_write_register(ViPipe, 0x15, 0x03); + tp2863_write_register(ViPipe, 0x16, 0xd2); + tp2863_write_register(ViPipe, 0x17, 0x80); + tp2863_write_register(ViPipe, 0x18, 0x29); + tp2863_write_register(ViPipe, 0x19, 0x38); + tp2863_write_register(ViPipe, 0x1a, 0x47); + + tp2863_write_register(ViPipe, 0x1c, 0x0a); // 1920*1080, 25fps + tp2863_write_register(ViPipe, 0x1d, 0x50); // + + tp2863_write_register(ViPipe, 0x20, 0x30); + tp2863_write_register(ViPipe, 0x21, 0x84); + tp2863_write_register(ViPipe, 0x22, 0x36); + tp2863_write_register(ViPipe, 0x23, 0x3c); + + tp2863_write_register(ViPipe, 0x2b, 0x60); + tp2863_write_register(ViPipe, 0x2c, 0x0a); + tp2863_write_register(ViPipe, 0x2d, 0x30); + tp2863_write_register(ViPipe, 0x2e, 0x70); + + tp2863_write_register(ViPipe, 0x30, 0x48); + tp2863_write_register(ViPipe, 0x31, 0xbb); + tp2863_write_register(ViPipe, 0x32, 0x2e); + tp2863_write_register(ViPipe, 0x33, 0x90); + + tp2863_write_register(ViPipe, 0x35, 0x05); + tp2863_write_register(ViPipe, 0x39, 0x0C); + + if (STD_HDA == std) + { + tp2863_write_register(ViPipe, 0x02, 0x44); + + tp2863_write_register(ViPipe, 0x0d, 0x73); + + tp2863_write_register(ViPipe, 0x15, 0x01); + tp2863_write_register(ViPipe, 0x16, 0xf0); + tp2863_write_register(ViPipe, 0x18, 0x2a); + tp2863_write_register(ViPipe, 0x20, 0x3c); + tp2863_write_register(ViPipe, 0x21, 0x46); + + tp2863_write_register(ViPipe, 0x25, 0xfe); + tp2863_write_register(ViPipe, 0x26, 0x0d); + + tp2863_write_register(ViPipe, 0x2c, 0x3a); + tp2863_write_register(ViPipe, 0x2d, 0x54); + tp2863_write_register(ViPipe, 0x2e, 0x40); + + tp2863_write_register(ViPipe, 0x30, 0xa5); + tp2863_write_register(ViPipe, 0x31, 0x86); + tp2863_write_register(ViPipe, 0x32, 0xfb); + tp2863_write_register(ViPipe, 0x33, 0x60); + } + } + else if (FHD30 == fmt) + { + tmp = tp2863_read_register(ViPipe, 0x42); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x42, tmp); + + tmp = tp2863_read_register(ViPipe, 0x43); + tmp &= MASK42_43[ch]; + tp2863_write_register(ViPipe, 0x43, tmp); + + tp2863_write_register(ViPipe, 0x02, 0x40); + tp2863_write_register(ViPipe, 0x07, 0xc0); + tp2863_write_register(ViPipe, 0x0b, 0xc0); + tp2863_write_register(ViPipe, 0x0c, 0x03); + tp2863_write_register(ViPipe, 0x0d, 0x50); + + tp2863_write_register(ViPipe, 0x15, 0x03); + tp2863_write_register(ViPipe, 0x16, 0xd2); + tp2863_write_register(ViPipe, 0x17, 0x80); + tp2863_write_register(ViPipe, 0x18, 0x29); + tp2863_write_register(ViPipe, 0x19, 0x38); + tp2863_write_register(ViPipe, 0x1a, 0x47); + tp2863_write_register(ViPipe, 0x1c, 0x08); // 1920*1080, 30fps + tp2863_write_register(ViPipe, 0x1d, 0x98); // + + tp2863_write_register(ViPipe, 0x20, 0x30); + tp2863_write_register(ViPipe, 0x21, 0x84); + tp2863_write_register(ViPipe, 0x22, 0x36); + tp2863_write_register(ViPipe, 0x23, 0x3c); + + tp2863_write_register(ViPipe, 0x2b, 0x60); + tp2863_write_register(ViPipe, 0x2c, 0x0a); + tp2863_write_register(ViPipe, 0x2d, 0x30); + tp2863_write_register(ViPipe, 0x2e, 0x70); + + tp2863_write_register(ViPipe, 0x30, 0x48); + tp2863_write_register(ViPipe, 0x31, 0xbb); + tp2863_write_register(ViPipe, 0x32, 0x2e); + tp2863_write_register(ViPipe, 0x33, 0x90); + + tp2863_write_register(ViPipe, 0x35, 0x05); + tp2863_write_register(ViPipe, 0x39, 0x0C); + + if (STD_HDA == std) + { + tp2863_write_register(ViPipe, 0x02, 0x44); + + tp2863_write_register(ViPipe, 0x0d, 0x72); + + tp2863_write_register(ViPipe, 0x15, 0x01); + tp2863_write_register(ViPipe, 0x16, 0xf0); + tp2863_write_register(ViPipe, 0x18, 0x2a); + + tp2863_write_register(ViPipe, 0x20, 0x38); + tp2863_write_register(ViPipe, 0x21, 0x46); + + tp2863_write_register(ViPipe, 0x25, 0xfe); + tp2863_write_register(ViPipe, 0x26, 0x0d); + + tp2863_write_register(ViPipe, 0x2c, 0x3a); + tp2863_write_register(ViPipe, 0x2d, 0x54); + tp2863_write_register(ViPipe, 0x2e, 0x40); + + tp2863_write_register(ViPipe, 0x30, 0xa5); + tp2863_write_register(ViPipe, 0x31, 0x95); + tp2863_write_register(ViPipe, 0x32, 0xe0); + tp2863_write_register(ViPipe, 0x33, 0x60); + } + } +} + +void TP2863_mipi_out(VI_PIPE ViPipe, unsigned char output) +{ + // mipi setting + tp2863_write_register(ViPipe, 0x40, MIPI_PAGE); // MIPI page + tp2863_write_register(ViPipe, 0x02, 0x78); + tp2863_write_register(ViPipe, 0x03, 0x70); + tp2863_write_register(ViPipe, 0x04, 0x70); + tp2863_write_register(ViPipe, 0x05, 0x70); + tp2863_write_register(ViPipe, 0x06, 0x70); + + tp2863_write_register(ViPipe, 0x13, 0xef); + tp2863_write_register(ViPipe, 0x20, 0x00); + tp2863_write_register(ViPipe, 0x21, 0x22); + tp2863_write_register(ViPipe, 0x22, 0x20); + tp2863_write_register(ViPipe, 0x23, 0x9e); + + if (MIPI_1CH2LANE_297M == output) + { + tp2863_write_register(ViPipe, 0x21, 0x12); + tp2863_write_register(ViPipe, 0x14, 0x41); + tp2863_write_register(ViPipe, 0x15, 0x02); + tp2863_write_register(ViPipe, 0x2a, 0x04); + tp2863_write_register(ViPipe, 0x2b, 0x03); + tp2863_write_register(ViPipe, 0x2c, 0x09); + tp2863_write_register(ViPipe, 0x2e, 0x02); + tp2863_write_register(ViPipe, 0x10, 0xa0); + tp2863_write_register(ViPipe, 0x10, 0x20); + } + else if (MIPI_1CH2LANE_594M == output) + { + tp2863_write_register(ViPipe, 0x21, 0x12); + tp2863_write_register(ViPipe, 0x14, 0x00); // clk + tp2863_write_register(ViPipe, 0x15, 0x01); // clk + tp2863_write_register(ViPipe, 0x2a, 0x08); // LPX + tp2863_write_register(ViPipe, 0x2b, 0x08); // PREP + tp2863_write_register(ViPipe, 0x2c, 0x10); // TRAIL/HS ZERO + tp2863_write_register(ViPipe, 0x2e, 0x0a); + tp2863_write_register(ViPipe, 0x10, 0xa0); + tp2863_write_register(ViPipe, 0x10, 0x20); + } + else if (MIPI_2CH2LANE_297M == output) + { + tp2863_write_register(ViPipe, 0x21, 0x22); + tp2863_write_register(ViPipe, 0x14, 0x41); + tp2863_write_register(ViPipe, 0x15, 0x02); + tp2863_write_register(ViPipe, 0x2a, 0x04); + tp2863_write_register(ViPipe, 0x2b, 0x03); + tp2863_write_register(ViPipe, 0x2c, 0x09); + tp2863_write_register(ViPipe, 0x2e, 0x02); + tp2863_write_register(ViPipe, 0x10, 0xa0); + tp2863_write_register(ViPipe, 0x10, 0x20); + } + else if (MIPI_2CH2LANE_594M == output) + { + tp2863_write_register(ViPipe, 0x21, 0x22); + tp2863_write_register(ViPipe, 0x14, 0x00); + tp2863_write_register(ViPipe, 0x15, 0x01); + tp2863_write_register(ViPipe, 0x2a, 0x08); + tp2863_write_register(ViPipe, 0x2b, 0x08); + tp2863_write_register(ViPipe, 0x2c, 0x10); + tp2863_write_register(ViPipe, 0x2e, 0x0a); + tp2863_write_register(ViPipe, 0x10, 0xa0); + tp2863_write_register(ViPipe, 0x10, 0x20); + } + + /* Enable MIPI CSI2 output */ + tp2863_write_register(ViPipe, 0x28, 0x02); + tp2863_write_register(ViPipe, 0x28, 0x00); +} + +void TP2863_reg_init(VI_PIPE ViPipe, CVI_U8 u8ImgMode) +{ + if (u8ImgMode == TP2863_MODE_1080P_30P) + { + TP2863_decoder_init(ViPipe, CH_1, FHD30, STD_HDA); + TP2863_mipi_out(ViPipe, MIPI_1CH2LANE_297M); + printf("Techpoint TP2863 1080 FHD30\n"); + } + else if (u8ImgMode == TP2863_MODE_1080P_25P) + { + TP2863_decoder_init(ViPipe, CH_1, FHD25, STD_HDA); + TP2863_mipi_out(ViPipe, MIPI_1CH2LANE_297M); + printf("Techpoint TP2863 720 FHD25\n"); + } + else if (u8ImgMode == TP2863_MODE_720P_30P) + { + TP2863_decoder_init(ViPipe, CH_1, HD30, STD_HDA); + TP2863_mipi_out(ViPipe, MIPI_1CH2LANE_297M); + printf("Techpoint TP2863 720 HD30\n"); + } + else if (u8ImgMode == TP2863_MODE_720P_25P) + { + TP2863_decoder_init(ViPipe, CH_1, HD25, STD_HDA); + TP2863_mipi_out(ViPipe, MIPI_1CH2LANE_297M); + printf("Techpoint TP2863 720 HD25\n"); + } +} + +void tp2863_init(VI_PIPE ViPipe) +{ + tp2863_i2c_init(ViPipe); + + syslog(LOG_DEBUG, "Loading Techpoint TP2863 sensor\n"); + + // check sensor chip id + tp2863_write_register(ViPipe, 0x40, 0x0); + if (tp2863_read_register(ViPipe, 0xfe) != 0x28 || + tp2863_read_register(ViPipe, 0xff) != 0x63) + { + syslog(LOG_DEBUG, "read TP2863 chip id fail\n"); + return; + } + + TP2863_reg_init(ViPipe, g_pastTP2863[ViPipe]->u8ImgMode); + + usleep(500 * 1000); + +#if TP2863_BLUE_SCREEN + tp2863_write_register(ViPipe, 0x40, 0x00); + tp2863_write_register(ViPipe, 0x2A, 0x3C); +#endif +} + +void tp2863_exit(VI_PIPE ViPipe) +{ + tp2863_i2c_exit(ViPipe); +} \ No newline at end of file diff --git a/middleware/v2/component/panel/cv180x/bt656_tp2803.h b/middleware/v2/component/panel/cv180x/bt656_tp2803.h new file mode 100644 index 000000000..19d784cc0 --- /dev/null +++ b/middleware/v2/component/panel/cv180x/bt656_tp2803.h @@ -0,0 +1,27 @@ +#ifndef _BT656_TP2803_H_ +#define _BT656_TP2803_H_ + +#include + +const struct VO_BT_PINS tp2803_pins_cfg = { + .pin_num = 9, + .d_pins = { + {VO_VIVO_D0, VO_MUX_BT_DATA0}, + {VO_VIVO_D1, VO_MUX_BT_DATA1}, + {VO_VIVO_D2, VO_MUX_BT_DATA2}, + {VO_VIVO_D3, VO_MUX_BT_DATA3}, + {VO_VIVO_D4, VO_MUX_BT_DATA4}, + {VO_VIVO_D5, VO_MUX_BT_DATA5}, + {VO_VIVO_D6, VO_MUX_BT_DATA6}, + {VO_VIVO_D7, VO_MUX_BT_DATA7}, + {VO_VIVO_CLK, VO_MUX_BT_VS} + } +}; + +const VO_BT_ATTR_S stTP2803Cfg = { + .pins = tp2803_pins_cfg, + .mode = VO_BT_MODE_656, + .bt_clk = VO_BT_CLK_MODE_72M, +}; + +#endif // _I80_PARAM_ST7789V_H_ diff --git a/middleware/v2/component/panel/cv180x/dsi_3aml069lp01g.h b/middleware/v2/component/panel/cv180x/dsi_3aml069lp01g.h index a2f903d2c..24fe2e503 100644 --- a/middleware/v2/component/panel/cv180x/dsi_3aml069lp01g.h +++ b/middleware/v2/component/panel/cv180x/dsi_3aml069lp01g.h @@ -17,7 +17,7 @@ #define PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000) -const struct combo_dev_cfg_s dev_cfg_3AML069LP01G_600x1024 = { +struct combo_dev_cfg_s dev_cfg_3AML069LP01G_600x1024 = { .devno = 0, #ifdef MIPI_PANEL_2_LANES .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, -1, -1}, diff --git a/middleware/v2/component/panel/cv180x/dsi_hx8394_evb.h b/middleware/v2/component/panel/cv180x/dsi_hx8394_evb.h index 48f4ba9fa..c6372e925 100644 --- a/middleware/v2/component/panel/cv180x/dsi_hx8394_evb.h +++ b/middleware/v2/component/panel/cv180x/dsi_hx8394_evb.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_hx8394_720x1280 = { +struct combo_dev_cfg_s dev_cfg_hx8394_720x1280 = { .devno = 0, #ifdef MIPI_PANEL_2_LANES .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, -1, -1}, diff --git a/middleware/v2/component/panel/cv180x/dsi_hx8399_1080p.h b/middleware/v2/component/panel/cv180x/dsi_hx8399_1080p.h index 57b27c22a..ff900ec46 100644 --- a/middleware/v2/component/panel/cv180x/dsi_hx8399_1080p.h +++ b/middleware/v2/component/panel/cv180x/dsi_hx8399_1080p.h @@ -17,7 +17,7 @@ #define PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000) -const struct combo_dev_cfg_s dev_cfg_hx8399_1080x1920 = { +struct combo_dev_cfg_s dev_cfg_hx8399_1080x1920 = { .devno = 0, #ifdef MIPI_PANEL_2_LANES .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, -1, -1}, diff --git a/middleware/v2/component/panel/cv180x/dsi_icn9707.h b/middleware/v2/component/panel/cv180x/dsi_icn9707.h index 5a0e42f4c..d2a0bf459 100644 --- a/middleware/v2/component/panel/cv180x/dsi_icn9707.h +++ b/middleware/v2/component/panel/cv180x/dsi_icn9707.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_icn9707_480x1920 = { +struct combo_dev_cfg_s dev_cfg_icn9707_480x1920 = { .devno = 0, .lane_id = {MIPI_TX_LANE_3, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, MIPI_TX_LANE_0}, .lane_pn_swap = {true, true, true, true, true}, diff --git a/middleware/v2/component/panel/cv180x/dsi_ili9881c.h b/middleware/v2/component/panel/cv180x/dsi_ili9881c.h index 8ff5e47cc..b7cae29db 100644 --- a/middleware/v2/component/panel/cv180x/dsi_ili9881c.h +++ b/middleware/v2/component/panel/cv180x/dsi_ili9881c.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_ili9881c_720x1280 = { +struct combo_dev_cfg_s dev_cfg_ili9881c_720x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, MIPI_TX_LANE_2, MIPI_TX_LANE_3}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv180x/dsi_ili9881d.h b/middleware/v2/component/panel/cv180x/dsi_ili9881d.h index 1b0b68a37..88d488859 100644 --- a/middleware/v2/component/panel/cv180x/dsi_ili9881d.h +++ b/middleware/v2/component/panel/cv180x/dsi_ili9881d.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_ili9881d_720x1280 = { +struct combo_dev_cfg_s dev_cfg_ili9881d_720x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv180x/dsi_jd9366ab.h b/middleware/v2/component/panel/cv180x/dsi_jd9366ab.h index f284f738c..3b4bace71 100644 --- a/middleware/v2/component/panel/cv180x/dsi_jd9366ab.h +++ b/middleware/v2/component/panel/cv180x/dsi_jd9366ab.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_jd9366ab_800x1280 = { +struct combo_dev_cfg_s dev_cfg_jd9366ab_800x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3, MIPI_TX_LANE_2}, .lane_pn_swap = {true, true, true, true, true}, diff --git a/middleware/v2/component/panel/cv180x/dsi_nt35521.h b/middleware/v2/component/panel/cv180x/dsi_nt35521.h index 704e83cae..9607f21ce 100644 --- a/middleware/v2/component/panel/cv180x/dsi_nt35521.h +++ b/middleware/v2/component/panel/cv180x/dsi_nt35521.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_nt35521_800x1280 = { +struct combo_dev_cfg_s dev_cfg_nt35521_800x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_CLK, MIPI_TX_LANE_0, MIPI_TX_LANE_2, MIPI_TX_LANE_3, MIPI_TX_LANE_1}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv180x/dsi_ota7290b.h b/middleware/v2/component/panel/cv180x/dsi_ota7290b.h index 6da973b6a..cf3e324a0 100644 --- a/middleware/v2/component/panel/cv180x/dsi_ota7290b.h +++ b/middleware/v2/component/panel/cv180x/dsi_ota7290b.h @@ -5,7 +5,7 @@ #include // Not support BTA -const struct combo_dev_cfg_s dev_cfg_ota7290b_320x1280 = { +struct combo_dev_cfg_s dev_cfg_ota7290b_320x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, MIPI_TX_LANE_2, MIPI_TX_LANE_3}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv180x/dsi_ota7290b_1920.h b/middleware/v2/component/panel/cv180x/dsi_ota7290b_1920.h index 4483cf2b2..0ff10869b 100644 --- a/middleware/v2/component/panel/cv180x/dsi_ota7290b_1920.h +++ b/middleware/v2/component/panel/cv180x/dsi_ota7290b_1920.h @@ -5,7 +5,7 @@ #include // Not support BTA -const struct combo_dev_cfg_s dev_cfg_ota7290b_440x1920 = { +struct combo_dev_cfg_s dev_cfg_ota7290b_440x1920 = { .devno = 0, .lane_id = {MIPI_TX_LANE_3, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, MIPI_TX_LANE_0}, .lane_pn_swap = {true, true, true, true, true}, diff --git a/middleware/v2/component/panel/cv180x/dsi_st7701.h b/middleware/v2/component/panel/cv180x/dsi_st7701.h index a38a4a341..9cb59ca8c 100644 --- a/middleware/v2/component/panel/cv180x/dsi_st7701.h +++ b/middleware/v2/component/panel/cv180x/dsi_st7701.h @@ -19,7 +19,7 @@ #define PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000) -const struct combo_dev_cfg_s dev_cfg_st7701_480x800 = { +struct combo_dev_cfg_s dev_cfg_st7701_480x800 = { .devno = 0, .lane_id = {MIPI_TX_LANE_1, MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, -1, -1}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv181x/bt656_tp2803.h b/middleware/v2/component/panel/cv181x/bt656_tp2803.h new file mode 100644 index 000000000..19d784cc0 --- /dev/null +++ b/middleware/v2/component/panel/cv181x/bt656_tp2803.h @@ -0,0 +1,27 @@ +#ifndef _BT656_TP2803_H_ +#define _BT656_TP2803_H_ + +#include + +const struct VO_BT_PINS tp2803_pins_cfg = { + .pin_num = 9, + .d_pins = { + {VO_VIVO_D0, VO_MUX_BT_DATA0}, + {VO_VIVO_D1, VO_MUX_BT_DATA1}, + {VO_VIVO_D2, VO_MUX_BT_DATA2}, + {VO_VIVO_D3, VO_MUX_BT_DATA3}, + {VO_VIVO_D4, VO_MUX_BT_DATA4}, + {VO_VIVO_D5, VO_MUX_BT_DATA5}, + {VO_VIVO_D6, VO_MUX_BT_DATA6}, + {VO_VIVO_D7, VO_MUX_BT_DATA7}, + {VO_VIVO_CLK, VO_MUX_BT_VS} + } +}; + +const VO_BT_ATTR_S stTP2803Cfg = { + .pins = tp2803_pins_cfg, + .mode = VO_BT_MODE_656, + .bt_clk = VO_BT_CLK_MODE_72M, +}; + +#endif // _I80_PARAM_ST7789V_H_ diff --git a/middleware/v2/component/panel/cv181x/dsi_3aml069lp01g.h b/middleware/v2/component/panel/cv181x/dsi_3aml069lp01g.h index a2f903d2c..24fe2e503 100644 --- a/middleware/v2/component/panel/cv181x/dsi_3aml069lp01g.h +++ b/middleware/v2/component/panel/cv181x/dsi_3aml069lp01g.h @@ -17,7 +17,7 @@ #define PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000) -const struct combo_dev_cfg_s dev_cfg_3AML069LP01G_600x1024 = { +struct combo_dev_cfg_s dev_cfg_3AML069LP01G_600x1024 = { .devno = 0, #ifdef MIPI_PANEL_2_LANES .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, -1, -1}, diff --git a/middleware/v2/component/panel/cv181x/dsi_hx8394_evb.h b/middleware/v2/component/panel/cv181x/dsi_hx8394_evb.h index 48f4ba9fa..c6372e925 100644 --- a/middleware/v2/component/panel/cv181x/dsi_hx8394_evb.h +++ b/middleware/v2/component/panel/cv181x/dsi_hx8394_evb.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_hx8394_720x1280 = { +struct combo_dev_cfg_s dev_cfg_hx8394_720x1280 = { .devno = 0, #ifdef MIPI_PANEL_2_LANES .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, -1, -1}, diff --git a/middleware/v2/component/panel/cv181x/dsi_hx8399_1080p.h b/middleware/v2/component/panel/cv181x/dsi_hx8399_1080p.h index 57b27c22a..ff900ec46 100644 --- a/middleware/v2/component/panel/cv181x/dsi_hx8399_1080p.h +++ b/middleware/v2/component/panel/cv181x/dsi_hx8399_1080p.h @@ -17,7 +17,7 @@ #define PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000) -const struct combo_dev_cfg_s dev_cfg_hx8399_1080x1920 = { +struct combo_dev_cfg_s dev_cfg_hx8399_1080x1920 = { .devno = 0, #ifdef MIPI_PANEL_2_LANES .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, -1, -1}, diff --git a/middleware/v2/component/panel/cv181x/dsi_icn9707.h b/middleware/v2/component/panel/cv181x/dsi_icn9707.h index 5a0e42f4c..d2a0bf459 100644 --- a/middleware/v2/component/panel/cv181x/dsi_icn9707.h +++ b/middleware/v2/component/panel/cv181x/dsi_icn9707.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_icn9707_480x1920 = { +struct combo_dev_cfg_s dev_cfg_icn9707_480x1920 = { .devno = 0, .lane_id = {MIPI_TX_LANE_3, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, MIPI_TX_LANE_0}, .lane_pn_swap = {true, true, true, true, true}, diff --git a/middleware/v2/component/panel/cv181x/dsi_ili9881c.h b/middleware/v2/component/panel/cv181x/dsi_ili9881c.h index 8ff5e47cc..b7cae29db 100644 --- a/middleware/v2/component/panel/cv181x/dsi_ili9881c.h +++ b/middleware/v2/component/panel/cv181x/dsi_ili9881c.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_ili9881c_720x1280 = { +struct combo_dev_cfg_s dev_cfg_ili9881c_720x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, MIPI_TX_LANE_2, MIPI_TX_LANE_3}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv181x/dsi_ili9881d.h b/middleware/v2/component/panel/cv181x/dsi_ili9881d.h index 1b0b68a37..88d488859 100644 --- a/middleware/v2/component/panel/cv181x/dsi_ili9881d.h +++ b/middleware/v2/component/panel/cv181x/dsi_ili9881d.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_ili9881d_720x1280 = { +struct combo_dev_cfg_s dev_cfg_ili9881d_720x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv181x/dsi_jd9366ab.h b/middleware/v2/component/panel/cv181x/dsi_jd9366ab.h index f284f738c..3b4bace71 100644 --- a/middleware/v2/component/panel/cv181x/dsi_jd9366ab.h +++ b/middleware/v2/component/panel/cv181x/dsi_jd9366ab.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_jd9366ab_800x1280 = { +struct combo_dev_cfg_s dev_cfg_jd9366ab_800x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, MIPI_TX_LANE_3, MIPI_TX_LANE_2}, .lane_pn_swap = {true, true, true, true, true}, diff --git a/middleware/v2/component/panel/cv181x/dsi_nt35521.h b/middleware/v2/component/panel/cv181x/dsi_nt35521.h index 704e83cae..9607f21ce 100644 --- a/middleware/v2/component/panel/cv181x/dsi_nt35521.h +++ b/middleware/v2/component/panel/cv181x/dsi_nt35521.h @@ -4,7 +4,7 @@ #include #include -const struct combo_dev_cfg_s dev_cfg_nt35521_800x1280 = { +struct combo_dev_cfg_s dev_cfg_nt35521_800x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_CLK, MIPI_TX_LANE_0, MIPI_TX_LANE_2, MIPI_TX_LANE_3, MIPI_TX_LANE_1}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv181x/dsi_ota7290b.h b/middleware/v2/component/panel/cv181x/dsi_ota7290b.h index 6da973b6a..cf3e324a0 100644 --- a/middleware/v2/component/panel/cv181x/dsi_ota7290b.h +++ b/middleware/v2/component/panel/cv181x/dsi_ota7290b.h @@ -5,7 +5,7 @@ #include // Not support BTA -const struct combo_dev_cfg_s dev_cfg_ota7290b_320x1280 = { +struct combo_dev_cfg_s dev_cfg_ota7290b_320x1280 = { .devno = 0, .lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_1, MIPI_TX_LANE_CLK, MIPI_TX_LANE_2, MIPI_TX_LANE_3}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/component/panel/cv181x/dsi_ota7290b_1920.h b/middleware/v2/component/panel/cv181x/dsi_ota7290b_1920.h index 4483cf2b2..0ff10869b 100644 --- a/middleware/v2/component/panel/cv181x/dsi_ota7290b_1920.h +++ b/middleware/v2/component/panel/cv181x/dsi_ota7290b_1920.h @@ -5,7 +5,7 @@ #include // Not support BTA -const struct combo_dev_cfg_s dev_cfg_ota7290b_440x1920 = { +struct combo_dev_cfg_s dev_cfg_ota7290b_440x1920 = { .devno = 0, .lane_id = {MIPI_TX_LANE_3, MIPI_TX_LANE_2, MIPI_TX_LANE_CLK, MIPI_TX_LANE_1, MIPI_TX_LANE_0}, .lane_pn_swap = {true, true, true, true, true}, diff --git a/middleware/v2/component/panel/cv181x/dsi_st7701.h b/middleware/v2/component/panel/cv181x/dsi_st7701.h index a38a4a341..9cb59ca8c 100644 --- a/middleware/v2/component/panel/cv181x/dsi_st7701.h +++ b/middleware/v2/component/panel/cv181x/dsi_st7701.h @@ -19,7 +19,7 @@ #define PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \ * (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000) -const struct combo_dev_cfg_s dev_cfg_st7701_480x800 = { +struct combo_dev_cfg_s dev_cfg_st7701_480x800 = { .devno = 0, .lane_id = {MIPI_TX_LANE_1, MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, -1, -1}, .lane_pn_swap = {false, false, false, false, false}, diff --git a/middleware/v2/cv180x/ko/cv180x_vcodec.ko b/middleware/v2/cv180x/ko/cv180x_vcodec.ko index 92db6e655..91487cdab 100644 Binary files a/middleware/v2/cv180x/ko/cv180x_vcodec.ko and b/middleware/v2/cv180x/ko/cv180x_vcodec.ko differ diff --git a/middleware/v2/cv180x/ko/cv180x_vi.ko b/middleware/v2/cv180x/ko/cv180x_vi.ko index 015354a73..af4d64c7e 100644 Binary files a/middleware/v2/cv180x/ko/cv180x_vi.ko and b/middleware/v2/cv180x/ko/cv180x_vi.ko differ diff --git a/middleware/v2/cv180x/ko/cvi_vc_driver.ko b/middleware/v2/cv180x/ko/cvi_vc_driver.ko index 6e98234fb..4732a1de4 100644 Binary files a/middleware/v2/cv180x/ko/cvi_vc_driver.ko and b/middleware/v2/cv180x/ko/cvi_vc_driver.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/3rd/cvi_wiegand_gpio.ko b/middleware/v2/cv180x/ko_shrink/3rd/cvi_wiegand_gpio.ko new file mode 100644 index 000000000..aace33c51 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/3rd/cvi_wiegand_gpio.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_base.ko b/middleware/v2/cv180x/ko_shrink/cv180x_base.ko new file mode 100644 index 000000000..84aeb675f Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_base.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_clock_cooling.ko b/middleware/v2/cv180x/ko_shrink/cv180x_clock_cooling.ko new file mode 100644 index 000000000..768264829 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_clock_cooling.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_dwa.ko b/middleware/v2/cv180x/ko_shrink/cv180x_dwa.ko new file mode 100644 index 000000000..9e2a69138 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_dwa.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_fast_image.ko b/middleware/v2/cv180x/ko_shrink/cv180x_fast_image.ko new file mode 100644 index 000000000..3ec7d3971 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_fast_image.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_jpeg.ko b/middleware/v2/cv180x/ko_shrink/cv180x_jpeg.ko new file mode 100644 index 000000000..d37d4507d Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_jpeg.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_mon.ko b/middleware/v2/cv180x/ko_shrink/cv180x_mon.ko new file mode 100644 index 000000000..265f54133 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_mon.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_pwm.ko b/middleware/v2/cv180x/ko_shrink/cv180x_pwm.ko new file mode 100644 index 000000000..06639bf68 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_pwm.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_rgn.ko b/middleware/v2/cv180x/ko_shrink/cv180x_rgn.ko new file mode 100644 index 000000000..dc42b2954 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_rgn.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_rtc.ko b/middleware/v2/cv180x/ko_shrink/cv180x_rtc.ko new file mode 100644 index 000000000..97f43f415 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_rtc.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_rtos_cmdqu.ko b/middleware/v2/cv180x/ko_shrink/cv180x_rtos_cmdqu.ko new file mode 100644 index 000000000..0d7d97b9b Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_rtos_cmdqu.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_saradc.ko b/middleware/v2/cv180x/ko_shrink/cv180x_saradc.ko new file mode 100644 index 000000000..821be2bc8 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_saradc.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_sys.ko b/middleware/v2/cv180x/ko_shrink/cv180x_sys.ko new file mode 100644 index 000000000..4d90aa164 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_sys.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_tpu.ko b/middleware/v2/cv180x/ko_shrink/cv180x_tpu.ko new file mode 100644 index 000000000..6bc886731 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_tpu.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_vcodec.ko b/middleware/v2/cv180x/ko_shrink/cv180x_vcodec.ko new file mode 100644 index 000000000..678e0ac0f Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_vcodec.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_vi.ko b/middleware/v2/cv180x/ko_shrink/cv180x_vi.ko new file mode 100644 index 000000000..94edc54d0 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_vi.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_vpss.ko b/middleware/v2/cv180x/ko_shrink/cv180x_vpss.ko new file mode 100644 index 000000000..6e04f6db6 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_vpss.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cv180x_wdt.ko b/middleware/v2/cv180x/ko_shrink/cv180x_wdt.ko new file mode 100644 index 000000000..50fb8b5c7 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cv180x_wdt.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cvi_mipi_rx.ko b/middleware/v2/cv180x/ko_shrink/cvi_mipi_rx.ko new file mode 100644 index 000000000..b218c2b96 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cvi_mipi_rx.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cvi_vc_driver.ko b/middleware/v2/cv180x/ko_shrink/cvi_vc_driver.ko new file mode 100644 index 000000000..b1451a2a8 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cvi_vc_driver.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cvi_wiegand.ko b/middleware/v2/cv180x/ko_shrink/cvi_wiegand.ko new file mode 100644 index 000000000..f3467e821 Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cvi_wiegand.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/cviaudio_core.ko b/middleware/v2/cv180x/ko_shrink/cviaudio_core.ko new file mode 100644 index 000000000..f1a8bf8cc Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/cviaudio_core.ko differ diff --git a/middleware/v2/cv180x/ko_shrink/snsr_i2c.ko b/middleware/v2/cv180x/ko_shrink/snsr_i2c.ko new file mode 100644 index 000000000..c75da9cbe Binary files /dev/null and b/middleware/v2/cv180x/ko_shrink/snsr_i2c.ko differ diff --git a/middleware/v2/cv180x/lib_glibc_riscv64/libae.a b/middleware/v2/cv180x/lib_glibc_riscv64/libae.a index 82f3db279..1b2efa07c 100644 Binary files a/middleware/v2/cv180x/lib_glibc_riscv64/libae.a and b/middleware/v2/cv180x/lib_glibc_riscv64/libae.a differ diff --git a/middleware/v2/cv180x/lib_glibc_riscv64/libae.so b/middleware/v2/cv180x/lib_glibc_riscv64/libae.so index 765e4eb03..9378ce49f 100755 Binary files a/middleware/v2/cv180x/lib_glibc_riscv64/libae.so and b/middleware/v2/cv180x/lib_glibc_riscv64/libae.so differ diff --git a/middleware/v2/cv180x/lib_musl_riscv64/libae.a b/middleware/v2/cv180x/lib_musl_riscv64/libae.a index f63e07505..130c25b59 100644 Binary files a/middleware/v2/cv180x/lib_musl_riscv64/libae.a and b/middleware/v2/cv180x/lib_musl_riscv64/libae.a differ diff --git a/middleware/v2/cv180x/lib_musl_riscv64/libae.so b/middleware/v2/cv180x/lib_musl_riscv64/libae.so index d0b371397..e75bceb9e 100755 Binary files a/middleware/v2/cv180x/lib_musl_riscv64/libae.so and b/middleware/v2/cv180x/lib_musl_riscv64/libae.so differ diff --git a/middleware/v2/cv181x/ko/cv181x_mipi_tx.ko b/middleware/v2/cv181x/ko/cv181x_mipi_tx.ko index 1b3d48faa..1574e8517 100644 Binary files a/middleware/v2/cv181x/ko/cv181x_mipi_tx.ko and b/middleware/v2/cv181x/ko/cv181x_mipi_tx.ko differ diff --git a/middleware/v2/cv181x/ko/cv181x_vcodec.ko b/middleware/v2/cv181x/ko/cv181x_vcodec.ko index f0e63f2a0..241605d51 100644 Binary files a/middleware/v2/cv181x/ko/cv181x_vcodec.ko and b/middleware/v2/cv181x/ko/cv181x_vcodec.ko differ diff --git a/middleware/v2/cv181x/ko/cv181x_vi.ko b/middleware/v2/cv181x/ko/cv181x_vi.ko index 35edb28fc..315f3ebcf 100644 Binary files a/middleware/v2/cv181x/ko/cv181x_vi.ko and b/middleware/v2/cv181x/ko/cv181x_vi.ko differ diff --git a/middleware/v2/cv181x/ko/cv181x_vo.ko b/middleware/v2/cv181x/ko/cv181x_vo.ko index 389bc3987..e8a1b202e 100644 Binary files a/middleware/v2/cv181x/ko/cv181x_vo.ko and b/middleware/v2/cv181x/ko/cv181x_vo.ko differ diff --git a/middleware/v2/cv181x/ko/cvi_vc_driver.ko b/middleware/v2/cv181x/ko/cvi_vc_driver.ko index 0fb5c2ed9..994103774 100644 Binary files a/middleware/v2/cv181x/ko/cvi_vc_driver.ko and b/middleware/v2/cv181x/ko/cvi_vc_driver.ko differ diff --git a/middleware/v2/cv181x/lib_glibc_riscv64/libae.a b/middleware/v2/cv181x/lib_glibc_riscv64/libae.a index 071a786ec..17512b6fb 100644 Binary files a/middleware/v2/cv181x/lib_glibc_riscv64/libae.a and b/middleware/v2/cv181x/lib_glibc_riscv64/libae.a differ diff --git a/middleware/v2/cv181x/lib_glibc_riscv64/libae.so b/middleware/v2/cv181x/lib_glibc_riscv64/libae.so index 4c397f64c..15ba14c7a 100755 Binary files a/middleware/v2/cv181x/lib_glibc_riscv64/libae.so and b/middleware/v2/cv181x/lib_glibc_riscv64/libae.so differ diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libae.a b/middleware/v2/cv181x/lib_musl_riscv64/libae.a index b734413a4..1e073f695 100644 Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libae.a and b/middleware/v2/cv181x/lib_musl_riscv64/libae.a differ diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libae.so b/middleware/v2/cv181x/lib_musl_riscv64/libae.so index 260c70a26..bc40cf90a 100755 Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libae.so and b/middleware/v2/cv181x/lib_musl_riscv64/libae.so differ diff --git a/middleware/v2/include/cvi_sns_ctrl.h b/middleware/v2/include/cvi_sns_ctrl.h index 4dee97800..70c9d2d38 100644 --- a/middleware/v2/include/cvi_sns_ctrl.h +++ b/middleware/v2/include/cvi_sns_ctrl.h @@ -117,6 +117,7 @@ typedef struct _ISP_SNS_OBJ_S { extern ISP_SNS_OBJ_S stSnsBG0808_Obj; extern ISP_SNS_OBJ_S stSnsGc02m1b_Obj; +extern ISP_SNS_OBJ_S stSnsGc0329_Obj; extern ISP_SNS_OBJ_S stSnsGc1054_Obj; extern ISP_SNS_OBJ_S stSnsGc2053_Obj; extern ISP_SNS_OBJ_S stSnsGc2053_Slave_Obj; @@ -127,6 +128,7 @@ extern ISP_SNS_OBJ_S stSnsGc2145_Obj; extern ISP_SNS_OBJ_S stSnsGc4023_Obj; extern ISP_SNS_OBJ_S stSnsGc4653_Obj; extern ISP_SNS_OBJ_S stSnsGc4653_Slave_Obj; +extern ISP_SNS_OBJ_S stSnsMIS2008_Obj; extern ISP_SNS_OBJ_S stSnsN5_Obj; extern ISP_SNS_OBJ_S stSnsN6_Obj; extern ISP_SNS_OBJ_S stSnsOs02d10_Obj; @@ -189,6 +191,7 @@ extern ISP_SNS_OBJ_S stSnsImx347_Obj; extern ISP_SNS_OBJ_S stSnsImx385_Obj; extern ISP_SNS_OBJ_S stSnsTP2850_Obj; extern ISP_SNS_OBJ_S stSnsTP2825_Obj; +extern ISP_SNS_OBJ_S stSnsTP2863_Obj; extern ISP_SNS_OBJ_S stSnsMCS369_Obj; extern ISP_SNS_OBJ_S stSnsMCS369Q_Obj; extern ISP_SNS_OBJ_S stSnsMM308M2_Obj; diff --git a/middleware/v2/include/isp/cv181x/cvi_comm_isp.h b/middleware/v2/include/isp/cv181x/cvi_comm_isp.h index fdb026fa2..4bb998e96 100644 --- a/middleware/v2/include/isp/cv181x/cvi_comm_isp.h +++ b/middleware/v2/include/isp/cv181x/cvi_comm_isp.h @@ -2086,9 +2086,9 @@ typedef struct _ISP_PRESHARPEN_MANUAL_ATTR_S { CVI_U8 LumaAdpGain[SHARPEN_LUT_NUM]; /*RW; Range:[0x0, 0x3f]*/ CVI_U8 DeltaAdpGain[SHARPEN_LUT_NUM]; /*RW; Range:[0x0, 0x3f]*/ CVI_U8 LumaCorLutIn[EE_LUT_NODE]; /*RW; Range:[0x0, 0xff]*/ - CVI_U8 LumaCorLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x20]*/ + CVI_U8 LumaCorLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x1f]*/ CVI_U8 MotionCorLutIn[EE_LUT_NODE]; /*RW; Range:[0x0, 0xff]*/ - CVI_U8 MotionCorLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x20]*/ + CVI_U8 MotionCorLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x1f]*/ CVI_U8 MotionCorWgtLutIn[EE_LUT_NODE]; /*RW; Range:[0x0, 0xff]*/ CVI_U8 MotionCorWgtLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x80]*/ CVI_U8 GlobalGain; /*RW; Range:[0x0, 0xff]*/ @@ -2111,9 +2111,9 @@ typedef struct _ISP_PRESHARPEN_AUTO_ATTR_S { CVI_U8 LumaAdpGain[SHARPEN_LUT_NUM][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x3f]*/ CVI_U8 DeltaAdpGain[SHARPEN_LUT_NUM][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x3f]*/ CVI_U8 LumaCorLutIn[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0xff]*/ - CVI_U8 LumaCorLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x20]*/ + CVI_U8 LumaCorLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x1f]*/ CVI_U8 MotionCorLutIn[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0xff]*/ - CVI_U8 MotionCorLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x20]*/ + CVI_U8 MotionCorLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x1f]*/ CVI_U8 MotionCorWgtLutIn[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0xff]*/ CVI_U8 MotionCorWgtLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x80]*/ CVI_U8 GlobalGain[ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0xff]*/ @@ -2509,9 +2509,9 @@ typedef struct _ISP_SHARPEN_MANUAL_ATTR_S { CVI_U8 LumaAdpGain[SHARPEN_LUT_NUM]; /*RW; Range:[0x0, 0x3f]*/ CVI_U8 DeltaAdpGain[SHARPEN_LUT_NUM]; /*RW; Range:[0x0, 0x3f]*/ CVI_U8 LumaCorLutIn[EE_LUT_NODE]; /*RW; Range:[0x0, 0xff]*/ - CVI_U8 LumaCorLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x20]*/ + CVI_U8 LumaCorLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x1f]*/ CVI_U8 MotionCorLutIn[EE_LUT_NODE]; /*RW; Range:[0x0, 0xff]*/ - CVI_U8 MotionCorLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x20]*/ + CVI_U8 MotionCorLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x1f]*/ CVI_U8 MotionCorWgtLutIn[EE_LUT_NODE]; /*RW; Range:[0x0, 0xff]*/ CVI_U8 MotionCorWgtLutOut[EE_LUT_NODE]; /*RW; Range:[0x0, 0x80]*/ CVI_U8 GlobalGain; /*RW; Range:[0x0, 0xff]*/ @@ -2534,9 +2534,9 @@ typedef struct _ISP_SHARPEN_AUTO_ATTR_S { CVI_U8 LumaAdpGain[SHARPEN_LUT_NUM][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x3f]*/ CVI_U8 DeltaAdpGain[SHARPEN_LUT_NUM][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x3f]*/ CVI_U8 LumaCorLutIn[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0xff]*/ - CVI_U8 LumaCorLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x20]*/ + CVI_U8 LumaCorLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x1f]*/ CVI_U8 MotionCorLutIn[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0xff]*/ - CVI_U8 MotionCorLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x20]*/ + CVI_U8 MotionCorLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x1f]*/ CVI_U8 MotionCorWgtLutIn[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0xff]*/ CVI_U8 MotionCorWgtLutOut[EE_LUT_NODE][ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0x80]*/ CVI_U8 GlobalGain[ISP_AUTO_ISO_STRENGTH_NUM]; /*RW; Range:[0x0, 0xff]*/ diff --git a/middleware/v2/include/linux/cvi_comm_venc.h b/middleware/v2/include/linux/cvi_comm_venc.h index 2f425728e..f40eef8f8 100644 --- a/middleware/v2/include/linux/cvi_comm_venc.h +++ b/middleware/v2/include/linux/cvi_comm_venc.h @@ -47,6 +47,8 @@ enum VENC_BIND_MODE_E { #define CVI_VENC_MASK_TRACE 0x10000 #define CVI_VENC_MASK_DUMP_YUV 0x100000 #define CVI_VENC_MASK_DUMP_BS 0x200000 +#define CVI_VENC_MASK_DEBUG 0x400000 + #define CVI_VENC_MASK_CURR (CVI_VENC_MASK_ERR) typedef struct _venc_dbg_ { @@ -197,12 +199,13 @@ extern pthread_t gs_VencTask[VENC_MAX_CHN_NUM]; #define CVI_VENC_DEBUG(msg, ...) \ do { \ - struct timespec64 ts; \ - ktime_get_ts64(&ts); \ - pr_info("[DEBUG][%llu] %s = %d," msg, ts.tv_sec * 1000 + ts.tv_nsec / 1000000, __func__, \ - __LINE__, ## __VA_ARGS__); \ + if (vencDbg.currMask & CVI_VENC_MASK_DEBUG) { \ + struct timespec64 ts; \ + ktime_get_ts64(&ts); \ + pr_info("[DEBUG][%llu] %s = %d," msg, ts.tv_sec * 1000 + ts.tv_nsec / 1000000, __func__, \ + __LINE__, ## __VA_ARGS__); \ + } \ } while (0) - #define CVI_VENC_ERR(msg, ...) \ do { \ if (vencDbg.currMask & CVI_VENC_MASK_ERR) \ diff --git a/middleware/v2/include/linux/cvi_comm_vo.h b/middleware/v2/include/linux/cvi_comm_vo.h index 6fae63dc3..a3813af6f 100644 --- a/middleware/v2/include/linux/cvi_comm_vo.h +++ b/middleware/v2/include/linux/cvi_comm_vo.h @@ -36,6 +36,9 @@ extern "C" { #define VO_INTF_I80 (0x01L << 16) #define VO_GAMMA_NODENUM 65 + +#define MAX_BT_PINS 20 + typedef CVI_U32 VO_INTF_TYPE_E; typedef enum _VO_INTF_SYNC_E { @@ -288,6 +291,137 @@ typedef struct _VO_LVDS_ATTR_S { enum VO_LVDS_MODE_E lvds_vesa_mode; } VO_LVDS_ATTR_S; +enum VO_TOP_MUX { + VO_MUX_BT_VS = 0, + VO_MUX_BT_HS, + VO_MUX_BT_HDE, + VO_MUX_BT_DATA0, + VO_MUX_BT_DATA1, + VO_MUX_BT_DATA2, + VO_MUX_BT_DATA3, + VO_MUX_BT_DATA4, + VO_MUX_BT_DATA5, + VO_MUX_BT_DATA6, + VO_MUX_BT_DATA7, + VO_MUX_BT_DATA8, + VO_MUX_BT_DATA9, + VO_MUX_BT_DATA10, + VO_MUX_BT_DATA11, + VO_MUX_BT_DATA12, + VO_MUX_BT_DATA13, + VO_MUX_BT_DATA14, + VO_MUX_BT_DATA15, + VO_MUX_TG_HS_TILE = 30, + VO_MUX_TG_VS_TILE, + VO_MUX_MAX, +}; + +enum VO_TOP_SEL { + VO_CLK0 = 0, + VO_CLK1, + VO_D0, + VO_D1, + VO_D2, + VO_D3, + VO_D4, + VO_D5, + VO_D6, + VO_D7, + VO_D8, + VO_D9, + VO_D10, + VO_D11, + VO_D12, + VO_D13, + VO_D14, + VO_D15, + VO_D16, + VO_D17, + VO_D18, + VO_D19, + VO_D20, + VO_D21, + VO_D22, + VO_D23, + VO_D24, + VO_D25, + VO_D26, + VO_D27, + VO_D_MAX, +}; + +enum VO_TOP_D_SEL { + VO_VIVO_D0 = VO_D13, + VO_VIVO_D1 = VO_D14, + VO_VIVO_D2 = VO_D15, + VO_VIVO_D3 = VO_D16, + VO_VIVO_D4 = VO_D17, + VO_VIVO_D5 = VO_D18, + VO_VIVO_D6 = VO_D19, + VO_VIVO_D7 = VO_D20, + VO_VIVO_D8 = VO_D21, + VO_VIVO_D9 = VO_D22, + VO_VIVO_D10 = VO_D23, + VO_VIVO_CLK = VO_CLK1, + VO_MIPI_TXM4 = VO_D24, + VO_MIPI_TXP4 = VO_D25, + VO_MIPI_TXM3 = VO_D26, + VO_MIPI_TXP3 = VO_D27, + VO_MIPI_TXM2 = VO_D0, + VO_MIPI_TXP2 = VO_CLK0, + VO_MIPI_TXM1 = VO_D2, + VO_MIPI_TXP1 = VO_D1, + VO_MIPI_TXM0 = VO_D4, + VO_MIPI_TXP0 = VO_D3, + VO_MIPI_RXN5 = VO_D12, + VO_MIPI_RXP5 = VO_D11, + VO_MIPI_RXN2 = VO_D10, + VO_MIPI_RXP2 = VO_D9, + VO_MIPI_RXN1 = VO_D8, + VO_MIPI_RXP1 = VO_D7, + VO_MIPI_RXN0 = VO_D6, + VO_MIPI_RXP0 = VO_D5, + VO_PAD_MAX = VO_D_MAX +}; + +struct VO_D_REMAP { + enum VO_TOP_D_SEL sel; + enum VO_TOP_MUX mux; +}; + +struct VO_BT_PINS { + unsigned char pin_num; + struct VO_D_REMAP d_pins[MAX_BT_PINS]; +}; + +enum VO_BT_MODE { + VO_BT_MODE_656 = 0, + VO_BT_MODE_1120, + VO_BT_MODE_601, + VO_BT_MODE_MAX, +}; + +enum VO_BT_CLK_MODE { + VO_BT_CLK_MODE_27M = 0, + VO_BT_CLK_MODE_36M, + VO_BT_CLK_MODE_37P125M, + VO_BT_CLK_MODE_72M, + VO_BT_CLK_MODE_74P25M, + VO_BT_CLK_MODE_148P5M, +}; + +/* Define BT's config + * + * bt_clk: bt clk sel + * mode: bt mode + * pins: bt pinmux cfg + */ +typedef struct _VO_BT_ATTR_S { + enum VO_BT_CLK_MODE bt_clk; + enum VO_BT_MODE mode; + struct VO_BT_PINS pins; +} VO_BT_ATTR_S; + /* * u32BgColor: Background color of a device, in RGB format. * enIntfType: Type of a VO interface. @@ -304,6 +438,7 @@ typedef struct _VO_PUB_ATTR_S { union { VO_I80_CFG_S sti80Cfg; VO_LVDS_ATTR_S stLvdsAttr; + VO_BT_ATTR_S stBtAttr; }; } VO_PUB_ATTR_S; diff --git a/middleware/v2/include/linux/vo_disp.h b/middleware/v2/include/linux/vo_disp.h index c46eb709f..59290a228 100644 --- a/middleware/v2/include/linux/vo_disp.h +++ b/middleware/v2/include/linux/vo_disp.h @@ -5,6 +5,8 @@ #define LANE_MAX_NUM 5 #endif +#define MAX_BT_PINS 20 + enum cvi_disp_intf { CVI_VIP_DISP_INTF_DSI = 0, CVI_VIP_DISP_INTF_BT, @@ -54,6 +56,109 @@ struct cvi_lvds_intf_cfg { __s8 backlight_avtive; }; +enum sclr_top_vo_mux { + SCLR_VO_MUX_BT_VS = 0, + SCLR_VO_MUX_BT_HS, + SCLR_VO_MUX_BT_HDE, + SCLR_VO_MUX_BT_DATA0, + SCLR_VO_MUX_BT_DATA1, + SCLR_VO_MUX_BT_DATA2, + SCLR_VO_MUX_BT_DATA3, + SCLR_VO_MUX_BT_DATA4, + SCLR_VO_MUX_BT_DATA5, + SCLR_VO_MUX_BT_DATA6, + SCLR_VO_MUX_BT_DATA7, + SCLR_VO_MUX_BT_DATA8, + SCLR_VO_MUX_BT_DATA9, + SCLR_VO_MUX_BT_DATA10, + SCLR_VO_MUX_BT_DATA11, + SCLR_VO_MUX_BT_DATA12, + SCLR_VO_MUX_BT_DATA13, + SCLR_VO_MUX_BT_DATA14, + SCLR_VO_MUX_BT_DATA15, + SCLR_VO_MUX_TG_HS_TILE = 30, + SCLR_VO_MUX_TG_VS_TILE, + SCLR_VO_MUX_MAX, +}; + +enum sclr_top_vo_sel { + SCLR_VO_CLK0 = 0, + SCLR_VO_CLK1, + SCLR_VO_D0, + SCLR_VO_D1, + SCLR_VO_D2, + SCLR_VO_D3, + SCLR_VO_D4, + SCLR_VO_D5, + SCLR_VO_D6, + SCLR_VO_D7, + SCLR_VO_D8, + SCLR_VO_D9, + SCLR_VO_D10, + SCLR_VO_D11, + SCLR_VO_D12, + SCLR_VO_D13, + SCLR_VO_D14, + SCLR_VO_D15, + SCLR_VO_D16, + SCLR_VO_D17, + SCLR_VO_D18, + SCLR_VO_D19, + SCLR_VO_D20, + SCLR_VO_D21, + SCLR_VO_D22, + SCLR_VO_D23, + SCLR_VO_D24, + SCLR_VO_D25, + SCLR_VO_D26, + SCLR_VO_D27, + SCLR_VO_D_MAX, +}; + +enum sclr_top_vo_d_sel { + SCLR_VO_VIVO_D0 = SCLR_VO_D13, + SCLR_VO_VIVO_D1 = SCLR_VO_D14, + SCLR_VO_VIVO_D2 = SCLR_VO_D15, + SCLR_VO_VIVO_D3 = SCLR_VO_D16, + SCLR_VO_VIVO_D4 = SCLR_VO_D17, + SCLR_VO_VIVO_D5 = SCLR_VO_D18, + SCLR_VO_VIVO_D6 = SCLR_VO_D19, + SCLR_VO_VIVO_D7 = SCLR_VO_D20, + SCLR_VO_VIVO_D8 = SCLR_VO_D21, + SCLR_VO_VIVO_D9 = SCLR_VO_D22, + SCLR_VO_VIVO_D10 = SCLR_VO_D23, + SCLR_VO_VIVO_CLK = SCLR_VO_CLK1, + SCLR_VO_MIPI_TXM4 = SCLR_VO_D24, + SCLR_VO_MIPI_TXP4 = SCLR_VO_D25, + SCLR_VO_MIPI_TXM3 = SCLR_VO_D26, + SCLR_VO_MIPI_TXP3 = SCLR_VO_D27, + SCLR_VO_MIPI_TXM2 = SCLR_VO_D0, + SCLR_VO_MIPI_TXP2 = SCLR_VO_CLK0, + SCLR_VO_MIPI_TXM1 = SCLR_VO_D2, + SCLR_VO_MIPI_TXP1 = SCLR_VO_D1, + SCLR_VO_MIPI_TXM0 = SCLR_VO_D4, + SCLR_VO_MIPI_TXP0 = SCLR_VO_D3, + SCLR_VO_MIPI_RXN5 = SCLR_VO_D12, + SCLR_VO_MIPI_RXP5 = SCLR_VO_D11, + SCLR_VO_MIPI_RXN2 = SCLR_VO_D10, + SCLR_VO_MIPI_RXP2 = SCLR_VO_D9, + SCLR_VO_MIPI_RXN1 = SCLR_VO_D8, + SCLR_VO_MIPI_RXP1 = SCLR_VO_D7, + SCLR_VO_MIPI_RXN0 = SCLR_VO_D6, + SCLR_VO_MIPI_RXP0 = SCLR_VO_D5, + SCLR_VO_PAD_MAX = SCLR_VO_D_MAX +}; + +struct vo_d_remap { + enum sclr_top_vo_d_sel sel; + enum sclr_top_vo_mux mux; +}; + +struct bt_pins { + unsigned char pin_num; + struct vo_d_remap d_pins[MAX_BT_PINS]; +}; + enum BT_MODE { BT_MODE_656 = 0, BT_MODE_1120, @@ -61,12 +166,22 @@ enum BT_MODE { BT_MODE_MAX, }; +enum BT_CLK_MODE { + BT_CLK_MODE_27M = 0, + BT_CLK_MODE_36M, + BT_CLK_MODE_37P125M, + BT_CLK_MODE_72M, + BT_CLK_MODE_74P25M, + BT_CLK_MODE_148P5M, +}; + /* * @pixelclock: pixel clock in kHz */ struct cvi_bt_intf_cfg { - __u32 pixelclock; + __u8 bt_clk; enum BT_MODE mode; + struct bt_pins pins; }; struct cvi_disp_intf_cfg { diff --git a/middleware/v2/sample/common/Kbuild b/middleware/v2/sample/common/Kbuild index fef71822e..6932edd73 100644 --- a/middleware/v2/sample/common/Kbuild +++ b/middleware/v2/sample/common/Kbuild @@ -9,6 +9,10 @@ ifeq ($(CONFIG_SENSOR_GCORE_GC02M1), y) KBUILD_DEFINES += -DSENSOR_GCORE_GC02M1 endif +ifeq ($(CONFIG_SENSOR_GCORE_GC0329), y) + KBUILD_DEFINES += -DSENSOR_GCORE_GC0329 +endif + ifeq ($(CONFIG_SENSOR_GCORE_GC1054), y) KBUILD_DEFINES += -DSENSOR_GCORE_GC1054 endif @@ -49,6 +53,10 @@ ifeq ($(CONFIG_SENSOR_GCORE_GC4653_SLAVE), y) KBUILD_DEFINES += -DSENSOR_GCORE_GC4653_SLAVE endif +ifeq ($(CONFIG_SENSOR_IMGDS_MIS2008), y) + KBUILD_DEFINES += -DSENSOR_ID_MIS2008 +endif + ifeq ($(CONFIG_SENSOR_NEXTCHIP_N5), y) KBUILD_DEFINES += -DSENSOR_NEXTCHIP_N5 endif @@ -301,6 +309,10 @@ ifeq ($(CONFIG_SENSOR_TECHPOINT_TP2825), y) KBUILD_DEFINES += -DSENSOR_TECHPOINT_TP2825 endif +ifeq ($(CONFIG_SENSOR_TECHPOINT_TP2863), y) + KBUILD_DEFINES += -DSENSOR_TECHPOINT_TP2863 +endif + ifeq ($(CONFIG_SENSOR_VIVO_MCS369Q), y) KBUILD_DEFINES += -DSENSOR_VIVO_MCS369Q endif diff --git a/middleware/v2/sample/common/sample_comm.h b/middleware/v2/sample/common/sample_comm.h index d64c9cfb8..213bef639 100644 --- a/middleware/v2/sample/common/sample_comm.h +++ b/middleware/v2/sample/common/sample_comm.h @@ -179,6 +179,7 @@ typedef enum _SAMPLE_SNS_TYPE_E { /* ------ LINEAR BEGIN ------*/ BRIGATES_BG0808_MIPI_2M_30FPS_10BIT, GCORE_GC02M1_MIPI_2M_30FPS_10BIT, + GCORE_GC0329_MIPI_480P_10FPS_8BIT, GCORE_GC1054_MIPI_1M_30FPS_10BIT, GCORE_GC2053_MIPI_2M_30FPS_10BIT, GCORE_GC2053_SLAVE_MIPI_2M_30FPS_10BIT, @@ -189,6 +190,7 @@ typedef enum _SAMPLE_SNS_TYPE_E { GCORE_GC4023_MIPI_4M_30FPS_10BIT, GCORE_GC4653_MIPI_4M_30FPS_10BIT, GCORE_GC4653_SLAVE_MIPI_4M_30FPS_10BIT, + IMGDS_MIS2008_MIPI_2M_1080P_30FPS_12BIT, NEXTCHIP_N5_1M_2CH_25FPS_8BIT, NEXTCHIP_N5_2M_25FPS_8BIT, NEXTCHIP_N6_2M_4CH_25FPS_8BIT, @@ -279,6 +281,10 @@ typedef enum _SAMPLE_SNS_TYPE_E { TECHPOINT_TP2850_MIPI_2M_30FPS_8BIT, TECHPOINT_TP2850_MIPI_4M_30FPS_8BIT, TECHPOINT_TP2825_MIPI_2M_30FPS_8BIT, + TECHPOINT_TP2863_MIPI_1M_25FPS_8BIT, + TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT, + TECHPOINT_TP2863_MIPI_1M_30FPS_8BIT, + TECHPOINT_TP2863_MIPI_2M_30FPS_8BIT, VIVO_MCS369_2M_30FPS_12BIT, VIVO_MCS369Q_4M_30FPS_12BIT, VIVO_MM308M2_2M_25FPS_8BIT, diff --git a/middleware/v2/sample/common/sample_common_sensor.c b/middleware/v2/sample/common/sample_common_sensor.c index d599c8b46..c00f6f3ab 100644 --- a/middleware/v2/sample/common/sample_common_sensor.c +++ b/middleware/v2/sample/common/sample_common_sensor.c @@ -86,6 +86,7 @@ static const char *snsr_type_name[SAMPLE_SNS_TYPE_BUTT] = { /* ------ LINEAR BEGIN ------*/ "BRIGATES_BG0808_MIPI_2M_30FPS_10BIT", "GCORE_GC02M1_MIPI_2M_30FPS_10BIT", + "GCORE_GC0329_MIPI_480P_10FPS_8BIT", "GCORE_GC1054_MIPI_1M_30FPS_10BIT", "GCORE_GC2053_MIPI_2M_30FPS_10BIT", "GCORE_GC2053_SLAVE_MIPI_2M_30FPS_10BIT", @@ -96,6 +97,7 @@ static const char *snsr_type_name[SAMPLE_SNS_TYPE_BUTT] = { "GCORE_GC4023_MIPI_4M_30FPS_10BIT", "GCORE_GC4653_MIPI_4M_30FPS_10BIT", "GCORE_GC4653_SLAVE_MIPI_4M_30FPS_10BIT", + "IMGDS_MIS2008_MIPI_2M_1080P_30FPS_12BIT", "NEXTCHIP_N5_1M_2CH_25FPS_8BIT", "NEXTCHIP_N5_2M_25FPS_8BIT", "NEXTCHIP_N6_2M_4CH_25FPS_8BIT", @@ -186,6 +188,10 @@ static const char *snsr_type_name[SAMPLE_SNS_TYPE_BUTT] = { "TECHPOINT_TP2850_MIPI_2M_30FPS_8BIT", "TECHPOINT_TP2850_MIPI_4M_30FPS_8BIT", "TECHPOINT_TP2825_MIPI_2M_30FPS_8BIT", + "TECHPOINT_TP2863_MIPI_1M_25FPS_8BIT", + "TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT", + "TECHPOINT_TP2863_MIPI_1M_30FPS_8BIT", + "TECHPOINT_TP2863_MIPI_2M_30FPS_8BIT", "VIVO_MCS369_2M_30FPS_12BIT", "VIVO_MCS369Q_4M_30FPS_12BIT", "VIVO_MM308M2_2M_25FPS_8BIT", @@ -291,6 +297,8 @@ CVI_S32 SAMPLE_COMM_SNS_GetSize(SAMPLE_SNS_TYPE_E enMode, PIC_SIZE_E *penSize) case SMS_SC1346_1L_SLAVE_MIPI_1M_60FPS_10BIT: case SOI_H65_MIPI_1M_30FPS_10BIT: case SONY_IMX290_MIPI_1M_30FPS_12BIT: + case TECHPOINT_TP2863_MIPI_1M_25FPS_8BIT: + case TECHPOINT_TP2863_MIPI_1M_30FPS_8BIT: #ifdef FPGA_PORTING case SONY_IMX327_MIPI_1M_30FPS_10BIT: case SONY_IMX327_MIPI_1M_30FPS_10BIT_WDR2TO1: @@ -355,8 +363,11 @@ CVI_S32 SAMPLE_COMM_SNS_GetSize(SAMPLE_SNS_TYPE_E enMode, PIC_SIZE_E *penSize) case SONY_IMX385_MIPI_2M_30FPS_12BIT_WDR2TO1: case TECHPOINT_TP2850_MIPI_2M_30FPS_8BIT: case TECHPOINT_TP2825_MIPI_2M_30FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_30FPS_8BIT: case VIVO_MCS369_2M_30FPS_12BIT: case VIVO_MM308M2_2M_25FPS_8BIT: + case IMGDS_MIS2008_MIPI_2M_1080P_30FPS_12BIT: *penSize = PIC_1080P; break; case GCORE_GC4023_MIPI_4M_30FPS_10BIT: @@ -440,6 +451,7 @@ CVI_S32 SAMPLE_COMM_SNS_GetSize(SAMPLE_SNS_TYPE_E enMode, PIC_SIZE_E *penSize) case SMS_SC035GS_MIPI_480P_120FPS_12BIT: case SMS_SC035GS_1L_MIPI_480P_120FPS_10BIT: case SMS_SC035HGS_MIPI_480P_120FPS_12BIT: + case GCORE_GC0329_MIPI_480P_10FPS_8BIT: *penSize = PIC_640x480; break; case PICO640_THERMAL_479P: @@ -673,10 +685,19 @@ CVI_S32 SAMPLE_COMM_SNS_GetDevAttr(SAMPLE_SNS_TYPE_E enSnsType, VI_DEV_ATTR_S *p pstViDevAttr->enIntfMode = VI_MODE_MIPI_YUV422; break; case GCORE_GC2145_MIPI_2M_12FPS_8BIT: + case GCORE_GC0329_MIPI_480P_10FPS_8BIT: pstViDevAttr->enDataSeq = VI_DATA_SEQ_YUYV; pstViDevAttr->enInputDataType = VI_DATA_TYPE_YUV; pstViDevAttr->enIntfMode = VI_MODE_BT601; break; + case TECHPOINT_TP2863_MIPI_1M_25FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT: + case TECHPOINT_TP2863_MIPI_1M_30FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_30FPS_8BIT: + pstViDevAttr->enDataSeq = VI_DATA_SEQ_UYVY; + pstViDevAttr->enInputDataType = VI_DATA_TYPE_YUV; + pstViDevAttr->enIntfMode = VI_MODE_MIPI_YUV422; + break; default: break; }; @@ -684,6 +705,7 @@ CVI_S32 SAMPLE_COMM_SNS_GetDevAttr(SAMPLE_SNS_TYPE_E enSnsType, VI_DEV_ATTR_S *p // BT601 switch (enSnsType) { case GCORE_GC2145_MIPI_2M_12FPS_8BIT: + case GCORE_GC0329_MIPI_480P_10FPS_8BIT: pstViDevAttr->enIntfMode = VI_MODE_BT601; break; default: @@ -827,11 +849,16 @@ CVI_S32 SAMPLE_COMM_SNS_GetYuvBypassSts(SAMPLE_SNS_TYPE_E enSnsType) CVI_S32 s32Ret = 0; //Set YUV sensor need bypass isp switch (enSnsType) { + case GCORE_GC0329_MIPI_480P_10FPS_8BIT: case GCORE_GC2145_MIPI_2M_12FPS_8BIT: case PICO640_THERMAL_479P: case TECHPOINT_TP2850_MIPI_2M_30FPS_8BIT: case TECHPOINT_TP2850_MIPI_4M_30FPS_8BIT: case TECHPOINT_TP2825_MIPI_2M_30FPS_8BIT: + case TECHPOINT_TP2863_MIPI_1M_25FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT: + case TECHPOINT_TP2863_MIPI_1M_30FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_30FPS_8BIT: case VIVO_MCS369Q_4M_30FPS_12BIT: case VIVO_MCS369_2M_30FPS_12BIT: case VIVO_MM308M2_2M_25FPS_8BIT: @@ -896,6 +923,8 @@ CVI_S32 SAMPLE_COMM_SNS_GetIspAttrBySns(SAMPLE_SNS_TYPE_E enSnsType, ISP_PUB_ATT break; case TECHPOINT_TP2850_MIPI_2M_30FPS_8BIT: case TECHPOINT_TP2850_MIPI_4M_30FPS_8BIT: + case TECHPOINT_TP2863_MIPI_1M_30FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_30FPS_8BIT: case SMS_SC1346_1L_MIPI_1M_30FPS_10BIT: case SMS_SC1346_1L_MIPI_1M_30FPS_10BIT_WDR2TO1: case SMS_SC1346_1L_SLAVE_MIPI_1M_30FPS_10BIT: @@ -907,12 +936,19 @@ CVI_S32 SAMPLE_COMM_SNS_GetIspAttrBySns(SAMPLE_SNS_TYPE_E enSnsType, ISP_PUB_ATT case GCORE_GC2145_MIPI_2M_12FPS_8BIT: pstPubAttr->f32FrameRate = 12; break; + case GCORE_GC0329_MIPI_480P_10FPS_8BIT: + pstPubAttr->f32FrameRate = 10; + break; #ifdef FPGA_PORTING case SONY_IMX327_MIPI_1M_30FPS_10BIT: case SONY_IMX327_MIPI_1M_30FPS_10BIT_WDR2TO1: pstPubAttr->f32FrameRate = 10; break; #endif + case TECHPOINT_TP2863_MIPI_1M_25FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT: + pstPubAttr->f32FrameRate = 25; + break; default: pstPubAttr->f32FrameRate = 25; break; @@ -974,6 +1010,7 @@ CVI_S32 SAMPLE_COMM_SNS_GetIspAttrBySns(SAMPLE_SNS_TYPE_E enSnsType, ISP_PUB_ATT case GCORE_GC2093_SLAVE_MIPI_2M_30FPS_10BIT: case GCORE_GC2093_SLAVE_MIPI_2M_30FPS_10BIT_WDR2TO1: case GCORE_GC4023_MIPI_4M_30FPS_10BIT: + case IMGDS_MIS2008_MIPI_2M_1080P_30FPS_12BIT: pstPubAttr->enBayer = BAYER_RGGB; break; case GCORE_GC4653_MIPI_4M_30FPS_10BIT: @@ -1013,6 +1050,10 @@ CVI_VOID *SAMPLE_COMM_SNS_GetSnsObj(SAMPLE_SNS_TYPE_E enSnsType) case GCORE_GC02M1_MIPI_2M_30FPS_10BIT: return &stSnsGc02m1_Obj; #endif +#if defined(SENSOR_GCORE_GC0329) + case GCORE_GC0329_MIPI_480P_10FPS_8BIT: + return &stSnsGc0329_Obj; +#endif #if defined(SENSOR_GCORE_GC1054) case GCORE_GC1054_MIPI_1M_30FPS_10BIT: return &stSnsGc1054_Obj; @@ -1056,6 +1097,11 @@ CVI_VOID *SAMPLE_COMM_SNS_GetSnsObj(SAMPLE_SNS_TYPE_E enSnsType) case GCORE_GC4653_SLAVE_MIPI_4M_30FPS_10BIT: return &stSnsGc4653_Slave_Obj; #endif +#if defined(SENSOR_ID_MIS2008) + case IMGDS_MIS2008_MIPI_2M_1080P_30FPS_12BIT: + pSnsObj = &stSnsMIS2008_Obj; + break; +#endif #if defined(SENSOR_NEXTCHIP_N5) case NEXTCHIP_N5_2M_25FPS_8BIT: case NEXTCHIP_N5_1M_2CH_25FPS_8BIT: @@ -1426,6 +1472,14 @@ CVI_VOID *SAMPLE_COMM_SNS_GetSnsObj(SAMPLE_SNS_TYPE_E enSnsType) pSnsObj = &stSnsTP2825_Obj; break; #endif +#if defined(SENSOR_TECHPOINT_TP2863) + case TECHPOINT_TP2863_MIPI_1M_30FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_30FPS_8BIT: + case TECHPOINT_TP2863_MIPI_1M_25FPS_8BIT: + case TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT: + pSnsObj = &stSnsTP2863_Obj; + break; +#endif #if defined(SENSOR_VIVO_MCS369) case VIVO_MCS369_2M_30FPS_12BIT: pSnsObj = &stSnsMCS369_Obj; @@ -1812,11 +1866,11 @@ CVI_S32 SAMPLE_COMM_SNS_ParseIni(SAMPLE_INI_CFG_S *pstIniCfg) SAMPLE_PRT("Parse %s\n", g_snsCfgPath); ret = ini_parse(g_snsCfgPath, parse_handler, pstIniCfg); if (ret >= 0) { - return 1; + return CVI_SUCCESS; } if (ret != -1) { SAMPLE_PRT("Parse %s incomplete, use default cfg\n", INI_FILE_PATH); - return 0; + return CVI_FAILURE; } SAMPLE_PRT("%s Not Found\n", g_snsCfgPath); @@ -1824,11 +1878,11 @@ CVI_S32 SAMPLE_COMM_SNS_ParseIni(SAMPLE_INI_CFG_S *pstIniCfg) SAMPLE_PRT("Parse %s\n", INI_FILE_PATH); ret = ini_parse(INI_FILE_PATH, parse_handler, pstIniCfg); if (ret >= 0) { - return 1; + return CVI_SUCCESS; } if (ret != -1) { SAMPLE_PRT("Parse %s incomplete, use default cfg\n", INI_FILE_PATH); - return 0; + return CVI_FAILURE; } SAMPLE_PRT("%s Not Found\n", INI_FILE_PATH); SAMPLE_PRT("Parse %s\n", INI_DEF_PATH); @@ -1841,8 +1895,8 @@ CVI_S32 SAMPLE_COMM_SNS_ParseIni(SAMPLE_INI_CFG_S *pstIniCfg) SAMPLE_PRT("Parse %s incomplete, use default cfg\n", INI_DEF_PATH); } - return 0; + return CVI_FAILURE; } - return 1; + return CVI_SUCCESS; } \ No newline at end of file diff --git a/middleware/v2/sample/common/sample_common_vo.c b/middleware/v2/sample/common/sample_common_vo.c index a906474f5..698b9defe 100644 --- a/middleware/v2/sample/common/sample_common_vo.c +++ b/middleware/v2/sample/common/sample_common_vo.c @@ -21,6 +21,7 @@ #include "dsi_hx8394_evb.h" #include "i80_st7789v.h" +#include "bt656_tp2803.h" static CVI_S32 sample_vo_i2c_file = -1; static CVI_S32 sample_vo_i2c_slave_addr; @@ -176,6 +177,8 @@ CVI_S32 SAMPLE_COMM_VO_FillIntfAttr(VO_PUB_ATTR_S *pstPubAttr) case VO_INTF_YPBPR: case VO_INTF_VGA: case VO_INTF_BT656: + pstPubAttr->stBtAttr = stTP2803Cfg; + break; case VO_INTF_BT1120: case VO_INTF_LCD: case VO_INTF_LCD_18BIT: diff --git a/middleware/v2/sample/mipi_tx/sample_dsi.c b/middleware/v2/sample/mipi_tx/sample_dsi.c index e1d015f29..2db50c3ee 100644 --- a/middleware/v2/sample/mipi_tx/sample_dsi.c +++ b/middleware/v2/sample/mipi_tx/sample_dsi.c @@ -3,7 +3,7 @@ #include #include #include - +#include #include #include #include @@ -17,6 +17,33 @@ #define PANLE_ADAPTIVITY 0 static int fd; +#define MAX_DSI_OPTIONS 128 +typedef enum _ARG_TYPE_ { + ARG_INT = 0, + ARG_UINT, + ARG_STRING, +} ARG_TYPE; + +typedef struct _optionExt_ { + struct option opt; + int type; + int64_t min; + int64_t max; + const char *help; +} optionExt; + +static optionExt long_option_ext[] = { + {{"laneid", optional_argument, NULL, 'l'}, ARG_STRING, 0, 0, + "laneid sequence by order"}, + {{"pnswap", optional_argument, NULL, 'p'}, ARG_STRING, 0, 0, + "pnswap sequence by order"}, + {{"dsi-control", no_argument, NULL, 'd'}, ARG_STRING, 0, 0, + "set/get dsi status or settings." }, + {{"help", no_argument, NULL, 'h'}, ARG_STRING, 0, 0, + "print usage."}, + {{NULL, 0, NULL, 0}, ARG_INT, 0, 0, "no param: just init the panel."} +}; + int dsi_init(int devno, const struct dsc_instr *cmds, int size) { int ret; @@ -142,39 +169,91 @@ void SAMPLE_DSI_Print_Control(void) printf(" 5: set hs settle settings\n"); } -void SAMPLE_DSI_Usage(char *sPrgNm) +void printDsiHelp(char **argv) { - printf("Usage : %s \n", sPrgNm); - printf("no param: just init the panel.\n"); - printf("-h: print usage.\n"); - printf("-d: set/get dsi status or settings.\n"); + CVI_U32 idx; + + printf("// ------------------------------------------------\n"); + printf("%s --laneid=laneid sequence --pnswap=pnswap sequence\n", argv[0]); + printf("EX.\n"); + printf(" %s -h\n", argv[0]); + printf(" %s --laneid=1,2,0,-1,-1 --pnswap=1,1,0,0,0\n", argv[0]); + printf(" %s -d\n", argv[0]); + printf("// ------------------------------------------------\n"); + + for (idx = 0; idx < sizeof(long_option_ext) / sizeof(optionExt); idx++) { + if (long_option_ext[idx].opt.name == NULL) + break; + + printf("--%s\n", long_option_ext[idx].opt.name); + printf(" %s\n", long_option_ext[idx].help); + } } -int main(int argc, char *argv[]) +CVI_S32 SAMPLE_MIPI_SET_LANEID(char* pLaneid) +{ + if (pLaneid ==NULL) { + return CVI_FAILURE; + } + + CVI_S32 lane_id[] = {0,0,0,0,0}; + CVI_S32 n = sscanf(pLaneid, "%02d,%02d,%02d,%02d,%02d", &lane_id[0], &lane_id[1],&lane_id[2],&lane_id[3],&lane_id[4]); + + if(n != sizeof(lane_id)/sizeof(CVI_S32)) { + return CVI_FAILURE; + } + + for(CVI_U32 i = 0; i < sizeof(lane_id)/sizeof(CVI_S32); i++) { + if(lane_id[i] < -1 || lane_id[i] > 5) { + return CVI_FAILURE; + } + dev_cfg_hx8394_720x1280.lane_id[i] = lane_id[i]; + } + + return CVI_SUCCESS; +} + +CVI_S32 SAMPLE_MIPI_SET_PNSWAP(char* pPnswap) +{ + if (pPnswap ==NULL) { + return CVI_FAILURE; + } + + CVI_U32 pnswap[] = {0,0,0,0,0}; + CVI_S32 n = sscanf(pPnswap, "%02d,%02d,%02d,%02d,%02d", &pnswap[0], &pnswap[1],&pnswap[2],&pnswap[3],&pnswap[4]); + + if(n != sizeof(pnswap)/sizeof(CVI_U32)) { + return CVI_FAILURE; + } + + for(CVI_U32 i = 0; i < sizeof(pnswap)/sizeof(CVI_U32); i++) { + if((pnswap[i] != 0) && (pnswap[i] != 1)) { + return CVI_FAILURE; + } + dev_cfg_hx8394_720x1280.lane_pn_swap[i] = (bool)(pnswap[i]); + } + + return CVI_SUCCESS; +} + +CVI_S32 SAMPLE_MIPI_TX_ENABLE() { fd = open(MIPI_TX_NAME, O_RDWR | O_NONBLOCK, 0); if (fd == -1) { SAMPLE_PRT("Cannot open '%s': %d, %s\n", MIPI_TX_NAME, errno, strerror(errno)); - return -1; - } - - if (argc == 1) { - mipi_tx_disable(fd); - mipi_tx_cfg(fd, (struct combo_dev_cfg_s *)panel_desc.dev_cfg); - dsi_init(0, panel_desc.dsi_init_cmds, panel_desc.dsi_init_cmds_size); - mipi_tx_set_hs_settle(fd, panel_desc.hs_timing_cfg); - mipi_tx_enable(fd); - printf("Init for MIPI-Driver-%s\n", panel_desc.panel_name); - return 0; - } else if (argc == 2) { - if (!strncmp(argv[1], "-d", 2)) - ; - else { - SAMPLE_DSI_Usage(argv[0]); - return 0; - } + return CVI_FAILURE; } + mipi_tx_disable(fd); + mipi_tx_cfg(fd, (struct combo_dev_cfg_s *)panel_desc.dev_cfg); + dsi_init(0, panel_desc.dsi_init_cmds, panel_desc.dsi_init_cmds_size); + mipi_tx_set_hs_settle(fd, panel_desc.hs_timing_cfg); + mipi_tx_enable(fd); + printf("Init for MIPI-Driver-%s\n", panel_desc.panel_name); + return CVI_SUCCESS; +} +void SAMPLE_DSI_CONTROLE() +{ do { CVI_U32 tmp; SAMPLE_DSI_Print_Control(); @@ -252,6 +331,74 @@ int main(int argc, char *argv[]) } else break; } while (1); +} +int main(int argc, char *argv[]) +{ + if(argc == 1) { + SAMPLE_MIPI_TX_ENABLE(); + return CVI_SUCCESS; + } + + struct option long_options[MAX_DSI_OPTIONS + 1]; + CVI_S32 ch, idx, ret; + bool use_input_para = false; + + memset((void *)long_options, 0, sizeof(long_options)); + + for (idx = 0; idx < MAX_DSI_OPTIONS; idx++) { + if (long_option_ext[idx].opt.name == NULL) + break; + + if (idx >= MAX_DSI_OPTIONS) { + CVI_TRACE_LOG(CVI_DBG_ERR, "too many options\n"); + return -1; + } + + memcpy(&long_options[idx], &long_option_ext[idx].opt, sizeof(struct option)); + } + + optind = 0; + while ((ch = getopt_long(argc, argv, "dh", long_options, &idx)) != -1) { + switch (ch) { + case 'l': + ret = SAMPLE_MIPI_SET_LANEID(optarg); + if(ret != CVI_SUCCESS) { + CVI_TRACE_LOG(CVI_DBG_ERR, "invalid laneid parameter\n"); + return ret; + } + use_input_para = true; + break; + case 'p': + ret = SAMPLE_MIPI_SET_PNSWAP(optarg); + if(ret != CVI_SUCCESS) { + CVI_TRACE_LOG(CVI_DBG_ERR, "invalid pnswap parameter\n"); + return ret; + } + use_input_para = true; + break; + case 'd': + if(argc > 2) { + CVI_TRACE_LOG(CVI_DBG_ERR, "usage:%s -d. -d can't use in the same time with other command\n", argv[0]); + return CVI_FAILURE; + } + SAMPLE_DSI_CONTROLE(); + break; + case 'h': + printDsiHelp(argv); + break; + default: + SAMPLE_PRT("ch = %c\n", ch); + printDsiHelp(argv); + break; + } + } + + if (optind < argc) + printDsiHelp(argv); + + if(use_input_para) { + SAMPLE_MIPI_TX_ENABLE(); + } return 0; } diff --git a/middleware/v2/sample/tp2863_tp2803/Makefile b/middleware/v2/sample/tp2863_tp2803/Makefile new file mode 100644 index 000000000..050d88fc9 --- /dev/null +++ b/middleware/v2/sample/tp2863_tp2803/Makefile @@ -0,0 +1,64 @@ +SHELL = /bin/bash +ifeq ($(PARAM_FILE), ) + PARAM_FILE:=../../Makefile.param + include $(PARAM_FILE) +endif +include ../sample.mk + +SDIR = $(PWD) +SRCS = $(wildcard $(SDIR)/*.c) +INCS = -I$(MW_INC) -I$(ISP_INC) -I../common/ -I$(KERNEL_INC) +OBJS = $(SRCS:.c=.o) +DEPS = $(SRCS:.c=.d) + +TARGET = sample_test_tp2863_tp2803 +ifeq ($(CONFIG_ENABLE_SDK_ASAN), y) +TARGET = sample_test_tp2863_tp2803_asan +endif + +PKG_CONFIG_PATH = $(MW_PATH)/pkgconfig +REQUIRES = cvi_common cvi_sample + +MW_LIBS = $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) pkg-config --libs --define-variable=mw_dir=$(MW_PATH) $(REQUIRES)) + +LIBS = $(MW_LIBS) +ifeq ($(MULTI_PROCESS_SUPPORT), 1) +DEFS += -DRPC_MULTI_PROCESS +LIBS += -lnanomsg +endif + +EXTRA_CFLAGS = $(INCS) $(DEFS) +EXTRA_LDFLAGS = $(LIBS) -lpthread -lm -lini + +# IVE_SUPPORT = 1 +ifeq ($(IVE_SUPPORT), 1) +CFLAGS += -DIVE_SUPPORT + +IVE_PATH = $(MW_PATH)/../install/soc_cv1835_wevb_0002a_spinand/tpu_64/cvitek_ive_sdk +EXTRA_CFLAGS += -I$(IVE_PATH)/include/ive +EXTRA_LDFLAGS += -L$(IVE_PATH)/lib -lcvi_ive_tpu-static + +TPU_PATH = $(MW_PATH)/../install/soc_cv1835_wevb_0002a_spinand/tpu_64/cvitek_tpu_sdk +EXTRA_CFLAGS += -I$(TPU_PATH)/include +EXTRA_LDFLAGS += -L$(TPU_PATH)/lib -lcviruntime-static -lcvimath-static -lcvikernel-static -lcnpy -lglog -lz +endif + +.PHONY : clean all +all: $(TARGET) + +$(COMMON_DIR)/%.o: $(COMMON_DIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -o $@ -c $< + @echo [$(notdir $(CC))] $(notdir $@) + +$(SDIR)/%.o: $(SDIR)/%.c + @$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -o $@ -c $< + @echo [$(notdir $(CC))] $(notdir $@) + +$(TARGET): $(COMM_OBJ) $(OBJS) $(ISP_OBJ) $(MW_LIB)/libvpu.a $(MW_LIB)/libsys.a + @$(CXX) -o $@ -Wl,--start-group $(OBJS) $(COMM_OBJS) -lsys $(MW_LIB)/libsys.a -Wl,--end-group $(ELFFLAGS) $(EXTRA_LDFLAGS) + @echo -e $(BLUE)[LINK]$(END)[$(notdir $(CXX))] $(notdir $@) + +clean: + @rm -f $(OBJS) $(DEPS) $(COMM_OBJ) $(COMM_DEPS) $(TARGET) + +-include $(DEPS) diff --git a/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.c b/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.c new file mode 100644 index 000000000..28239c0ef --- /dev/null +++ b/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.c @@ -0,0 +1,280 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cvi_buffer.h" +#include "cvi_ae_comm.h" +#include "cvi_awb_comm.h" +#include "cvi_comm_isp.h" + +#include "sample_comm.h" +#include "sample_vio_tp2863_tp2803.h" + +#define FILENAME "testpic.yuv" + +VI_PIPE ViPipe = 0; +VI_CHN ViChn = 0; +SAMPLE_VI_CONFIG_S stViConfig; +VPSS_GRP VpssGrp = 0; +VPSS_CHN VpssChn = VPSS_CHN0; +CVI_BOOL abChnEnable[VPSS_MAX_PHY_CHN_NUM] = {0}; +SAMPLE_VO_CONFIG_S stVoConfig; +VO_CHN VoChn = 0; + +CVI_S32 SAMPLE_VIO(void) +{ + SAMPLE_SNS_TYPE_E enSnsType = TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT; + WDR_MODE_E enWDRMode = WDR_MODE_NONE; + DYNAMIC_RANGE_E enDynamicRange = DYNAMIC_RANGE_SDR8; + PIXEL_FORMAT_E enPixFormat = PIXEL_FORMAT_UYVY; + VIDEO_FORMAT_E enVideoFormat = VIDEO_FORMAT_LINEAR; + COMPRESS_MODE_E enCompressMode = COMPRESS_MODE_NONE; + VI_VPSS_MODE_E enMastPipeMode = VI_OFFLINE_VPSS_OFFLINE; + + VB_CONFIG_S stVbConf; + PIC_SIZE_E enPicSize; + CVI_U32 u32BlkSize; + SIZE_S stSize; + CVI_S32 s32Ret = CVI_SUCCESS; + + VI_DEV ViDev = 0; + CVI_S32 s32WorkSnsId = 0; + VI_PIPE_ATTR_S stPipeAttr; + + /************************************************ + * step1: Config VI + ************************************************/ + SAMPLE_COMM_VI_GetSensorInfo(&stViConfig); + + stViConfig.astViInfo[s32WorkSnsId].stSnsInfo.enSnsType = enSnsType; + stViConfig.s32WorkingViNum = 1; + stViConfig.as32WorkingViId[0] = 0; + stViConfig.astViInfo[s32WorkSnsId].stSnsInfo.MipiDev = 0xFF; + stViConfig.astViInfo[s32WorkSnsId].stSnsInfo.s32BusId = 3; + stViConfig.astViInfo[s32WorkSnsId].stDevInfo.ViDev = ViDev; + stViConfig.astViInfo[s32WorkSnsId].stDevInfo.enWDRMode = enWDRMode; + stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.enMastPipeMode = enMastPipeMode; + stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.aPipe[0] = ViPipe; + stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.aPipe[1] = -1; + stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.aPipe[2] = -1; + stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.aPipe[3] = -1; + stViConfig.astViInfo[s32WorkSnsId].stChnInfo.ViChn = ViChn; + stViConfig.astViInfo[s32WorkSnsId].stChnInfo.enPixFormat = enPixFormat; + stViConfig.astViInfo[s32WorkSnsId].stChnInfo.enDynamicRange = enDynamicRange; + stViConfig.astViInfo[s32WorkSnsId].stChnInfo.enVideoFormat = enVideoFormat; + stViConfig.astViInfo[s32WorkSnsId].stChnInfo.enCompressMode = enCompressMode; + + /************************************************ + * step2: Get input size + ************************************************/ + s32Ret = SAMPLE_COMM_VI_GetSizeBySensor(stViConfig.astViInfo[s32WorkSnsId].stSnsInfo.enSnsType, &enPicSize); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("SAMPLE_COMM_VI_GetSizeBySensor failed with %#x\n", s32Ret); + return s32Ret; + } + + s32Ret = SAMPLE_COMM_SYS_GetPicSize(enPicSize, &stSize); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("SAMPLE_COMM_SYS_GetPicSize failed with %#x\n", s32Ret); + return s32Ret; + } + + /************************************************ + * step3: Init SYS and common VB + ************************************************/ + memset(&stVbConf, 0, sizeof(VB_CONFIG_S)); + stVbConf.u32MaxPoolCnt = 1; + + u32BlkSize = COMMON_GetPicBufferSize(stSize.u32Width, stSize.u32Height, enPixFormat, DATA_BITWIDTH_8 + , enCompressMode, DEFAULT_ALIGN); + stVbConf.astCommPool[0].u32BlkSize = u32BlkSize; + stVbConf.astCommPool[0].u32BlkCnt = 16; + SAMPLE_PRT("common pool[0] BlkSize %d\n", u32BlkSize); + + s32Ret = SAMPLE_COMM_SYS_Init(&stVbConf); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("system init failed with %#x\n", s32Ret); + return -1; + } + + /************************************************ + * step4: Init VI ISP + ************************************************/ + s32Ret = SAMPLE_COMM_VI_StartSensor(&stViConfig); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_LOG(CVI_DBG_ERR, "system start sensor failed with %#x\n", s32Ret); + return s32Ret; + } + s32Ret = SAMPLE_COMM_VI_StartDev(&stViConfig.astViInfo[ViDev]); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_LOG(CVI_DBG_ERR, "VI_StartDev failed with %#x!\n", s32Ret); + return s32Ret; + } + s32Ret = SAMPLE_COMM_VI_StartMIPI(&stViConfig); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_LOG(CVI_DBG_ERR, "system start MIPI failed with %#x\n", s32Ret); + return s32Ret; + } + + stPipeAttr.bYuvSkip = CVI_FALSE; + stPipeAttr.u32MaxW = stSize.u32Width; + stPipeAttr.u32MaxH = stSize.u32Height; + stPipeAttr.enPixFmt = PIXEL_FORMAT_RGB_BAYER_12BPP; + stPipeAttr.enBitWidth = DATA_BITWIDTH_12; + stPipeAttr.stFrameRate.s32SrcFrameRate = -1; + stPipeAttr.stFrameRate.s32DstFrameRate = -1; + stPipeAttr.bYuvBypassPath = CVI_TRUE; + stPipeAttr.bNrEn = CVI_TRUE; + s32Ret = CVI_VI_CreatePipe(ViPipe, &stPipeAttr); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("CVI_VI_CreatePipe failed with %#x!\n", s32Ret); + return s32Ret; + } + + s32Ret = CVI_VI_StartPipe(ViPipe); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("CVI_VI_StartPipe failed with %#x!\n", s32Ret); + return s32Ret; + } + + s32Ret = CVI_VI_GetPipeAttr(ViPipe, &stPipeAttr); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("CVI_VI_StartPipe failed with %#x!\n", s32Ret); + return s32Ret; + } + + s32Ret = SAMPLE_COMM_VI_CreateIsp(&stViConfig); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_LOG(CVI_DBG_ERR, "VI_CreateIsp failed with %#x!\n", s32Ret); + return s32Ret; + } + + SAMPLE_COMM_VI_StartViChn(&stViConfig); + + /************************************************ + * step5: Init VPSS + ************************************************/ + VPSS_GRP_ATTR_S stVpssGrpAttr; + VPSS_CHN_ATTR_S astVpssChnAttr[VPSS_MAX_PHY_CHN_NUM] = {0}; + + stVpssGrpAttr.stFrameRate.s32SrcFrameRate = -1; + stVpssGrpAttr.stFrameRate.s32DstFrameRate = -1; + stVpssGrpAttr.enPixelFormat = PIXEL_FORMAT_UYVY; + stVpssGrpAttr.u32MaxW = stSize.u32Width; + stVpssGrpAttr.u32MaxH = stSize.u32Height; + stVpssGrpAttr.u8VpssDev = 0; + + astVpssChnAttr[VpssChn].u32Width = 1280; + astVpssChnAttr[VpssChn].u32Height = 720; + astVpssChnAttr[VpssChn].enVideoFormat = VIDEO_FORMAT_LINEAR; + astVpssChnAttr[VpssChn].enPixelFormat = PIXEL_FORMAT_NV21; + astVpssChnAttr[VpssChn].stFrameRate.s32SrcFrameRate = -1; + astVpssChnAttr[VpssChn].stFrameRate.s32DstFrameRate = -1; + astVpssChnAttr[VpssChn].u32Depth = 0; + astVpssChnAttr[VpssChn].bMirror = CVI_FALSE; + astVpssChnAttr[VpssChn].bFlip = CVI_FALSE; + astVpssChnAttr[VpssChn].stAspectRatio.enMode = ASPECT_RATIO_NONE; + astVpssChnAttr[VpssChn].stNormalize.bEnable = CVI_FALSE; + + /*start vpss*/ + abChnEnable[0] = CVI_TRUE; + s32Ret = SAMPLE_COMM_VPSS_Init(VpssGrp, abChnEnable, &stVpssGrpAttr, astVpssChnAttr); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("init vpss group failed. s32Ret: 0x%x !\n", s32Ret); + return s32Ret; + } + + s32Ret = SAMPLE_COMM_VPSS_Start(VpssGrp, abChnEnable, &stVpssGrpAttr, astVpssChnAttr); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("start vpss group failed. s32Ret: 0x%x !\n", s32Ret); + return s32Ret; + } + + s32Ret = SAMPLE_COMM_VI_Bind_VPSS(ViPipe, ViChn, VpssGrp); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("vi bind vpss failed. s32Ret: 0x%x !\n", s32Ret); + return s32Ret; + } + + /************************************************ + * step6: Init VO + ************************************************/ + RECT_S stDefDispRect = {0, 0, 1280, 720}; + SIZE_S stDefImageSize = {1280, 720}; + + s32Ret = SAMPLE_COMM_VO_GetDefConfig(&stVoConfig); + if (s32Ret != CVI_SUCCESS) { + CVI_TRACE_LOG(CVI_DBG_ERR, "SAMPLE_COMM_VO_GetDefConfig failed with %#x\n", s32Ret); + return s32Ret; + } + + stVoConfig.VoDev = 0; + stVoConfig.stVoPubAttr.enIntfType = VO_INTF_BT656; + stVoConfig.stVoPubAttr.enIntfSync = VO_OUTPUT_720P50; + stVoConfig.stDispRect = stDefDispRect; + stVoConfig.stImageSize = stDefImageSize; + stVoConfig.enPixFormat = PIXEL_FORMAT_NV21; + stVoConfig.enVoMode = VO_MODE_1MUX; + + s32Ret = SAMPLE_COMM_VO_StartVO(&stVoConfig); + if (s32Ret != CVI_SUCCESS) { + SAMPLE_PRT("SAMPLE_COMM_VO_StartVO failed with %#x\n", s32Ret); + return s32Ret; + } + + SAMPLE_COMM_VPSS_Bind_VO(VpssGrp, VpssChn, 0, 0); + + // s32Ret = SAMPLE_COMM_VPSS_SendFrame(VpssGrp, &stSize, PIXEL_FORMAT_UYVY, FILENAME); + // if (s32Ret != CVI_SUCCESS) { + // SAMPLE_PRT("SAMPLE_COMM_VPSS_SendFrame for grp0 chn0. s32Ret: 0x%x !\n", s32Ret); + // return s32Ret; + // } + + // VIDEO_FRAME_INFO_S stVideoFrame; + // s32Ret = CVI_VPSS_GetChnFrame(VpssGrp, VpssChn, &stVideoFrame, -1/*10000*/); + // if (s32Ret != CVI_SUCCESS) { + // SAMPLE_PRT("CVI_VPSS_GetChnFrame for grp0 chn0. s32Ret: 0x%x !\n", s32Ret); + // return s32Ret; + // } + + // s32Ret = SAMPLE_COMM_FRAME_SaveToFile("vpss.yuv", &stVideoFrame); + // if (s32Ret != CVI_SUCCESS) { + // SAMPLE_PRT("SAMPLE_COMM_FRAME_SaveToFile. s32Ret: 0x%x !\n", s32Ret); + // } + + return s32Ret; +} + +void SAMPLE_VIO_HandleSig(CVI_S32 signo) +{ + signal(SIGINT, SIG_IGN); + signal(SIGTERM, SIG_IGN); + + if (SIGINT == signo || SIGTERM == signo) { + + SAMPLE_COMM_VPSS_UnBind_VO(VpssGrp, VpssChn, stVoConfig.VoDev, VoChn); + + SAMPLE_COMM_VO_StopVO(&stVoConfig); + + SAMPLE_COMM_VI_UnBind_VPSS(ViPipe, ViChn, VpssGrp); + + SAMPLE_COMM_VPSS_Stop(VpssGrp, abChnEnable); + + SAMPLE_COMM_VI_DestroyIsp(&stViConfig); + + SAMPLE_COMM_VI_DestroyVi(&stViConfig); + + SAMPLE_COMM_SYS_Exit(); + //todo for release + SAMPLE_PRT("Program termination abnormally\n"); + } + exit(-1); +} \ No newline at end of file diff --git a/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.h b/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.h new file mode 100644 index 000000000..1ec2085c9 --- /dev/null +++ b/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * File Name: sample_vio.h + * Description: + */ + +#ifndef __SAMPLE_VIO_H__ +#define __SAMPLE_VIO_H__ + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* End of #ifdef __cplusplus */ + +#include +#include + +CVI_S32 SAMPLE_VIO(void); +void SAMPLE_VIO_HandleSig(CVI_S32 signo); + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* End of #ifdef __cplusplus */ + +#endif /* End of #ifndef __SAMPLE_VIO_H__*/ diff --git a/middleware/v2/sample/tp2863_tp2803/tp2863_tp2803_main.c b/middleware/v2/sample/tp2863_tp2803/tp2863_tp2803_main.c new file mode 100644 index 000000000..abb679592 --- /dev/null +++ b/middleware/v2/sample/tp2863_tp2803/tp2863_tp2803_main.c @@ -0,0 +1,451 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sample_comm.h" +#include "sample_vio_tp2863_tp2803.h" +#include "cvi_sys.h" +#include + +const CVI_U8 tp2803_master_i2c_addr = 0x45; /* I2C slave address of tp2803 master chip*/ +const CVI_U32 tp2803_addr_byte = 1; +const CVI_U32 tp2803_data_byte = 1; +static int i2c_fd = -1; + +/*gpio*/ +enum CVI_GPIO_NUM_E { +CVI_GPIOD_00 = 404, +CVI_GPIOD_01, CVI_GPIOD_02, CVI_GPIOD_03, CVI_GPIOD_04, CVI_GPIOD_05, +CVI_GPIOD_06, CVI_GPIOD_07, CVI_GPIOD_08, CVI_GPIOD_09, CVI_GPIOD_10, +CVI_GPIOD_11, +CVI_GPIOC_00 = 416, +CVI_GPIOC_01, CVI_GPIOC_02, CVI_GPIOC_03, CVI_GPIOC_04, CVI_GPIOC_05, +CVI_GPIOC_06, CVI_GPIOC_07, CVI_GPIOC_08, CVI_GPIOC_09, CVI_GPIOC_10, +CVI_GPIOC_11, CVI_GPIOC_12, CVI_GPIOC_13, CVI_GPIOC_14, CVI_GPIOC_15, +CVI_GPIOC_16, CVI_GPIOC_17, CVI_GPIOC_18, CVI_GPIOC_19, CVI_GPIOC_20, +CVI_GPIOC_21, CVI_GPIOC_22, CVI_GPIOC_23, CVI_GPIOC_24, CVI_GPIOC_25, +CVI_GPIOC_26, CVI_GPIOC_27, CVI_GPIOC_28, CVI_GPIOC_29, CVI_GPIOC_30, +CVI_GPIOC_31, +CVI_GPIOB_00 = 448, +CVI_GPIOB_01, CVI_GPIOB_02, CVI_GPIOB_03, CVI_GPIOB_04, CVI_GPIOB_05, +CVI_GPIOB_06, CVI_GPIOB_07, CVI_GPIOB_08, CVI_GPIOB_09, CVI_GPIOB_10, +CVI_GPIOB_11, CVI_GPIOB_12, CVI_GPIOB_13, CVI_GPIOB_14, CVI_GPIOB_15, +CVI_GPIOB_16, CVI_GPIOB_17, CVI_GPIOB_18, CVI_GPIOB_19, CVI_GPIOB_20, +CVI_GPIOB_21, CVI_GPIOB_22, CVI_GPIOB_23, CVI_GPIOB_24, CVI_GPIOB_25, +CVI_GPIOB_26, CVI_GPIOB_27, CVI_GPIOB_28, CVI_GPIOB_29, CVI_GPIOB_30, +CVI_GPIOB_31, +CVI_GPIOA_00 = 480, +CVI_GPIOA_01, CVI_GPIOA_02, CVI_GPIOA_03, CVI_GPIOA_04, CVI_GPIOA_05, +CVI_GPIOA_06, CVI_GPIOA_07, CVI_GPIOA_08, CVI_GPIOA_09, CVI_GPIOA_10, +CVI_GPIOA_11, CVI_GPIOA_12, CVI_GPIOA_13, CVI_GPIOA_14, CVI_GPIOA_15, +CVI_GPIOA_16, CVI_GPIOA_17, CVI_GPIOA_18, CVI_GPIOA_19, CVI_GPIOA_20, +CVI_GPIOA_21, CVI_GPIOA_22, CVI_GPIOA_23, CVI_GPIOA_24, CVI_GPIOA_25, +CVI_GPIOA_26, CVI_GPIOA_27, CVI_GPIOA_28, CVI_GPIOA_29, CVI_GPIOA_30, +CVI_GPIOA_31, +}; + +#define CVI_GPIO_MIN CVI_GPIOD_00 +#define CVI_GPIO_MAX CVI_GPIOA_31 + +#define SYSFS_GPIO_DIR "/sys/class/gpio" +#define MAX_BUF 64 + +static int tp2803_GPIO_Export(unsigned int gpio) +{ + int fd, len; + char buf[MAX_BUF]; + + fd = open(SYSFS_GPIO_DIR"/export", O_WRONLY); + if (fd < 0) { + perror("gpio/export"); + return fd; + } + + len = snprintf(buf, sizeof(buf), "%d", gpio); + write(fd, buf, len); + close(fd); + + return 0; +} + +static int tp2803_GPIO_SetDirection(unsigned int gpio, unsigned int out_flag) +{ + int fd; + char buf[MAX_BUF]; + + snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR"/gpio%d/direction", gpio); + if (access(buf, 0) == -1) + tp2803_GPIO_Export(gpio); + + fd = open(buf, O_WRONLY); + if (fd < 0) { + perror("gpio/direction"); + return fd; + } + //printf("mark %d , %s\n",out_flag, buf); + if (out_flag) + write(fd, "out", 4); + else + write(fd, "in", 3); + + close(fd); + return 0; +} + +static int tp2803_GPIO_SetValue(unsigned int gpio, unsigned int value) +{ + int fd; + char buf[MAX_BUF]; + + snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR"/gpio%d/value", gpio); + if (access(buf, 0) == -1) + tp2803_GPIO_Export(gpio); + + tp2803_GPIO_SetDirection(gpio, 1); //output + + fd = open(buf, O_WRONLY); + if (fd < 0) { + perror("gpio/set-value"); + return fd; + } + + if (value) + write(fd, "1", 2); + else + write(fd, "0", 2); + + close(fd); + return 0; +} + +int tp2803_i2c_init(VI_PIPE ViPipe, CVI_U8 i2c_addr) +{ + UNUSED(ViPipe); + int ret; + char acDevFile[16] = {0}; + CVI_U8 u8DevNum = 1; + + snprintf(acDevFile, sizeof(acDevFile), "/dev/i2c-%u", u8DevNum); + printf("open %s\n", acDevFile); + + i2c_fd = open(acDevFile, O_RDWR, 0600); + if (i2c_fd < 0) { + printf("Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum); + return CVI_FAILURE; + } + + ret = ioctl(i2c_fd, I2C_SLAVE_FORCE, i2c_addr); + if (ret < 0) { + printf("I2C_SLAVE_FORCE error!\n"); + close(i2c_fd); + i2c_fd = -1; + return ret; + } + + return CVI_SUCCESS; +} + +int tp2803_read_register(VI_PIPE ViPipe, int addr) +{ + UNUSED(ViPipe); + int ret, data; + CVI_U8 buf[8]; + CVI_U8 idx = 0; + + if (tp2803_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + ret = write(i2c_fd, buf, tp2803_addr_byte); + if (ret < 0) { + printf("I2C_READ error!\n"); + return 0; + } + + buf[0] = 0; + buf[1] = 0; + ret = read(i2c_fd, buf, tp2803_data_byte); + if (ret < 0) { + printf("I2C_READ error!\n"); + return 0; + } + + // pack read back data + data = 0; + if (tp2803_data_byte == 2) { + data = buf[0] << 8; + data += buf[1]; + } else { + data = buf[0]; + } + + printf("i2c r 0x%x = 0x%x\n", addr, data); + return data; +} + +int tp2803_write_register(VI_PIPE ViPipe, int addr, int data) +{ + UNUSED(ViPipe); + CVI_U8 idx = 0; + int ret; + CVI_U8 buf[8]; + + if (tp2803_addr_byte == 2) + buf[idx++] = (addr >> 8) & 0xff; + + // add address byte 0 + buf[idx++] = addr & 0xff; + + if (tp2803_data_byte == 2) + buf[idx++] = (data >> 8) & 0xff; + + // add data byte 0 + buf[idx++] = data & 0xff; + + ret = write(i2c_fd, buf, tp2803_addr_byte + tp2803_data_byte); + if (ret < 0) { + printf("I2C_WRITE error!\n"); + return CVI_FAILURE; + } + printf("i2c w 0x%x 0x%x\n", addr, data); + +#if 0 // read back checing + ret = tp2803_read_register(ViPipe, addr); + if (ret != data) + printf("i2c readback-check fail, 0x%x != 0x%x\n", ret, data); +#endif + return CVI_SUCCESS; +} + +int tp2803_gpio_init(VI_PIPE ViPipe) +{ + (void) ViPipe; + + //VO_RESET + if (tp2803_GPIO_SetValue(CVI_GPIOB_13, 0) != 0) { + printf("set power down gpio error!\n"); + return CVI_FAILURE; + } + + usleep(100 * 1000); + + if (tp2803_GPIO_SetValue(CVI_GPIOB_13, 1) != 0) { + printf("set power down gpio error!\n"); + return CVI_FAILURE; + } + + usleep(100 * 1000); + + return CVI_SUCCESS; +} + +void tp2803_reg_init() +{ + //AHD 720P 25FPS + tp2803_write_register(0, 0xFF, 0x00); //Page 00 + tp2803_write_register(0, 0x00, 0x00); + tp2803_write_register(0, 0x01, 0x00); + tp2803_write_register(0, 0x02, 0x9B); + tp2803_write_register(0, 0x03, 0x62); + tp2803_write_register(0, 0x04, 0x00); + tp2803_write_register(0, 0x05, 0x6C); + tp2803_write_register(0, 0x06, 0x00); + tp2803_write_register(0, 0x07, 0xC1); + tp2803_write_register(0, 0x08, 0x76); + tp2803_write_register(0, 0x09, 0x76); + tp2803_write_register(0, 0x0A, 0x76); + tp2803_write_register(0, 0x0B, 0x15); + tp2803_write_register(0, 0x0C, 0x04); + tp2803_write_register(0, 0x0D, 0xF0); + tp2803_write_register(0, 0x0E, 0x82); + tp2803_write_register(0, 0x0F, 0x80); + tp2803_write_register(0, 0x10, 0x17); + tp2803_write_register(0, 0x11, 0x80); + tp2803_write_register(0, 0x12, 0x01); + tp2803_write_register(0, 0x13, 0x3C); + tp2803_write_register(0, 0x14, 0x38); + tp2803_write_register(0, 0x15, 0x39); + tp2803_write_register(0, 0x16, 0xEB); + tp2803_write_register(0, 0x17, 0x10); + tp2803_write_register(0, 0x18, 0x10); + tp2803_write_register(0, 0x19, 0xF0); + tp2803_write_register(0, 0x1A, 0x10); + tp2803_write_register(0, 0x1B, 0xA4); + tp2803_write_register(0, 0x1C, 0x55); + tp2803_write_register(0, 0x1D, 0x76); + tp2803_write_register(0, 0x1E, 0x80); + tp2803_write_register(0, 0x1F, 0x00); + tp2803_write_register(0, 0x20, 0x28); + tp2803_write_register(0, 0x21, 0xC4); + tp2803_write_register(0, 0x22, 0x44); + tp2803_write_register(0, 0x23, 0x44); + tp2803_write_register(0, 0x24, 0x86); + tp2803_write_register(0, 0x25, 0x40); + tp2803_write_register(0, 0x26, 0x00); + tp2803_write_register(0, 0x27, 0x56); + tp2803_write_register(0, 0x28, 0x00); + tp2803_write_register(0, 0x29, 0x34); + tp2803_write_register(0, 0x2A, 0x19); + tp2803_write_register(0, 0x2B, 0x5e); + tp2803_write_register(0, 0x2C, 0x60); + tp2803_write_register(0, 0x2D, 0x00); + tp2803_write_register(0, 0x2E, 0x00); + tp2803_write_register(0, 0x2F, 0x00); + tp2803_write_register(0, 0x30, 0x01); + tp2803_write_register(0, 0x31, 0x00); + tp2803_write_register(0, 0x32, 0x00); + tp2803_write_register(0, 0x33, 0x00); + tp2803_write_register(0, 0x34, 0x00); + tp2803_write_register(0, 0x35, 0x00); + tp2803_write_register(0, 0x36, 0x00); + tp2803_write_register(0, 0x37, 0x00); + tp2803_write_register(0, 0x38, 0x00); + tp2803_write_register(0, 0x39, 0x00); + tp2803_write_register(0, 0x3A, 0x00); + tp2803_write_register(0, 0x3B, 0x90); + tp2803_write_register(0, 0x3C, 0x10); + tp2803_write_register(0, 0x3D, 0x80); + tp2803_write_register(0, 0x3E, 0x18); + tp2803_write_register(0, 0x3F, 0x00); + tp2803_write_register(0, 0x45, 0x41); + tp2803_write_register(0, 0xF0, 0x00); + tp2803_write_register(0, 0xF1, 0x08); + tp2803_write_register(0, 0xF2, 0x1e); + tp2803_write_register(0, 0xF3, 0x4a); + tp2803_write_register(0, 0xF4, 0x41); + tp2803_write_register(0, 0xF5, 0x00); + + //AHD 720P 30FPS + // tp2803_write_register(0, 0xFF, 0x00); + // tp2803_write_register(0, 0x00, 0x00); + // tp2803_write_register(0, 0x01, 0x00); + // tp2803_write_register(0, 0x02, 0xCB); + // tp2803_write_register(0, 0x03, 0x62); + // tp2803_write_register(0, 0x04, 0x00); + // tp2803_write_register(0, 0x05, 0x6C); + // tp2803_write_register(0, 0x06, 0x00); + // tp2803_write_register(0, 0x07, 0xC1); + // tp2803_write_register(0, 0x08, 0x76); + // tp2803_write_register(0, 0x09, 0x76); + // tp2803_write_register(0, 0x0A, 0x76); + // tp2803_write_register(0, 0x0B, 0x00); + // tp2803_write_register(0, 0x0C, 0x04); + // tp2803_write_register(0, 0x0D, 0xF0); + // tp2803_write_register(0, 0x0E, 0x82); + // tp2803_write_register(0, 0x0F, 0x40); + // tp2803_write_register(0, 0x10, 0x06); + // tp2803_write_register(0, 0x11, 0x3E); + // tp2803_write_register(0, 0x12, 0x00); + // tp2803_write_register(0, 0x13, 0x3C); + // tp2803_write_register(0, 0x14, 0x38); + // tp2803_write_register(0, 0x15, 0x39); + // tp2803_write_register(0, 0x16, 0xEB); + // tp2803_write_register(0, 0x17, 0x10); + // tp2803_write_register(0, 0x18, 0x10); + // tp2803_write_register(0, 0x19, 0xF0); + // tp2803_write_register(0, 0x1A, 0x10); + // tp2803_write_register(0, 0x1B, 0xA4); + // tp2803_write_register(0, 0x1C, 0x55); + // tp2803_write_register(0, 0x1D, 0x76); + // tp2803_write_register(0, 0x1E, 0x80); + // tp2803_write_register(0, 0x1F, 0x00); + // tp2803_write_register(0, 0x20, 0x28); + // tp2803_write_register(0, 0x21, 0xAE); + // tp2803_write_register(0, 0x22, 0x14); + // tp2803_write_register(0, 0x23, 0x7A); + // tp2803_write_register(0, 0x24, 0x86); + // tp2803_write_register(0, 0x25, 0x40); + // tp2803_write_register(0, 0x26, 0x00); + // tp2803_write_register(0, 0x27, 0x56); + // tp2803_write_register(0, 0x28, 0x00); + // tp2803_write_register(0, 0x29, 0x34); + // tp2803_write_register(0, 0x2A, 0x19); + // tp2803_write_register(0, 0x2B, 0x5e); + // tp2803_write_register(0, 0x2C, 0x60); + // tp2803_write_register(0, 0x2D, 0x00); + // tp2803_write_register(0, 0x2E, 0x00); + // tp2803_write_register(0, 0x2F, 0x00); + // tp2803_write_register(0, 0x30, 0x01); + // tp2803_write_register(0, 0x31, 0x00); + // tp2803_write_register(0, 0x32, 0x00); + // tp2803_write_register(0, 0x33, 0x00); + // tp2803_write_register(0, 0x34, 0x00); + // tp2803_write_register(0, 0x35, 0x00); + // tp2803_write_register(0, 0x36, 0x00); + // tp2803_write_register(0, 0x37, 0x00); + // tp2803_write_register(0, 0x38, 0x00); + // tp2803_write_register(0, 0x39, 0x00); + // tp2803_write_register(0, 0x3A, 0x00); + // tp2803_write_register(0, 0x3B, 0xD0); + // tp2803_write_register(0, 0x3C, 0x10); + // tp2803_write_register(0, 0x3D, 0x80); + // tp2803_write_register(0, 0x3E, 0x18); + // tp2803_write_register(0, 0x3F, 0x00); + // tp2803_write_register(0, 0x45, 0x40); + // tp2803_write_register(0, 0xF0, 0x00); + // tp2803_write_register(0, 0xF1, 0x08); + // tp2803_write_register(0, 0xF2, 0x1e); + // tp2803_write_register(0, 0xF3, 0x4a); + // tp2803_write_register(0, 0xF4, 0x41); + // tp2803_write_register(0, 0xF5, 0x00); +} + +int main(int argc, char *argv[]) +{ + UNUSED(argc); + UNUSED(argv); + + CVI_S32 s32Ret = CVI_FAILURE; + + signal(SIGINT, SAMPLE_VIO_HandleSig); + signal(SIGTERM, SAMPLE_VIO_HandleSig); + + s32Ret = SAMPLE_VIO(); + if (s32Ret == CVI_SUCCESS){ + SAMPLE_PRT("sample_vio exit success!\n"); + }else{ + SAMPLE_PRT("sample_vio exit abnormally!\n"); + return s32Ret; + } + + //output tp2803 mclk + SNS_MCLK_S mclk; + mclk.u8Cam = 0; + mclk.enFreq = MCLK_FREQ_27M; + CVI_MIPI_SetSnsMclk(&mclk); + + //gpio reset + tp2803_gpio_init(0); + + //i2c init + tp2803_i2c_init(0, tp2803_master_i2c_addr); + + // check sensor chip id + if (tp2803_read_register(0, 0xfe) != 0x29 || + tp2803_read_register(0, 0xff) != 0x12) + { + printf("read tp2803 chip id fail\n"); + return CVI_FAILURE; + } + + //tp2803 mode init + tp2803_reg_init(); + + while(1) + { + usleep(1000 * 1000); + } + + return s32Ret; +} \ No newline at end of file