Demo/Linux_Drivers
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

middleware: remains commit d1d59d9af

Browse Source
This commit is contained in:
carbon
2023-12-22 16:54:29 +08:00
parent c7a79bfac0
commit e6b5f43553
619 changed files with 4873 additions and 56059 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
middleware/v2/include/linux/cvi_comm_vdec.h
View File

@ -115,7 +115,6 @@ extern vdec_dbg vdecDbg;
CVI_TRACE(level, CVI_ID_VDEC, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#else
#ifndef VC_DEBUG_BASIC_LEVEL
#define CVI_VDEC_PRNT(msg, ...) \
pr_info(msg, ##__VA_ARGS__)
@ -162,26 +161,7 @@ extern vdec_dbg vdecDbg;
#define CVI_TRACE_VDEC(level, fmt, ...) \
CVI_TRACE(level, CVI_ID_VDEC, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#else
#define CVI_VDEC_PRNT(msg, ...)
#define CVI_VDEC_ERR(msg, ...) \
do { \
if (vdecDbg.currMask & CVI_VDEC_MASK_ERR) \
pr_err("[ERR] %s = %d, "msg, __func__, __LINE__, ## __VA_ARGS__); \
} while (0)
#define CVI_VDEC_WARN(msg, ...) \
do { \
if (vdecDbg.currMask & CVI_VDEC_MASK_WARN) \
pr_warn("[WARN] %s = %d, "msg, __func__, __LINE__, ## __VA_ARGS__); \
} while (0)
#define CVI_VDEC_DISP(msg, ...)
#define CVI_VDEC_INFO(msg, ...)
#define CVI_VDEC_MEM(msg, ...)
#define CVI_VDEC_API(msg, ...)
#define CVI_VDEC_TRACE(msg, ...)
#define CVI_VDEC_PERF(msg, ...)
#define CVI_TRACE_VDEC(level, fmt, ...)
#endif
#endif
#define CVI_IO_BLOCK CVI_TRUE

61
middleware/v2/include/linux/cvi_comm_venc.h
View File

@ -196,7 +196,7 @@ extern pthread_t gs_VencTask[VENC_MAX_CHN_NUM];
CVI_TRACE(level, CVI_ID_VENC, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#else
#ifndef VC_DEBUG_BASIC_LEVEL
#define CVI_VENC_DEBUG(msg, ...) \
do { \
if (vencDbg.currMask & CVI_VENC_MASK_DEBUG) { \
@ -295,45 +295,6 @@ extern pthread_t gs_VencTask[VENC_MAX_CHN_NUM];
#define CVI_TRACE_VENC(level, fmt, ...) \
pr_debug("%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
#else
#define CVI_VENC_DEBUG(msg, ...) \
do { \
if (vencDbg.currMask & CVI_VENC_MASK_DEBUG) { \
struct timespec64 ts; \
ktime_get_ts64(&ts); \
pr_info("[DEBUG][%llu] %s = %d," msg, ts.tv_sec * 1000 + ts.tv_nsec / 1000000, __func__, \
__LINE__, ## __VA_ARGS__); \
} \
} while (0)
#define CVI_VENC_ERR(msg, ...) \
do { \
if (vencDbg.currMask & CVI_VENC_MASK_ERR) \
pr_err("[ERR] %s = %d, "msg, __func__, __LINE__, ## __VA_ARGS__); \
} while (0)
#define CVI_VENC_WARN(msg, ...) \
do { \
if (vencDbg.currMask & CVI_VENC_MASK_WARN) \
pr_warn("[WARN] %s = %d, "msg, __func__, __LINE__, ## __VA_ARGS__); \
} while (0)
#define CVI_VENC_BS(msg, ...)
#define CVI_VENC_SRC(msg, ...)
#define CVI_VENC_PERF(msg, ...)
#define CVI_VENC_CFG(msg, ...)
#define CVI_VENC_FRC(msg, ...)
#define CVI_VENC_BIND(msg, ...)
#define CVI_VENC_INFO(msg, ...)
#define CVI_VENC_FLOW(msg, ...)
#define CVI_VENC_API(msg, ...)
#define CVI_VENC_DBG(msg, ...)
#define CVI_VENC_SYNC(msg, ...)
#define CVI_VENC_TRACE(msg, ...)
#define CVI_VENC_DUMP_YUV(msg, ...)
#define CVI_VENC_DUMP_BS(msg, ...)
#define CVI_TRACE_VENC(level, fmt, ...)
#endif
#endif
// TODO: refinememt for hardcode
@ -1305,6 +1266,26 @@ typedef struct _VENC_FRAME_PARAM_S {
CVI_U32 u32FrameBits;
} VENC_FRAME_PARAM_S;
typedef struct _VENC_SB_Setting_S {
unsigned int codec; // 0x1:h265, 0x2:h264, 0x4:jpeg
CVI_U32 sb_mode;
CVI_U32 sb_size;
CVI_U32 sb_nb;
CVI_U32 y_stride;
CVI_U32 uv_stride;
CVI_U32 src_height;
//pri sb address
CVI_U32 sb_ybase;
CVI_U32 sb_uvbase;
CVI_U32 src_ybase; //[out]
CVI_U32 src_uvbase; //[out]
// sec sb address
CVI_U32 sb_ybase1;
CVI_U32 sb_uvbase1;
CVI_U32 src_ybase1; //[out]
CVI_U32 src_uvbase1; //[out]
} VENC_SB_Setting;
#ifdef __cplusplus
#if __cplusplus
}

6
middleware/v2/include/linux/cvi_comm_vi.h
View File

@ -358,12 +358,6 @@ typedef struct _VI_DEV_ATTR_S {
CVI_U32 chn_num; /* R; total chnannels sended from dev */
CVI_U32 snrFps; /* R; snr init fps from isp pub attr */
CVI_BOOL isMux; /* multi sensor use same dev*/
CVI_U32 switchGpioPin; /*switch pin*/
CVI_U8 switchGPioPol; /*switch pol*/
} VI_DEV_ATTR_S;
/* Information of pipe binded to device */

107
middleware/v2/include/linux/cvi_comm_vo.h
View File

@ -34,13 +34,10 @@ extern "C" {
#define VO_INTF_MIPI_SLAVE (0x01L << 14)
#define VO_INTF_HDMI (0x01L << 15)
#define VO_INTF_I80 (0x01L << 16)
#define VO_INTF_LVDS (0x01L << 17)
#define VO_INTF_HW_MCU (0x01L << 18)
#define VO_GAMMA_NODENUM 65
#define MAX_VO_PINS 32
#define MAX_MCU_INSTR 256
#define MAX_BT_PINS 20
typedef CVI_U32 VO_INTF_TYPE_E;
@ -99,20 +96,6 @@ typedef enum _VO_CSC_MATRIX_E {
VO_CSC_MATRIX_BUTT
} VO_CSC_MATRIX_E;
enum VO_PATTERN_MODE {
VO_PAT_OFF = 0,
VO_PAT_SNOW,
VO_PAT_AUTO,
VO_PAT_RED,
VO_PAT_GREEN,
VO_PAT_BLUE,
VO_PAT_COLORBAR,
VO_PAT_GRAY_GRAD_H,
VO_PAT_GRAY_GRAD_V,
VO_PAT_BLACK,
VO_PAT_MAX,
};
typedef enum _VO_I80_FORMAT {
VO_I80_FORMAT_RGB444 = 0,
VO_I80_FORMAT_RGB565,
@ -160,8 +143,7 @@ GPIOA_16, GPIOA_17, GPIOA_18, GPIOA_19, GPIOA_20,
GPIOA_21, GPIOA_22, GPIOA_23, GPIOA_24, GPIOA_25,
GPIOA_26, GPIOA_27, GPIOA_28, GPIOA_29, GPIOA_30,
GPIOA_31,
#if 1
// #ifdef ARCH_CV182X
#ifdef ARCH_CV182X
GPIOE_00 = 380,
GPIOE_01, GPIOE_02, GPIOE_03, GPIOE_04, GPIOE_05,
GPIOE_06, GPIOE_07, GPIOE_08, GPIOE_09, GPIOE_10,
@ -292,18 +274,14 @@ struct VO_LVDS_CTL_PIN_S {
/* Define LVDS's config
*
* out_bits: 6 bit, 8 bit or 10 bit
* mode: LVDS_MODE_VESA for VESA mode; LVDS_MODE_JEIDA for JEIDA mode
* chn_num: 2 for dual link, 1 and others for single link
* lvds_vesa_mode: true for VESA mode; false for JEIDA mode
* data_big_endian: true for big endian; true for little endian
* lane_id: lane mapping, -1 no used
* lane_pn_swap: lane pn-swap if true
* pixelclock: pixel clock
*/
typedef struct _VO_LVDS_ATTR_S {
enum VO_LVDS_OUT_BIT_E out_bits;
enum VO_LVDS_MODE_E mode;
CVI_U8 chn_num;
uint8_t chn_num;
CVI_BOOL data_big_endian;
enum VO_LVDS_LANE_ID lane_id[VO_LVDS_LANE_MAX];
CVI_BOOL lane_pn_swap[VO_LVDS_LANE_MAX];
@ -313,7 +291,7 @@ typedef struct _VO_LVDS_ATTR_S {
enum VO_LVDS_MODE_E lvds_vesa_mode;
} VO_LVDS_ATTR_S;
enum VO_TOP_BT_MUX {
enum VO_TOP_MUX {
VO_MUX_BT_VS = 0,
VO_MUX_BT_HS,
VO_MUX_BT_HDE,
@ -335,24 +313,7 @@ enum VO_TOP_BT_MUX {
VO_MUX_BT_DATA15,
VO_MUX_TG_HS_TILE = 30,
VO_MUX_TG_VS_TILE,
VO_MUX_BT_CLK,
VO_BT_MUX_MAX,
};
enum VO_TOP_MCU_MUX {
VO_MUX_MCU_CS = 0,
VO_MUX_MCU_RS,
VO_MUX_MCU_WR,
VO_MUX_MCU_RD,
VO_MUX_MCU_DATA0,
VO_MUX_MCU_DATA1,
VO_MUX_MCU_DATA2,
VO_MUX_MCU_DATA3,
VO_MUX_MCU_DATA4,
VO_MUX_MCU_DATA5,
VO_MUX_MCU_DATA6,
VO_MUX_MCU_DATA7,
VO_MCU_MUX_MAX,
VO_MUX_MAX,
};
enum VO_TOP_SEL {
@ -425,41 +386,42 @@ enum VO_TOP_D_SEL {
struct VO_D_REMAP {
enum VO_TOP_D_SEL sel;
CVI_U32 mux;
enum VO_TOP_MUX mux;
};
struct VO_PINMUX {
struct VO_BT_PINS {
unsigned char pin_num;
struct VO_D_REMAP d_pins[MAX_VO_PINS];
struct VO_D_REMAP d_pins[MAX_BT_PINS];
};
enum VO_BT_MODE {
VO_BT_MODE_656 = 0,
VO_BT_MODE_1120,
VO_BT_MODE_601,
VO_BT_MODE_MAX,
};
enum VO_BT_CLK_MODE {
VO_BT_CLK_MODE_27M = 0,
VO_BT_CLK_MODE_36M,
VO_BT_CLK_MODE_37P125M,
VO_BT_CLK_MODE_72M,
VO_BT_CLK_MODE_74P25M,
VO_BT_CLK_MODE_148P5M,
};
/* Define BT's config
*
* bt_clk: bt clk sel
* mode: bt mode
* pins: bt pinmux cfg
*/
typedef struct _VO_BT_ATTR_S {
struct VO_PINMUX pins;
enum VO_BT_CLK_MODE bt_clk;
enum VO_BT_MODE mode;
struct VO_BT_PINS pins;
} VO_BT_ATTR_S;
enum VO_MCU_MODE {
VO_MCU_MODE_RGB565 = 0,
VO_MCU_MODE_RGB888,
VO_MCU_MODE_MAX,
};
struct VO_MCU_INSTRS {
unsigned char instr_num;
VO_I80_INSTR_S instr_cmd[MAX_MCU_INSTR];
};
typedef struct _VO_HW_MCU_CFG_S {
enum VO_MCU_MODE mode;
struct VO_PINMUX pins;
CVI_U32 lcd_power_gpio_num;
CVI_S8 lcd_power_avtive;
CVI_U32 backlight_gpio_num;
CVI_S8 backlight_avtive;
CVI_U32 reset_gpio_num;
CVI_S8 reset_avtive;
struct VO_MCU_INSTRS instrs;
} VO_HW_MCU_CFG_S;
/*
* u32BgColor: Background color of a device, in RGB format.
* enIntfType: Type of a VO interface.
@ -475,7 +437,6 @@ typedef struct _VO_PUB_ATTR_S {
VO_SYNC_INFO_S stSyncInfo;
union {
VO_I80_CFG_S sti80Cfg;
VO_HW_MCU_CFG_S stMcuCfg;
VO_LVDS_ATTR_S stLvdsAttr;
VO_BT_ATTR_S stBtAttr;
};

8
middleware/v2/include/linux/cvi_defines.h
View File

@ -232,11 +232,9 @@ extern "C" {
* multiplied by VI_MAX_CHN_NUM, because all VI devices
* can't work at mode of 4 channels at the same time.
*/
#define VI_MAX_PHY_DEV_NUM 3
#define VI_MAX_VIR_DEV_NUM 2
#define VI_MAX_DEV_NUM (VI_MAX_PHY_DEV_NUM + VI_MAX_VIR_DEV_NUM)
#define VI_MAX_DEV_NUM 3
#define VI_MAX_PHY_PIPE_NUM 4
#define VI_MAX_VIR_PIPE_NUM 2
#define VI_MAX_VIR_PIPE_NUM 0
#define VI_MAX_PIPE_NUM (VI_MAX_PHY_PIPE_NUM + VI_MAX_VIR_PIPE_NUM)
#define VI_MAX_WDR_NUM 1
@ -337,7 +335,7 @@ extern "C" {
#define VPSS_DEV_0 0
#define VPSS_DEV_1 1
#define VPSS_MAX_GRP_NUM 16
#define VPSS_ONLINE_NUM 5
#define VPSS_ONLINE_NUM 3
#define VPSS_ONLINE_GRP_0 0
#define VPSS_ONLINE_GRP_1 1
#define VPSS_ONLINE_GRP_2 2

8
middleware/v2/include/linux/vb_uapi.h
View File

@ -7,7 +7,6 @@
#define VB_POOL_NAME_LEN (32)
#define VB_COMM_POOL_MAX_CNT (16)
#define VB_POOL_MAX_BLK (64)
enum VB_IOCTL {
VB_IOCTL_SET_CONFIG,
@ -15,7 +14,6 @@ enum VB_IOCTL {
VB_IOCTL_INIT,
VB_IOCTL_EXIT,
VB_IOCTL_CREATE_POOL,
VB_IOCTL_CREATE_EX_POOL,
VB_IOCTL_DESTROY_POOL,
VB_IOCTL_PHYS_TO_HANDLE,
VB_IOCTL_GET_BLK_INFO,
@ -45,12 +43,6 @@ struct cvi_vb_pool_cfg {
__u64 mem_base;
};
struct cvi_vb_pool_ex_cfg {
__u32 blk_cnt;
__u64 au64PhyAddr[VB_POOL_MAX_BLK][3];
__u32 pool_id;
};
/*
* comm_pool_cnt: number of common pools used.
* comm_pool: pool cfg for the pools.

21
middleware/v2/include/linux/vi_tun_cfg.h
View File

@ -21,9 +21,6 @@ enum cvi_isp_raw {
ISP_PRERAW_B,
ISP_PRERAW_C,
ISP_PRERAW_MAX,
ISP_PRERAW_VIRT_A = ISP_PRERAW_MAX,
ISP_PRERAW_VIRT_B,
ISP_PRERAW_VIRT_MAX,
};
enum cvi_isp_chn_num {
@ -1448,20 +1445,20 @@ struct cvi_vip_isp_post_cfg {
};
struct isp_tuning_cfg {
uint64_t fe_addr[ISP_PRERAW_VIRT_MAX];
void *fe_vir[ISP_PRERAW_VIRT_MAX];
uint64_t fe_addr[ISP_PRERAW_MAX];
void *fe_vir[ISP_PRERAW_MAX];
#ifdef __arm__
__u32 fe_padding[ISP_PRERAW_VIRT_MAX];
__u32 fe_padding[ISP_PRERAW_MAX];
#endif
uint64_t be_addr[ISP_PRERAW_VIRT_MAX];
void *be_vir[ISP_PRERAW_VIRT_MAX];
uint64_t be_addr[ISP_PRERAW_MAX];
void *be_vir[ISP_PRERAW_MAX];
#ifdef __arm__
__u32 be_padding[ISP_PRERAW_VIRT_MAX];
__u32 be_padding[ISP_PRERAW_MAX];
#endif
uint64_t post_addr[ISP_PRERAW_VIRT_MAX];
void *post_vir[ISP_PRERAW_VIRT_MAX];
uint64_t post_addr[ISP_PRERAW_MAX];
void *post_vir[ISP_PRERAW_MAX];
#ifdef __arm__
__u32 post_padding[ISP_PRERAW_VIRT_MAX];
__u32 post_padding[ISP_PRERAW_MAX];
#endif
};

6
middleware/v2/include/linux/vi_uapi.h
View File

@ -120,16 +120,10 @@ enum VI_EVENT {
VI_EVENT_BASE,
VI_EVENT_PRE0_SOF,
VI_EVENT_PRE1_SOF,
VI_EVENT_PRE2_SOF,
VI_EVENT_VIRT_PRE3_SOF,
VI_EVENT_PRE0_EOF,
VI_EVENT_PRE1_EOF,
VI_EVENT_PRE2_EOF,
VI_EVENT_VIRT_PRE3_EOF,
VI_EVENT_POST_EOF,
VI_EVENT_POST1_EOF,
VI_EVENT_POST2_EOF,
VI_EVENT_VIRT_POST3_EOF,
VI_EVENT_ISP_PROC_READ,
VI_EVENT_AWB0_DONE,
VI_EVENT_AWB1_DONE,

75
middleware/v2/include/linux/vo_disp.h
View File

@ -5,14 +5,12 @@
#define LANE_MAX_NUM 5
#endif
#define MAX_VO_PINS 32
#define MAX_MCU_INSTR 256
#define MAX_BT_PINS 20
enum cvi_disp_intf {
CVI_VIP_DISP_INTF_DSI = 0,
CVI_VIP_DISP_INTF_BT,
CVI_VIP_DISP_INTF_I80,
CVI_VIP_DISP_INTF_HW_MCU,
CVI_VIP_DISP_INTF_LVDS,
CVI_VIP_DISP_INTF_MAX,
};
@ -58,7 +56,7 @@ struct cvi_lvds_intf_cfg {
__s8 backlight_avtive;
};
enum sclr_top_vo_bt_mux {
enum sclr_top_vo_mux {
SCLR_VO_MUX_BT_VS = 0,
SCLR_VO_MUX_BT_HS,
SCLR_VO_MUX_BT_HDE,
@ -80,24 +78,7 @@ enum sclr_top_vo_bt_mux {
SCLR_VO_MUX_BT_DATA15,
SCLR_VO_MUX_TG_HS_TILE = 30,
SCLR_VO_MUX_TG_VS_TILE,
SCLR_VO_MUX_BT_CLK,
SCLR_VO_BT_MUX_MAX,
};
enum sclr_top_vo_mcu_mux {
SCLR_VO_MUX_MCU_CS = 0,
SCLR_VO_MUX_MCU_RS,
SCLR_VO_MUX_MCU_WR,
SCLR_VO_MUX_MCU_RD,
SCLR_VO_MUX_MCU_DATA0,
SCLR_VO_MUX_MCU_DATA1,
SCLR_VO_MUX_MCU_DATA2,
SCLR_VO_MUX_MCU_DATA3,
SCLR_VO_MUX_MCU_DATA4,
SCLR_VO_MUX_MCU_DATA5,
SCLR_VO_MUX_MCU_DATA6,
SCLR_VO_MUX_MCU_DATA7,
SCLR_VO_MCU_MUX_MAX,
SCLR_VO_MUX_MAX,
};
enum sclr_top_vo_sel {
@ -170,12 +151,12 @@ enum sclr_top_vo_d_sel {
struct vo_d_remap {
enum sclr_top_vo_d_sel sel;
__u32 mux;
enum sclr_top_vo_mux mux;
};
struct vo_pins {
struct bt_pins {
unsigned char pin_num;
struct vo_d_remap d_pins[MAX_VO_PINS];
struct vo_d_remap d_pins[MAX_BT_PINS];
};
enum BT_MODE {
@ -185,43 +166,22 @@ enum BT_MODE {
BT_MODE_MAX,
};
enum BT_CLK_MODE {
BT_CLK_MODE_27M = 0,
BT_CLK_MODE_36M,
BT_CLK_MODE_37P125M,
BT_CLK_MODE_72M,
BT_CLK_MODE_74P25M,
BT_CLK_MODE_148P5M,
};
/*
* @pixelclock: pixel clock in kHz
*/
struct cvi_bt_intf_cfg {
__u32 pixelclock;
__u8 bt_clk;
enum BT_MODE mode;
struct vo_pins pins;
};
struct cvi_i80_instr {
__u8 delay;
__u8 data_type;
__u8 data;
};
enum MCU_MODE {
MCU_MODE_RGB565 = 0,
MCU_MODE_RGB888,
MCU_MODE_MAX,
};
struct MCU_INSTRS {
unsigned char instr_num;
struct cvi_i80_instr instr_cmd[MAX_MCU_INSTR];
};
struct cvi_hw_mcu_intf_cfg {
enum MCU_MODE mode;
struct vo_pins pins;
__u32 lcd_power_gpio_num;
__s8 lcd_power_avtive;
__u32 backlight_gpio_num;
__s8 backlight_avtive;
__u32 reset_gpio_num;
__s8 reset_avtive;
struct MCU_INSTRS instrs;
__u32 pixelclock;
struct bt_pins pins;
};
struct cvi_disp_intf_cfg {
@ -230,7 +190,6 @@ struct cvi_disp_intf_cfg {
struct cvi_dsi_intf_cfg dsi_cfg;
struct cvi_lvds_intf_cfg lvds_cfg;
struct cvi_bt_intf_cfg bt_cfg;
struct cvi_hw_mcu_intf_cfg mcu_cfg;
};
};

2
middleware/v2/include/linux/vpss_uapi.h
View File

@ -223,7 +223,7 @@ struct vpss_scene {
#define CVI_VPSS_SET_CHN_LDC _IOW('S', 0x29, struct vpss_chn_ldc_cfg)
#define CVI_VPSS_GET_CHN_LDC _IOWR('S', 0x2a, struct vpss_chn_ldc_cfg)
#define CVI_VPSS_GET_CHN_FRAME _IOWR('S', 0x2b, struct vpss_chn_frm_cfg)
#define CVI_VPSS_RELEASE_CHN_FRAME _IOWR('S', 0x2c, struct vpss_chn_frm_cfg)
#define CVI_VPSS_RELEASE_CHN_RAME _IOWR('S', 0x2c, struct vpss_chn_frm_cfg)
#define CVI_VPSS_SET_CHN_ALIGN _IOW('S', 0x2d, struct vpss_chn_align_cfg)
#define CVI_VPSS_GET_CHN_ALIGN _IOWR('S', 0x2e, struct vpss_chn_align_cfg)
#define CVI_VPSS_SET_CHN_YRATIO _IOW('S', 0x2f, struct vpss_chn_yratio_cfg)