diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..51d3255a8
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,3 @@
+/install/
+__pycache__
+host-tools
diff --git a/middleware/v2/.gitignore b/middleware/v2/.gitignore
index 988a613e7..28f68f62e 100644
--- a/middleware/v2/.gitignore
+++ b/middleware/v2/.gitignore
@@ -6,6 +6,8 @@
 *.dwo
 
 lib
+ko
+ko_shrink
 bin
 include
 tags
@@ -35,6 +37,7 @@ sample/osdc/sample_osdc
 sample/scene_auto/sample_scene_auto
 sample/sensor_test/sensor_test
 sample/tp2863_tp2803/sample_test_tp2863_tp2803
+sample/sample_panel/sample_panel
 
 self_test/cvi_test/cvi_test
 self_test/cvi_test/res
diff --git a/middleware/v2/component/isp/sensor.mk b/middleware/v2/component/isp/sensor.mk
index 1ce5968a7..b718cc9af 100644
--- a/middleware/v2/component/isp/sensor.mk
+++ b/middleware/v2/component/isp/sensor.mk
@@ -68,6 +68,7 @@ sensor-$(CONFIG_SENSOR_GCORE_GC2145)         += gcore_gc2145
 sensor-$(CONFIG_SENSOR_GCORE_GC4023)         += gcore_gc4023
 sensor-$(CONFIG_SENSOR_GCORE_GC4653)         += gcore_gc4653
 sensor-$(CONFIG_SENSOR_IMGDS_MIS2008)        += imgds_mis2008
+sensor-$(CONFIG_SENSOR_IMGDS_MIS2008_1L)     += imgds_mis2008_1L
 sensor-$(CONFIG_SENSOR_NEXTCHIP_N5)          += nextchip_n5
 sensor-$(CONFIG_SENSOR_NEXTCHIP_N6)          += nextchip_n6
 sensor-$(CONFIG_SENSOR_OV_OS04A10)           += ov_os04a10
diff --git a/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos.c b/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos.c
index 8430e0493..611301b24 100644
--- a/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos.c
+++ b/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos.c
@@ -66,44 +66,60 @@ static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
 static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
 static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
 /*****CV4001 Lines Range*****/
-#define CV4001_FULL_LINES_MAX  (0xfffff)
+#define CV4001_FULL_LINES_MAX  (0xfffff / 2)//liner mode: vts_reg value is double real_vts
+#define CV4001_FULL_LINES_MAX_2TO1_WDR  (0xfffff / 4)//wdr mode: four
 
 /*****CV4001 Register Address*****/
-#define CV4001_EXP_ADDR0			0x3062 //bit[19:16]
-#define CV4001_EXP_ADDR1			0x3061
-#define CV4001_EXP_ADDR2			0x3060
+#define CV4001_EXP1_ADDR0			0x3062 //bit[19:16]
+#define CV4001_EXP1_ADDR1			0x3061
+#define CV4001_EXP1_ADDR2			0x3060
+#define CV4001_EXP2_ADDR0			0x3066
+#define CV4001_EXP2_ADDR1			0x3065
+#define CV4001_EXP2_ADDR2			0x3064
 
-#define CV4001_AGAIN_ADDR			0x3180 //bit[7:0]
+#define CV4001_AGAIN1_ADDR			0x3180 //bit[7:0]
+#define CV4001_AGAIN2_ADDR			0x3181 //bit[7:0]
 
-#define CV4001_DGAIN_H_ADDR			0x3179 //bit[15:8]
-#define CV4001_DGAIN_L_ADDR			0x3178 //bit[7:0]
+#define CV4001_DGAIN1_H_ADDR		0x3179 //bit[15:8]
+#define CV4001_DGAIN1_L_ADDR		0x3178 //bit[7:0]
+#define CV4001_DGAIN2_H_ADDR		0x317B //bit[15:8]
+#define CV4001_DGAIN2_L_ADDR		0x317A //bit[7:0]
 
 #define CV4001_VTS_ADDR0			0x302A //bit[19:16]
 #define CV4001_VTS_ADDR1			0x3029
 #define CV4001_VTS_ADDR2			0x3028
 
-#define CV4001_FLIP_MIRROR_ADDR			0x3034
+#define CV4001_FLIP_MIRROR_ADDR		0x3034
 
-#define CV4001_RES_IS_1440P(w, h)      ((w) <= 2560 && (h) <= 1440)
+#define CV4001_RES_IS_1440P(w, h)      ((w) == 2560 && (h) == 1440)
 
 static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
 {
+	const CV4001_MODE_S *pstMode;
+
+	CVI_U32 FpsMax;
 	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
 
 	CMOS_CHECK_POINTER(pstAeSnsDft);
 	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
 	CMOS_CHECK_POINTER(pstSnsState);
 
+	pstMode = &g_astCV4001_mode[pstSnsState->u8ImgMode];
+	FpsMax = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MaxFps;
+
 	pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
 	pstAeSnsDft->u32FlickerFreq = 50 * 256;
-	pstAeSnsDft->u32FullLinesMax = CV4001_FULL_LINES_MAX;
-	pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 25);
+	pstAeSnsDft->u32FullLinesMax = (pstSnsState->enWDRMode == WDR_MODE_NONE) ?
+			CV4001_FULL_LINES_MAX : CV4001_FULL_LINES_MAX_2TO1_WDR;
+	pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * FpsMax);
 
 	pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
 	pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
 	pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
+
 	pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
 	pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
+
 	pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
 	pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
 
@@ -112,27 +128,32 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
 	pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
 
 	if (g_au32LinesPer500ms[ViPipe] == 0)
-		pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 25 / 2;
+		pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * FpsMax / 2;
 	else
 		pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
 
 	switch (pstSnsState->enWDRMode) {
 	default:
 	case WDR_MODE_NONE:   /*linear mode*/
-		pstAeSnsDft->f32Fps = g_astCV4001_mode[CV4001_MODE_2560X1440P25].f32MaxFps;
-		pstAeSnsDft->f32MinFps = g_astCV4001_mode[CV4001_MODE_2560X1440P25].f32MinFps;
+		pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
+		pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
 		pstAeSnsDft->au8HistThresh[0] = 0xd;
 		pstAeSnsDft->au8HistThresh[1] = 0x28;
 		pstAeSnsDft->au8HistThresh[2] = 0x60;
 		pstAeSnsDft->au8HistThresh[3] = 0x80;
 
-		pstAeSnsDft->u32MaxAgain = 16384;
-		pstAeSnsDft->u32MinAgain = 1024;
+		pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
+		pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
+		pstAeSnsDft->u32MaxIntTimeTarget = 65535;
+		pstAeSnsDft->u32MinIntTimeTarget = 1;
+
+		pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max;
+		pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min;
 		pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
 		pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
 
-		pstAeSnsDft->u32MaxDgain = 16384;
-		pstAeSnsDft->u32MinDgain = 1024;
+		pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max;
+		pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Max;
 		pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
 		pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
 
@@ -142,14 +163,52 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
 		pstAeSnsDft->u32AEResponseFrame = 4;
 		pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
 		pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
-			g_au32InitExposure[ViPipe] : g_astCV4001_mode[CV4001_MODE_2560X1440P25].stExp[0].u16Def;
+			g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def;
 
-		pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
-		pstAeSnsDft->u32MinIntTime = g_astCV4001_mode[CV4001_MODE_2560X1440P25].stExp[0].u16Min;
+		break;
+
+	case WDR_MODE_2To1_LINE:
+		pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
+		pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
+		pstAeSnsDft->au8HistThresh[0] = 0xC;
+		pstAeSnsDft->au8HistThresh[1] = 0x18;
+		pstAeSnsDft->au8HistThresh[2] = 0x60;
+		pstAeSnsDft->au8HistThresh[3] = 0x80;
+
+		pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
+		pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
 		pstAeSnsDft->u32MaxIntTimeTarget = 65535;
 		pstAeSnsDft->u32MinIntTimeTarget = 1;
+
+		pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max;
+		pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min;
+		pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
+		pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
+
+		pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max;
+		pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Min;
+		pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
+		pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
+		pstAeSnsDft->u32MaxISPDgainTarget = 16 << pstAeSnsDft->u32ISPDgainShift;
+
+		pstAeSnsDft->u32InitAESpeed = 64;
+		pstAeSnsDft->u32InitAETolerance = 5;
+		pstAeSnsDft->u32AEResponseFrame = 4;
+		pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
+			g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def;
+
+		if (genFSWDRMode[ViPipe] == ISP_FSWDR_LONG_FRAME_MODE) {
+			pstAeSnsDft->u8AeCompensation = 64;
+			pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
+		} else {
+			pstAeSnsDft->u8AeCompensation = 40;
+			pstAeSnsDft->enAeExpMode = AE_EXP_LOWLIGHT_PRIOR;
+		}
+
 		break;
 	}
+	CVI_TRACE_SNS(CVI_DBG_INFO, "again[%d, %d], dgain[%d, %d]\n",
+		pstAeSnsDft->u32MinAgain, pstAeSnsDft->u32MaxAgain, pstAeSnsDft->u32MinDgain, pstAeSnsDft->u32MaxDgain);
 
 	return CVI_SUCCESS;
 }
@@ -168,27 +227,37 @@ static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_
 	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
 	CMOS_CHECK_POINTER(pstSnsState);
 
-	u32Vts = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
 	pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
+	u32Vts = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
 	f32MaxFps = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MaxFps;
 	f32MinFps = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MinFps;
 
-	if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
-		u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
-	} else {
-		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
-		return CVI_FAILURE;
-	}
-
-	u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX) ? CV4001_FULL_LINES_MAX : u32VMAX;
-
 	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
-		pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = ((u32VMAX & 0xFF0000) >> 16);
-		pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = ((u32VMAX & 0xFF00) >> 8);
-		pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = (u32VMAX & 0xFF);
+		if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
+			u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
+		} else {
+			CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
+			return CVI_FAILURE;
+		}
+
+		u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX) ?
+				CV4001_FULL_LINES_MAX : u32VMAX;
+		pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = (((u32VMAX * 2) & 0xFF0000) >> 16);
+		pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = (((u32VMAX * 2) & 0xFF00) >> 8);
+		pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = ((u32VMAX * 2) & 0xFF);
 	} else {
-		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
-		return CVI_FAILURE;
+		if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
+			u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
+		} else {
+			CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
+			return CVI_FAILURE;
+		}
+
+		u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX_2TO1_WDR) ?
+				CV4001_FULL_LINES_MAX_2TO1_WDR : u32VMAX;
+		pstSnsRegsInfo->astI2cData[WDR2_VTS_0].u32Data = (((u32VMAX * 4) & 0xFF0000) >> 16);
+		pstSnsRegsInfo->astI2cData[WDR2_VTS_1].u32Data = (((u32VMAX * 4) & 0xFF00) >> 8);
+		pstSnsRegsInfo->astI2cData[WDR2_VTS_2].u32Data = ((u32VMAX * 4) & 0xFF);
 	}
 
 	pstSnsState->u32FLStd = u32VMAX;
@@ -209,20 +278,37 @@ static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
 {
 	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
 	ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
-	CVI_S32 Cur_Vts;
-	CVI_S32 Reg_IntTime;
+	CVI_S32 Reg_IntTime1;
+	CVI_S32 Reg_IntTime2;
 
 	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
 	CMOS_CHECK_POINTER(pstSnsState);
 	CMOS_CHECK_POINTER(u32IntTime);
-
-	Cur_Vts = pstSnsState->u32FLStd;
-	Reg_IntTime = ((Cur_Vts / 2) - u32IntTime[0]) * 2;
-
 	pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
-	pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime >> 16) & 0x0F);
-	pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime >> 8) & 0xFF);
-	pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime & 0xFF);
+
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
+		Reg_IntTime1 = (pstSnsState->u32FLStd  - u32IntTime[0]) * 2;
+
+		pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F);
+		pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF);
+		pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime1 & 0xFF);
+	} else {
+		/* short exposure */
+		pstSnsState->au32WDRIntTime[0] = u32IntTime[0];//?
+		/* long exposure */
+		pstSnsState->au32WDRIntTime[1] = u32IntTime[1];
+
+		Reg_IntTime1 = (pstSnsState->u32FLStd  - u32IntTime[1]) * 4;//u32IntTime[1] long exposure
+		Reg_IntTime2 = (pstSnsState->u32FLStd  - u32IntTime[0]) * 4 + 2;//u32IntTime[0] short exposure
+
+		pstSnsRegsInfo->astI2cData[WDR2_EXP1_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F);
+		pstSnsRegsInfo->astI2cData[WDR2_EXP1_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF);
+		pstSnsRegsInfo->astI2cData[WDR2_EXP1_2].u32Data = (Reg_IntTime1 & 0xFF);
+
+		pstSnsRegsInfo->astI2cData[WDR2_EXP2_0].u32Data = ((Reg_IntTime2 >> 16) & 0x0F);
+		pstSnsRegsInfo->astI2cData[WDR2_EXP2_1].u32Data = ((Reg_IntTime2 >> 8) & 0xFF);
+		pstSnsRegsInfo->astI2cData[WDR2_EXP2_2].u32Data = (Reg_IntTime2 & 0xFF);
+	}
 
 	return CVI_SUCCESS;
 }
@@ -340,8 +426,13 @@ static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu
 		pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 8);
 		pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0xFF);
 	} else {
-		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
-		return CVI_FAILURE;
+		pstSnsRegsInfo->astI2cData[WDR2_AGAIN1].u32Data = u32Again;
+		pstSnsRegsInfo->astI2cData[WDR2_AGAIN2].u32Data = u32Again;
+
+		pstSnsRegsInfo->astI2cData[WDR2_DGAIN1_H].u32Data = (u32Dgain >> 8);
+		pstSnsRegsInfo->astI2cData[WDR2_DGAIN1_L].u32Data = (u32Dgain & 0xFF);
+		pstSnsRegsInfo->astI2cData[WDR2_DGAIN2_H].u32Data = (u32Dgain >> 8);
+		pstSnsRegsInfo->astI2cData[WDR2_DGAIN2_L].u32Data = (u32Dgain & 0xFF);
 	}
 	return CVI_SUCCESS;
 }
@@ -349,14 +440,62 @@ static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu
 static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
 				    CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
 {
-	UNUSED(ViPipe);
-	UNUSED(u16ManRatioEnable);
-	UNUSED(au32Ratio);
-	UNUSED(au32IntTimeMax);
-	UNUSED(au32IntTimeMin);
-	UNUSED(pu32LFMaxIntTime);
+	CVI_U32 u32IntTimeMaxTmp  = 0, u32IntTimeMaxTmp0 = 0;
+	CVI_U32 u32RatioTmp = 0x40;
+	CVI_U32 u32ShortTimeMinLimit = 0;
+	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
+
+	CMOS_CHECK_POINTER(au32Ratio);
+	CMOS_CHECK_POINTER(au32IntTimeMax);
+	CMOS_CHECK_POINTER(au32IntTimeMin);
+	CMOS_CHECK_POINTER(pu32LFMaxIntTime);
+	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
+	CMOS_CHECK_POINTER(pstSnsState);
+
+	u32ShortTimeMinLimit = 1;
+	/*
+	 * Long exp + Short exp < VTS
+	 */
+	u32IntTimeMaxTmp0 = ((pstSnsState->au32FL[1] - 1 - g_astCV4001_mode[pstSnsState->u8ImgMode].u32IspResTime -
+			pstSnsState->au32WDRIntTime[0]) * 0x40) / DIV_0_TO_1(au32Ratio[0]);
+	u32IntTimeMaxTmp  = ((pstSnsState->au32FL[0] - 1 - g_astCV4001_mode[pstSnsState->u8ImgMode].u32IspResTime)
+			* 0x40) / DIV_0_TO_1(au32Ratio[0] + 0x40);
+	u32IntTimeMaxTmp = (u32IntTimeMaxTmp > u32IntTimeMaxTmp0) ? u32IntTimeMaxTmp0 : u32IntTimeMaxTmp;
+	u32IntTimeMaxTmp  = (!u32IntTimeMaxTmp) ? u32ShortTimeMinLimit : u32IntTimeMaxTmp;
+
+	if (u32IntTimeMaxTmp >= u32ShortTimeMinLimit) {
+		if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
+			au32IntTimeMax[0] = u32IntTimeMaxTmp;
+			au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6;
+			au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6;
+			au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6;
+			au32IntTimeMin[0] = u32ShortTimeMinLimit;
+			au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6;
+			au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6;
+			au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6;
+		} else {
+		}
+	} else {
+		if (u16ManRatioEnable) {
+			CVI_TRACE_SNS(CVI_DBG_ERR, "Manaul ExpRatio is too large!\n");
+			return CVI_FAILURE;
+		}
+		u32IntTimeMaxTmp = u32ShortTimeMinLimit;
+
+		if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
+			u32RatioTmp = 0xFFF;
+			au32IntTimeMax[0] = u32IntTimeMaxTmp;
+			au32IntTimeMax[1] = au32IntTimeMax[0] * u32RatioTmp >> 6;
+		} else {
+		}
+		au32IntTimeMin[0] = au32IntTimeMax[0];
+		au32IntTimeMin[1] = au32IntTimeMax[1];
+		au32IntTimeMin[2] = au32IntTimeMax[2];
+		au32IntTimeMin[3] = au32IntTimeMax[3];
+	}
+	CVI_TRACE_SNS(CVI_DBG_DEBUG, "sexp[%d, %d], lexp[%d, %d], ratio:%d\n",
+			au32IntTimeMin[0], au32IntTimeMax[0], au32IntTimeMin[1], au32IntTimeMax[1], au32Ratio[0]);
 
-	CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode\n");
 	return CVI_SUCCESS;
 }
 
@@ -390,8 +529,9 @@ static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
 
 static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
 {
-	CMOS_CHECK_POINTER(pstAwbSnsDft);
 	UNUSED(ViPipe);
+	CMOS_CHECK_POINTER(pstAwbSnsDft);
+
 	memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
 
 	pstAwbSnsDft->u16InitGgain = 1024;
@@ -414,6 +554,7 @@ static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
 static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
 {
 	UNUSED(ViPipe);
+
 	memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
 
 	return CVI_SUCCESS;
@@ -421,12 +562,22 @@ static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
 
 static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
 {
-	CMOS_CHECK_POINTER(pstBlc);
+	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
+
 	UNUSED(ViPipe);
+	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
+	CMOS_CHECK_POINTER(pstSnsState);
+	CMOS_CHECK_POINTER(pstBlc);
+
 	memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
 
-	memcpy(pstBlc,
-		&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE)
+		memcpy(pstBlc,
+			&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
+	else
+		memcpy(pstBlc,
+			&g_stIspBlcCalibratio_wdr, sizeof(ISP_CMOS_BLACK_LEVEL_S));
+
 	return CVI_SUCCESS;
 }
 
@@ -439,11 +590,13 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
 	CMOS_CHECK_POINTER(pstSnsState);
 	pstMode = &g_astCV4001_mode[pstSnsState->u8ImgMode];
 
-	if (pstSnsState->enWDRMode != WDR_MODE_NONE) {
-		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
-	} else {
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
 		pstIspCfg->frm_num = 1;
 		memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
+	} else {
+		pstIspCfg->frm_num = 2;
+		memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
+		memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S));
 	}
 
 	return CVI_SUCCESS;
@@ -451,9 +604,42 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
 
 static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
 {
-	UNUSED(ViPipe);
-	UNUSED(u8Mode);
-	CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
+	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
+
+	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
+	CMOS_CHECK_POINTER(pstSnsState);
+
+	pstSnsState->bSyncInit = CVI_FALSE;
+
+	switch (u8Mode) {
+	case WDR_MODE_NONE:
+		if (pstSnsState->u8ImgMode == CV4001_MODE_2560X1440P15_WDR)
+			pstSnsState->u8ImgMode = CV4001_MODE_2560X1440P25;
+
+		pstSnsState->enWDRMode = WDR_MODE_NONE;
+		pstSnsState->u32FLStd = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
+		syslog(LOG_INFO, "WDR_MODE_NONE\n");
+		break;
+
+	case WDR_MODE_2To1_LINE:
+		if (pstSnsState->u8ImgMode == CV4001_MODE_2560X1440P25) {
+			pstSnsState->u8ImgMode = CV4001_MODE_2560X1440P15_WDR;
+		}
+
+		pstSnsState->enWDRMode = WDR_MODE_2To1_LINE;
+		pstSnsState->u32FLStd = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
+		syslog(LOG_INFO, "WDR_MODE_2To1_LINE 1440p mode(60fps->30fps)\n");
+		break;
+
+	default:
+		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
+		return CVI_FAILURE;
+	}
+
+	pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
+	pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
+	memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
+
 	return CVI_SUCCESS;
 }
 
@@ -505,7 +691,8 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 		pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunCV4001_BusInfo[ViPipe].s8I2cDev;
 		pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
 		pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
-		pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
+		pstCfg0->snsCfg.u32RegNum = (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) ?
+					WDR2_REGS_NUM : LINEAR_REGS_NUM;
 
 		for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
 			pstI2c_data[i].bUpdate = CVI_TRUE;
@@ -514,65 +701,54 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 			pstI2c_data[i].u32DataByteNum = cv4001_data_byte;
 		}
 
-		pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV4001_EXP_ADDR0;
-		pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV4001_EXP_ADDR1;
-		pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV4001_EXP_ADDR2;
-		pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV4001_AGAIN_ADDR;
-		pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV4001_DGAIN_H_ADDR;
-		pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV4001_DGAIN_L_ADDR;
-		pstI2c_data[LINEAR_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
-		pstI2c_data[LINEAR_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
-		pstI2c_data[LINEAR_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
-		pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
-
+		switch (pstSnsState->enWDRMode) {
+		case WDR_MODE_2To1_LINE:
+			pstI2c_data[WDR2_EXP1_0].u32RegAddr = CV4001_EXP1_ADDR0;
+			pstI2c_data[WDR2_EXP1_1].u32RegAddr = CV4001_EXP1_ADDR1;
+			pstI2c_data[WDR2_EXP1_2].u32RegAddr = CV4001_EXP1_ADDR2;
+			pstI2c_data[WDR2_EXP2_0].u32RegAddr = CV4001_EXP2_ADDR0;
+			pstI2c_data[WDR2_EXP2_1].u32RegAddr = CV4001_EXP2_ADDR1;
+			pstI2c_data[WDR2_EXP2_2].u32RegAddr = CV4001_EXP2_ADDR2;
+			pstI2c_data[WDR2_AGAIN1].u32RegAddr = CV4001_AGAIN1_ADDR;
+			pstI2c_data[WDR2_AGAIN2].u32RegAddr = CV4001_AGAIN2_ADDR;
+			pstI2c_data[WDR2_DGAIN1_H].u32RegAddr = CV4001_DGAIN1_H_ADDR;
+			pstI2c_data[WDR2_DGAIN1_L].u32RegAddr = CV4001_DGAIN1_L_ADDR;
+			pstI2c_data[WDR2_DGAIN2_H].u32RegAddr = CV4001_DGAIN2_H_ADDR;
+			pstI2c_data[WDR2_DGAIN2_L].u32RegAddr = CV4001_DGAIN2_L_ADDR;
+			pstI2c_data[WDR2_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
+			pstI2c_data[WDR2_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
+			pstI2c_data[WDR2_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
+			pstI2c_data[WDR2_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
+			break;
+		default:
+			pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV4001_EXP1_ADDR0;
+			pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV4001_EXP1_ADDR1;
+			pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV4001_EXP1_ADDR2;
+			pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV4001_AGAIN1_ADDR;
+			pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV4001_DGAIN1_H_ADDR;
+			pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV4001_DGAIN1_L_ADDR;
+			pstI2c_data[LINEAR_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
+			pstI2c_data[LINEAR_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
+			pstI2c_data[LINEAR_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
+			pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
+			break;
+		}
 		pstSnsState->bSyncInit = CVI_TRUE;
 		pstCfg0->snsCfg.need_update = CVI_TRUE;
 		/* recalcualte WDR size */
 		cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
 		pstCfg0->ispCfg.need_update = CVI_TRUE;
 	} else {
-
-		CVI_U32 gainsUpdate = 0, shutterUpdate = 0, vtsUpdate = 0;
-
 		pstCfg0->snsCfg.need_update = CVI_FALSE;
 		for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
 			if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
 				pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
 			} else {
-
-				if ((i >= LINEAR_AGAIN) && (i <= LINEAR_DGAIN_L)) {
-					gainsUpdate = 1;
-				}
-
-				if (i <= LINEAR_EXP_2) {
-					shutterUpdate = 1;
-				}
-
-				if ((i >= LINEAR_VTS_0) && (i <= LINEAR_VTS_2)) {
-					vtsUpdate = 1;
-				}
-
 				pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
 				pstCfg0->snsCfg.need_update = CVI_TRUE;
 			}
 		}
 
-		if (gainsUpdate) {
-			pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_H].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_L].bUpdate = CVI_TRUE;
-		}
-		if (shutterUpdate) {
-			pstCfg0->snsCfg.astI2cData[LINEAR_EXP_0].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_EXP_1].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_EXP_2].bUpdate = CVI_TRUE;
-		}
-		if (vtsUpdate) {
-			pstCfg0->snsCfg.astI2cData[LINEAR_VTS_0].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_VTS_1].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_VTS_2].bUpdate = CVI_TRUE;
-		}
-
 		/* check update isp crop or not */
 		pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
 				CVI_TRUE : CVI_FALSE);
@@ -582,7 +758,12 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 	memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
 	memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
 	pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
-	pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
+
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
+		pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
+	} else {
+		pstCfg0->snsCfg.astI2cData[WDR2_FLIP_MIRROR].bDropFrm = CVI_FALSE;
+	}
 
 	return CVI_SUCCESS;
 }
@@ -611,6 +792,17 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
 					      pstSnsState->enWDRMode);
 				return CVI_FAILURE;
 			}
+		} else if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
+			if (CV4001_RES_IS_1440P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
+				u8SensorImageMode = CV4001_MODE_2560X1440P15_WDR;
+			} else {
+				CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
+				       pstSensorImageMode->u16Width,
+				       pstSensorImageMode->u16Height,
+				       pstSensorImageMode->f32Fps,
+				       pstSnsState->enWDRMode);
+				return CVI_FAILURE;
+			}
 		} else {
 			CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
 				      pstSensorImageMode->u16Width,
@@ -677,9 +869,17 @@ static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSn
 			return;
 		}
 
-		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
-		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
-		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
+		if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
+			pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
+			pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
+			pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
+		} else {
+			start_x = 0;
+			start_y = 0;
+			pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].u32Data = value;
+			pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].bDropFrm = 1;
+			pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].u8DropFrmNum = 2;
+		}
 		g_aeCV4001_MirrorFip[ViPipe] = eSnsMirrorFlip;
 		pstIspCfg0->img_size[0].stWndRect.s32X = start_x;
 		pstIspCfg0->img_size[0].stWndRect.s32Y = start_y;
@@ -718,8 +918,11 @@ static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
 
 	pstRxAttr->img_size.width = g_astCV4001_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
 	pstRxAttr->img_size.height = g_astCV4001_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
-	if (pstSnsState->enWDRMode == WDR_MODE_NONE)
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
 		pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
+	} else {
+		pstRxAttr->mac_clk = RX_MAC_CLK_400M;
+	}
 
 	return CVI_SUCCESS;
 
diff --git a/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_ex.h
index b133ecfcb..610eec99a 100644
--- a/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_ex.h
+++ b/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_ex.h
@@ -36,8 +36,30 @@ enum cv4001_linear_regs_e {
 	LINEAR_REGS_NUM
 };
 
+enum cv4001_wdr2_regs_e {
+	WDR2_EXP1_0,
+	WDR2_EXP1_1,
+	WDR2_EXP1_2,
+	WDR2_EXP2_0,
+	WDR2_EXP2_1,
+	WDR2_EXP2_2,
+	WDR2_AGAIN1,
+	WDR2_AGAIN2,
+	WDR2_DGAIN1_H,
+	WDR2_DGAIN1_L,
+	WDR2_DGAIN2_H,
+	WDR2_DGAIN2_L,
+	WDR2_VTS_0,
+	WDR2_VTS_1,
+	WDR2_VTS_2,
+	WDR2_FLIP_MIRROR,
+	WDR2_REGS_NUM
+};
+
 typedef enum _CV4001_MODE_E {
 	CV4001_MODE_2560X1440P25 = 0,
+	CV4001_MODE_LINEAR_NUM,
+	CV4001_MODE_2560X1440P15_WDR = CV4001_MODE_LINEAR_NUM,
 	CV4001_MODE_NUM
 } CV4001_MODE_E;
 
@@ -52,6 +74,7 @@ typedef struct _CV4001_MODE_S {
 	CVI_U32 u32HtsDef;
 	CVI_U32 u32VtsDef;
 	SNS_ATTR_S stExp[2];
+	CVI_U32 u32IspResTime;
 	SNS_ATTR_LARGE_S stAgain[2];
 	SNS_ATTR_LARGE_S stDgain[2];
 	char name[64];
diff --git a/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_param.h b/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_param.h
index 62e9187c1..74855f389 100644
--- a/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_param.h
+++ b/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_cmos_param.h
@@ -39,13 +39,13 @@ static const CV4001_MODE_S g_astCV4001_mode[CV4001_MODE_NUM] = {
 			},
 		},
 		.f32MaxFps = 25,
-		.f32MinFps = 0.076, /* 3200 * 25 / 0x0FFFFF  */
-		.u32HtsDef = 743,
-		.u32VtsDef = 3200,
+		.f32MinFps = 0.072, /* 1500 * 25 / (0x0FFFFF / 2)  */
+		.u32HtsDef = 1480,	//hts_reg * 2
+		.u32VtsDef = 1500,	//vts_reg / 2
 		.stExp[0] = {
-			.u16Min = 8,
-			.u16Max = 3200-4,
-			.u16Def = 8,
+			.u16Min = 4,
+			.u16Max = 1500-2,
+			.u16Def = 4,
 			.u16Step = 1,
 		},
 		.stAgain[0] = {
@@ -61,6 +61,81 @@ static const CV4001_MODE_S g_astCV4001_mode[CV4001_MODE_NUM] = {
 			.u32Step = 64,
 		},
 	},
+	[CV4001_MODE_2560X1440P15_WDR] = {
+		.name = "2560X1440P15_WDR",
+		.astImg[0] = {
+			.stSnsSize = {
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+			.stWndRect = {
+				.s32X = 0,
+				.s32Y = 0,
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+			.stMaxSize = {
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+		},
+		.astImg[1] = {
+			.stSnsSize = {
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+			.stWndRect = {
+				.s32X = 0,
+				.s32Y = 0,
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+			.stMaxSize = {
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+		},
+		.f32MaxFps = 15,
+		.f32MinFps = 0.084, /* 1474 * 15 / (0x0FFFFF / 4) */
+		.u32HtsDef = 5088,	//hts_reg * 4
+		.u32VtsDef = 1474,	//vts_reg / 4
+		.stExp[0] = {
+			.u16Min = 4,
+			.u16Max = 1474-1,
+			.u16Def = 4,
+			.u16Step = 1,
+		},
+		.stExp[1] = {
+			.u16Min = 4,
+			.u16Max = 98,
+			.u16Def = 4,
+			.u16Step = 1,
+		},
+		.stAgain[0] = {
+			.u32Min = 1024,
+			.u32Max = 16384,
+			.u32Def = 1024,
+			.u32Step = 1,
+		},
+		.stAgain[1] = {
+			.u32Min = 1024,
+			.u32Max = 16384,
+			.u32Def = 1024,
+			.u32Step = 1,
+		},
+		.stDgain[0] = {
+			.u32Min = 1024,
+			.u32Max = 16384,
+			.u32Def = 1024,
+			.u32Step = 64,
+		},
+		.stDgain[1] = {
+			.u32Min = 1024,
+			.u32Max = 16384,
+			.u32Def = 1024,
+			.u32Step = 64,
+		},
+	}
 };
 
 
@@ -97,6 +172,39 @@ static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
 	},
 };
 
+static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio_wdr = {
+	.bUpdate = CVI_TRUE,
+	.blcAttr = {
+		.Enable = 1,
+		.enOpType = OP_TYPE_AUTO,
+		.stManual = {196, 196, 196, 196, 0, 0, 0, 0
+#ifdef ARCH_CV182X
+			, 1075, 1075, 1075, 1075
+#endif
+		},
+		.stAuto = {
+			{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
+			{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
+			{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
+			{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
+			{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+			{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+			{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+			{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+#ifdef ARCH_CV182X
+			{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
+				1075, 1075},
+			{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
+				1075, 1075},
+			{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
+				1075, 1075},
+			{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
+				1075, 1075},
+#endif
+		},
+	},
+};
+
 struct combo_dev_attr_s cv4001_rx_attr = {
 	.input_mode = INPUT_MODE_MIPI,
 	.mac_clk = RX_MAC_CLK_200M,
@@ -104,7 +212,7 @@ struct combo_dev_attr_s cv4001_rx_attr = {
 		.raw_data_type = RAW_DATA_12BIT,
 		.lane_id = {1, 2, 0, -1, -1},
 		.pn_swap = {1, 1, 1, 0, 0},
-		.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
+		.wdr_mode = CVI_MIPI_WDR_MODE_VC,
 	},
 	.mclk = {
 		.cam = 0,
diff --git a/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_sensor_ctl.c
index af0253489..c6ddd0d7e 100644
--- a/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_sensor_ctl.c
+++ b/middleware/v2/component/isp/sensor/cv180x/cvsens_cv4001/cv4001_sensor_ctl.c
@@ -19,9 +19,10 @@
 
 #define CV4001_CHIP_ID_ADDR_H	0x3003
 #define CV4001_CHIP_ID_ADDR_L	0x3002
-#define CV4001_CHIP_ID		0x4001
+#define CV4001_CHIP_ID			0x4001
 
 static void cv4001_linear_1440p25_init(VI_PIPE ViPipe);
+static void cv4001_wdr_1440p15_2to1_init(VI_PIPE ViPipe);
 
 CVI_U8 cv4001_i2c_addr = 0x35;
 const CVI_U32 cv4001_addr_byte = 2;
@@ -198,9 +199,23 @@ int cv4001_probe(VI_PIPE ViPipe)
 
 void cv4001_init(VI_PIPE ViPipe)
 {
+	WDR_MODE_E        enWDRMode;
+	CVI_U8            u8ImgMode;
+
+	enWDRMode   = g_pastCV4001[ViPipe]->enWDRMode;
+	u8ImgMode   = g_pastCV4001[ViPipe]->u8ImgMode;
+
 	cv4001_i2c_init(ViPipe);
 
-	cv4001_linear_1440p25_init(ViPipe);
+	if (enWDRMode == WDR_MODE_2To1_LINE) {
+		if (u8ImgMode == CV4001_MODE_2560X1440P15_WDR) {
+			cv4001_wdr_1440p15_2to1_init(ViPipe);
+		}
+	} else {
+		if (u8ImgMode == CV4001_MODE_2560X1440P25) {
+			cv4001_linear_1440p25_init(ViPipe);
+		}
+	}
 
 	g_pastCV4001[ViPipe]->bInit = CVI_TRUE;
 }
@@ -292,3 +307,99 @@ static void cv4001_linear_1440p25_init(VI_PIPE ViPipe)
 
 	printf("ViPipe:%d,===CV4001 1440P 25fps 12bit LINEAR Init OK!===\n", ViPipe);
 }
+
+static void cv4001_wdr_1440p15_2to1_init(VI_PIPE ViPipe)
+{
+	cv4001_write_register(ViPipe, 0x3028, 0x08);
+	cv4001_write_register(ViPipe, 0x3029, 0x17);
+	cv4001_write_register(ViPipe, 0x302C, 0xF8);
+	cv4001_write_register(ViPipe, 0x302D, 0x04);
+	cv4001_write_register(ViPipe, 0x3908, 0x4B);
+	cv4001_write_register(ViPipe, 0x3304, 0x01);
+	cv4001_write_register(ViPipe, 0x3305, 0x02);
+	cv4001_write_register(ViPipe, 0x3306, 0x01);
+	cv4001_write_register(ViPipe, 0x343E, 0x00);
+	cv4001_write_register(ViPipe, 0x3401, 0x03);
+	cv4001_write_register(ViPipe, 0x3035, 0x01);
+	cv4001_write_register(ViPipe, 0x3036, 0x01);
+	cv4001_write_register(ViPipe, 0x3020, 0x04);
+	cv4001_write_register(ViPipe, 0x3048, 0x44);
+	cv4001_write_register(ViPipe, 0x3049, 0x00);
+	cv4001_write_register(ViPipe, 0x304A, 0x00);
+	cv4001_write_register(ViPipe, 0x304B, 0x0A);
+	cv4001_write_register(ViPipe, 0x3054, 0x2C);
+	cv4001_write_register(ViPipe, 0x3056, 0xA8);
+	cv4001_write_register(ViPipe, 0x3057, 0x05);
+	cv4001_write_register(ViPipe, 0x3030, 0x05);
+	cv4001_write_register(ViPipe, 0x3060, 0x2C);
+	cv4001_write_register(ViPipe, 0x3064, 0x12);
+	cv4001_write_register(ViPipe, 0x3070, 0x1A);//62
+	cv4001_write_register(ViPipe, 0x3071, 0x00);
+	cv4001_write_register(ViPipe, 0x343C, 0x01);
+	cv4001_write_register(ViPipe, 0x3930, 0x00);
+	cv4001_write_register(ViPipe, 0x3040, 0x01);
+	cv4001_write_register(ViPipe, 0x3044, 0x04);
+	cv4001_write_register(ViPipe, 0x3046, 0xA0);
+	cv4001_write_register(ViPipe, 0x3047, 0x05);
+	cv4001_write_register(ViPipe, 0x362A, 0x00);
+	cv4001_write_register(ViPipe, 0x3625, 0x01);
+	cv4001_write_register(ViPipe, 0x35A4, 0x09);
+	cv4001_write_register(ViPipe, 0x35A8, 0x09);
+	cv4001_write_register(ViPipe, 0x35AE, 0x07);
+	cv4001_write_register(ViPipe, 0x35AF, 0x07);
+	cv4001_write_register(ViPipe, 0x34A2, 0x2C);
+	cv4001_write_register(ViPipe, 0x3416, 0x0F);
+	cv4001_write_register(ViPipe, 0x3418, 0x9F);
+	cv4001_write_register(ViPipe, 0x341A, 0x57);
+	cv4001_write_register(ViPipe, 0x341C, 0x57);
+	cv4001_write_register(ViPipe, 0x341E, 0x6F);
+	cv4001_write_register(ViPipe, 0x341F, 0x01);
+	cv4001_write_register(ViPipe, 0x3420, 0x57);
+	cv4001_write_register(ViPipe, 0x3422, 0x9F);
+	cv4001_write_register(ViPipe, 0x3424, 0x57);
+	cv4001_write_register(ViPipe, 0x3426, 0x8F);
+	cv4001_write_register(ViPipe, 0x3428, 0x47);
+	cv4001_write_register(ViPipe, 0x3348, 0x00);
+	cv4001_write_register(ViPipe, 0x3000, 0x00);
+	cv4001_write_register(ViPipe, 0x3220, 0x03);
+	cv4001_write_register(ViPipe, 0x3347, 0x01);
+	cv4001_write_register(ViPipe, 0x3348, 0x00);
+	cv4001_write_register(ViPipe, 0x3804, 0x0F);
+	cv4001_write_register(ViPipe, 0x3576, 0x06);
+	cv4001_write_register(ViPipe, 0x350F, 0x18);
+	cv4001_write_register(ViPipe, 0x3513, 0x07);
+	cv4001_write_register(ViPipe, 0x3517, 0x07);
+	cv4001_write_register(ViPipe, 0x351A, 0x05);
+	cv4001_write_register(ViPipe, 0x351E, 0x0B);
+	cv4001_write_register(ViPipe, 0x357A, 0x0B);
+	cv4001_write_register(ViPipe, 0x3244, 0x08);
+	cv4001_write_register(ViPipe, 0x3270, 0x60);
+	cv4001_write_register(ViPipe, 0x3271, 0x00);
+	cv4001_write_register(ViPipe, 0x3272, 0x00);
+	cv4001_write_register(ViPipe, 0x3890, 0x01);
+	cv4001_write_register(ViPipe, 0x3894, 0x05);
+	cv4001_write_register(ViPipe, 0x3690, 0x00);
+	cv4001_write_register(ViPipe, 0x3898, 0x20);
+	cv4001_write_register(ViPipe, 0x3899, 0x20);
+	cv4001_write_register(ViPipe, 0x389a, 0x20);
+	cv4001_write_register(ViPipe, 0x389b, 0x20);
+	cv4001_write_register(ViPipe, 0x389c, 0x20);
+	cv4001_write_register(ViPipe, 0x389d, 0x15);
+	cv4001_write_register(ViPipe, 0x389e, 0x05);
+	cv4001_write_register(ViPipe, 0x3583, 0x2f);
+	cv4001_write_register(ViPipe, 0x3b75, 0x00);
+	cv4001_write_register(ViPipe, 0x3b5E, 0x01);
+	cv4001_write_register(ViPipe, 0x3a10, 0x06);
+	cv4001_write_register(ViPipe, 0x3a11, 0x06);
+	cv4001_write_register(ViPipe, 0x316C, 0x64);
+	cv4001_write_register(ViPipe, 0x3162, 0x01);
+	cv4001_write_register(ViPipe, 0x3180, 0x00);
+	cv4001_write_register(ViPipe, 0x3178, 0x40);
+	cv4001_write_register(ViPipe, 0x3179, 0x00);
+
+	cv4001_default_reg_init(ViPipe);
+	delay_ms(100);
+
+	printf("ViPipe:%d,===CV4001 1440P 15fps 12bit WDR2TO1 Init OK!===\n", ViPipe);
+}
+
diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_k06/k06_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/soi_k06/k06_sensor_ctl.c
index d97d23e85..e9b8cd3d8 100644
--- a/middleware/v2/component/isp/sensor/cv180x/soi_k06/k06_sensor_ctl.c
+++ b/middleware/v2/component/isp/sensor/cv180x/soi_k06/k06_sensor_ctl.c
@@ -160,26 +160,36 @@ void k06_default_reg_init(VI_PIPE ViPipe)
 
 void k06_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
 {
-	CVI_U8 val = k06_read_register(ViPipe, 0x12) & (~0x30);
+	CVI_U8 val1 = k06_read_register(ViPipe, 0x12);
+	CVI_U8 val2 = k06_read_register(ViPipe, 0xAA);
+	CVI_U8 val3 = k06_read_register(ViPipe, 0x27);
 
 	switch (eSnsMirrorFlip) {
 	case ISP_SNS_NORMAL:
-		val |= 0x30;
+		val1 = 0x30;
+		val2 = 0x84;
 		break;
 	case ISP_SNS_MIRROR:
-		val |= (0x1 << 4);
+		val1 = 0x10;
+		val2 = 0x8B;
+		val3 += 1;
 		break;
 	case ISP_SNS_FLIP:
-		val |= (0x2 << 4);
+		val1 = 0x20;
+		val2 = 0x84;
 		break;
 	case ISP_SNS_MIRROR_FLIP:
-		val &= ~(0x1 << 4);
+		val1 = 0x00;
+		val2 = 0x8B;
+		val3 += 1;
 		break;
 	default:
 		return;
 	}
 
-	k06_write_register(ViPipe, 0x12, val);
+	k06_write_register(ViPipe, 0x12, val1);
+	k06_write_register(ViPipe, 0xAA, val2);
+	k06_write_register(ViPipe, 0x27, val3);
 }
 
 int k06_probe(VI_PIPE ViPipe)
@@ -235,6 +245,7 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x10, 0x48);
 	k06_write_register(ViPipe, 0x11, 0x80);
 	k06_write_register(ViPipe, 0x46, 0x08);
+	k06_write_register(ViPipe, 0x7F, 0x5E);
 	k06_write_register(ViPipe, 0x0D, 0xA0);
 	k06_write_register(ViPipe, 0x57, 0x67);
 	k06_write_register(ViPipe, 0x58, 0x1F);
@@ -247,10 +258,10 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x24, 0x80);
 	k06_write_register(ViPipe, 0x25, 0xA0);
 	k06_write_register(ViPipe, 0x26, 0x52);
-	k06_write_register(ViPipe, 0x27, 0x27);
+	k06_write_register(ViPipe, 0x27, 0x46);
 	k06_write_register(ViPipe, 0x28, 0x15);
 	k06_write_register(ViPipe, 0x29, 0x04);
-	k06_write_register(ViPipe, 0x2A, 0x20);
+	k06_write_register(ViPipe, 0x2A, 0x40);
 	k06_write_register(ViPipe, 0x2B, 0x14);
 	k06_write_register(ViPipe, 0x2C, 0x00);
 	k06_write_register(ViPipe, 0x2D, 0x00);
@@ -263,36 +274,35 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x77, 0x0C);
 	k06_write_register(ViPipe, 0x80, 0x01);
 	k06_write_register(ViPipe, 0xAF, 0x12);
-	k06_write_register(ViPipe, 0xAA, 0x04);
+	k06_write_register(ViPipe, 0xAA, 0x84);
 	k06_write_register(ViPipe, 0x1D, 0x00);
 	k06_write_register(ViPipe, 0x1E, 0x04);
 	k06_write_register(ViPipe, 0x6C, 0x40);
 	k06_write_register(ViPipe, 0x9E, 0xF8);
-	k06_write_register(ViPipe, 0x0C, 0x30);
-	k06_write_register(ViPipe, 0x6F, 0x80);
+	k06_write_register(ViPipe, 0x0C, 0x00);
 	k06_write_register(ViPipe, 0x6E, 0x2C);
 	k06_write_register(ViPipe, 0x70, 0xF9);
 	k06_write_register(ViPipe, 0x71, 0xDD);
 	k06_write_register(ViPipe, 0x72, 0xD5);
 	k06_write_register(ViPipe, 0x73, 0x5A);
 	k06_write_register(ViPipe, 0x74, 0x02);
-	k06_write_register(ViPipe, 0x78, 0x1D);
+	k06_write_register(ViPipe, 0x78, 0x1C);
 	k06_write_register(ViPipe, 0x89, 0x01);
 	k06_write_register(ViPipe, 0x6B, 0x20);
 	k06_write_register(ViPipe, 0x86, 0x40);
+	k06_write_register(ViPipe, 0x6F, 0x00);
 	k06_write_register(ViPipe, 0x30, 0x8D);
 	k06_write_register(ViPipe, 0x31, 0x08);
 	k06_write_register(ViPipe, 0x32, 0x20);
 	k06_write_register(ViPipe, 0x33, 0x5C);
 	k06_write_register(ViPipe, 0x34, 0x30);
 	k06_write_register(ViPipe, 0x35, 0x30);
-	k06_write_register(ViPipe, 0x3A, 0xB6);
+	k06_write_register(ViPipe, 0x3A, 0xB9);
 	k06_write_register(ViPipe, 0x56, 0x92);
-	k06_write_register(ViPipe, 0x59, 0x48);
+	k06_write_register(ViPipe, 0x59, 0x60);
 	k06_write_register(ViPipe, 0x5A, 0x01);
 	k06_write_register(ViPipe, 0x61, 0x00);
 	k06_write_register(ViPipe, 0x64, 0xC0);
-	k06_write_register(ViPipe, 0x7F, 0x46);
 	k06_write_register(ViPipe, 0x85, 0x44);
 	k06_write_register(ViPipe, 0x8A, 0x00);
 	k06_write_register(ViPipe, 0x91, 0x58);
@@ -317,14 +327,14 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x8F, 0x90);
 	k06_write_register(ViPipe, 0xA4, 0xC7);
 	k06_write_register(ViPipe, 0xA5, 0xAF);
-	k06_write_register(ViPipe, 0xB7, 0x21);
+	k06_write_register(ViPipe, 0xB7, 0x61);
 	k06_write_register(ViPipe, 0x97, 0x20);
 	k06_write_register(ViPipe, 0x13, 0x81);
 	k06_write_register(ViPipe, 0x96, 0x84);
 	k06_write_register(ViPipe, 0x4A, 0x01);
 	k06_write_register(ViPipe, 0x7E, 0x4C);
 	k06_write_register(ViPipe, 0x50, 0x02);
-	k06_write_register(ViPipe, 0x93, 0xC0);
+	k06_write_register(ViPipe, 0x93, 0x00);
 	k06_write_register(ViPipe, 0xB5, 0x4C);
 	k06_write_register(ViPipe, 0xB1, 0x00);
 	k06_write_register(ViPipe, 0xA1, 0x0F);
@@ -340,10 +350,12 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x1B, 0x4F);
 
 	k06_default_reg_init(ViPipe);
-//	k06_write_register(ViPipe, 0x12, 0x00);
+
 	k06_write_register(ViPipe, 0x12, 0x30);
 	k06_write_register(ViPipe, 0x48, 0x86);
 	k06_write_register(ViPipe, 0x48, 0x06);
+	k06_write_register(ViPipe, 0x00, 0x10);
+
 	printf("ViPipe:%d,===K06 1440P 25fps 10bit LINE Init OK!===\n", ViPipe);
 }
 
diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos.c b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos.c
index cd81e2fd9..606f9615b 100644
--- a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos.c
+++ b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos.c
@@ -64,10 +64,11 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
 #define Q03P_FULL_LINES_MAX  (0xFFFF)
 
 /*****Q03P Register Address*****/
-#define Q03P_SHS1_ADDR		0x01
-#define Q03P_GAIN_ADDR		0x00
-#define Q03P_VMAX_ADDR		0x22
-#define Q03P_TABLE_END		0xff
+#define Q03P_SHS1_ADDR			0x01
+#define Q03P_GAIN_ADDR			0x00
+#define Q03P_VMAX_ADDR			0x22
+#define Q03P_FLIP_MIRROR_ADDR	0x12
+#define Q03P_TABLE_END			0xff
 
 #define Q03P_RES_IS_1296P(w, h)      ((w) <= 2304 && (h) <= 1296)
 
@@ -500,6 +501,8 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 			pstI2c_data[LINEAR_VMAX_1_DATA].u32RegAddr = Q03P_VMAX_ADDR + 1;
 			pstI2c_data[LINEAR_VMAX_1_DATA].u8DelayFrmNum = 2;
 
+			pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = Q03P_FLIP_MIRROR_ADDR;
+
 			break;
 		default:
 			CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
@@ -529,6 +532,7 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 	memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
 	memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
 	pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
+	pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
 
 	return CVI_SUCCESS;
 }
@@ -579,12 +583,38 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
 
 static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
 {
+	CVI_U8 value = q03p_read_register(ViPipe, Q03P_FLIP_MIRROR_ADDR) & ~0x30;
+
 	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
+	ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
 
 	Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState);
 	CMOS_CHECK_POINTER_VOID(pstSnsState);
+
+	pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
+
+	/* Apply the setting on the fly  */
 	if (pstSnsState->bInit == CVI_TRUE && g_aeQ03P_MirrorFip[ViPipe] != eSnsMirrorFlip) {
-		q03p_mirror_flip(ViPipe, eSnsMirrorFlip);
+		switch (eSnsMirrorFlip) {
+		case ISP_SNS_NORMAL:
+			value |= 0x00;
+			break;
+		case ISP_SNS_MIRROR:
+			value |= 0x20;
+			break;
+		case ISP_SNS_FLIP:
+			value |= 0x10;
+			break;
+		case ISP_SNS_MIRROR_FLIP:
+			value |= 0x30;
+			break;
+		default:
+			return;
+		}
+
+		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
+		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
+		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
 		g_aeQ03P_MirrorFip[ViPipe] = eSnsMirrorFlip;
 	}
 }
diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h
index 0e41820f2..465186df6 100644
--- a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h
+++ b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_cmos_ex.h
@@ -28,6 +28,7 @@ enum q03p_linear_regs_e {
 	LINEAR_AGAIN_DATA,
 	LINEAR_VMAX_0_DATA,
 	LINEAR_VMAX_1_DATA,
+	LINEAR_FLIP_MIRROR,
 	LINEAR_REGS_NUM
 };
 
@@ -64,7 +65,6 @@ extern CVI_U16 g_au16Q03P_L2SMode[];
 extern CVI_U8 q03p_i2c_addr;
 extern const CVI_U32 q03p_addr_byte;
 extern const CVI_U32 q03p_data_byte;
-extern void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
 extern void q03p_init(VI_PIPE ViPipe);
 extern void q03p_exit(VI_PIPE ViPipe);
 extern void q03p_standby(VI_PIPE ViPipe);
diff --git a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_sensor_ctl.c
index 207faafae..04bbfd2de 100644
--- a/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_sensor_ctl.c
+++ b/middleware/v2/component/isp/sensor/cv180x/soi_q03p/q03p_sensor_ctl.c
@@ -175,29 +175,6 @@ void q03p_default_reg_init(VI_PIPE ViPipe)
 	}
 }
 
-void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
-{
-	CVI_U8 val = q03p_read_register(ViPipe, 0x12) & ~0x30;
-
-	switch (eSnsMirrorFlip) {
-	case ISP_SNS_NORMAL:
-		break;
-	case ISP_SNS_MIRROR:
-		val |= 0x20;
-		break;
-	case ISP_SNS_FLIP:
-		val |= 0x10;
-		break;
-	case ISP_SNS_MIRROR_FLIP:
-		val |= 0x30;
-		break;
-	default:
-		return;
-	}
-
-	q03p_write_register(ViPipe, 0x12, val);
-}
-
 int q03p_probe(VI_PIPE ViPipe)
 {
 	int nVal;
diff --git a/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos.c b/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos.c
index 8430e0493..611301b24 100644
--- a/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos.c
+++ b/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos.c
@@ -66,44 +66,60 @@ static CVI_U16 g_au16SampleRgain[VI_MAX_PIPE_NUM] = {0};
 static CVI_U16 g_au16SampleBgain[VI_MAX_PIPE_NUM] = {0};
 static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
 /*****CV4001 Lines Range*****/
-#define CV4001_FULL_LINES_MAX  (0xfffff)
+#define CV4001_FULL_LINES_MAX  (0xfffff / 2)//liner mode: vts_reg value is double real_vts
+#define CV4001_FULL_LINES_MAX_2TO1_WDR  (0xfffff / 4)//wdr mode: four
 
 /*****CV4001 Register Address*****/
-#define CV4001_EXP_ADDR0			0x3062 //bit[19:16]
-#define CV4001_EXP_ADDR1			0x3061
-#define CV4001_EXP_ADDR2			0x3060
+#define CV4001_EXP1_ADDR0			0x3062 //bit[19:16]
+#define CV4001_EXP1_ADDR1			0x3061
+#define CV4001_EXP1_ADDR2			0x3060
+#define CV4001_EXP2_ADDR0			0x3066
+#define CV4001_EXP2_ADDR1			0x3065
+#define CV4001_EXP2_ADDR2			0x3064
 
-#define CV4001_AGAIN_ADDR			0x3180 //bit[7:0]
+#define CV4001_AGAIN1_ADDR			0x3180 //bit[7:0]
+#define CV4001_AGAIN2_ADDR			0x3181 //bit[7:0]
 
-#define CV4001_DGAIN_H_ADDR			0x3179 //bit[15:8]
-#define CV4001_DGAIN_L_ADDR			0x3178 //bit[7:0]
+#define CV4001_DGAIN1_H_ADDR		0x3179 //bit[15:8]
+#define CV4001_DGAIN1_L_ADDR		0x3178 //bit[7:0]
+#define CV4001_DGAIN2_H_ADDR		0x317B //bit[15:8]
+#define CV4001_DGAIN2_L_ADDR		0x317A //bit[7:0]
 
 #define CV4001_VTS_ADDR0			0x302A //bit[19:16]
 #define CV4001_VTS_ADDR1			0x3029
 #define CV4001_VTS_ADDR2			0x3028
 
-#define CV4001_FLIP_MIRROR_ADDR			0x3034
+#define CV4001_FLIP_MIRROR_ADDR		0x3034
 
-#define CV4001_RES_IS_1440P(w, h)      ((w) <= 2560 && (h) <= 1440)
+#define CV4001_RES_IS_1440P(w, h)      ((w) == 2560 && (h) == 1440)
 
 static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSnsDft)
 {
+	const CV4001_MODE_S *pstMode;
+
+	CVI_U32 FpsMax;
 	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
 
 	CMOS_CHECK_POINTER(pstAeSnsDft);
 	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
 	CMOS_CHECK_POINTER(pstSnsState);
 
+	pstMode = &g_astCV4001_mode[pstSnsState->u8ImgMode];
+	FpsMax = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MaxFps;
+
 	pstAeSnsDft->u32FullLinesStd = pstSnsState->u32FLStd;
 	pstAeSnsDft->u32FlickerFreq = 50 * 256;
-	pstAeSnsDft->u32FullLinesMax = CV4001_FULL_LINES_MAX;
-	pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * 25);
+	pstAeSnsDft->u32FullLinesMax = (pstSnsState->enWDRMode == WDR_MODE_NONE) ?
+			CV4001_FULL_LINES_MAX : CV4001_FULL_LINES_MAX_2TO1_WDR;
+	pstAeSnsDft->u32HmaxTimes = (1000000) / (pstSnsState->u32FLStd * FpsMax);
 
 	pstAeSnsDft->stIntTimeAccu.enAccuType = AE_ACCURACY_LINEAR;
 	pstAeSnsDft->stIntTimeAccu.f32Accuracy = 1;
 	pstAeSnsDft->stIntTimeAccu.f32Offset = 0;
+
 	pstAeSnsDft->stAgainAccu.enAccuType = AE_ACCURACY_TABLE;
 	pstAeSnsDft->stAgainAccu.f32Accuracy = 1;
+
 	pstAeSnsDft->stDgainAccu.enAccuType = AE_ACCURACY_TABLE;
 	pstAeSnsDft->stDgainAccu.f32Accuracy = 1;
 
@@ -112,27 +128,32 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
 	pstAeSnsDft->u32MaxISPDgainTarget = 2 << pstAeSnsDft->u32ISPDgainShift;
 
 	if (g_au32LinesPer500ms[ViPipe] == 0)
-		pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * 25 / 2;
+		pstAeSnsDft->u32LinesPer500ms = pstSnsState->u32FLStd * FpsMax / 2;
 	else
 		pstAeSnsDft->u32LinesPer500ms = g_au32LinesPer500ms[ViPipe];
 
 	switch (pstSnsState->enWDRMode) {
 	default:
 	case WDR_MODE_NONE:   /*linear mode*/
-		pstAeSnsDft->f32Fps = g_astCV4001_mode[CV4001_MODE_2560X1440P25].f32MaxFps;
-		pstAeSnsDft->f32MinFps = g_astCV4001_mode[CV4001_MODE_2560X1440P25].f32MinFps;
+		pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
+		pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
 		pstAeSnsDft->au8HistThresh[0] = 0xd;
 		pstAeSnsDft->au8HistThresh[1] = 0x28;
 		pstAeSnsDft->au8HistThresh[2] = 0x60;
 		pstAeSnsDft->au8HistThresh[3] = 0x80;
 
-		pstAeSnsDft->u32MaxAgain = 16384;
-		pstAeSnsDft->u32MinAgain = 1024;
+		pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
+		pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
+		pstAeSnsDft->u32MaxIntTimeTarget = 65535;
+		pstAeSnsDft->u32MinIntTimeTarget = 1;
+
+		pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max;
+		pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min;
 		pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
 		pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
 
-		pstAeSnsDft->u32MaxDgain = 16384;
-		pstAeSnsDft->u32MinDgain = 1024;
+		pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max;
+		pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Max;
 		pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
 		pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
 
@@ -142,14 +163,52 @@ static CVI_S32 cmos_get_ae_default(VI_PIPE ViPipe, AE_SENSOR_DEFAULT_S *pstAeSns
 		pstAeSnsDft->u32AEResponseFrame = 4;
 		pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
 		pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
-			g_au32InitExposure[ViPipe] : g_astCV4001_mode[CV4001_MODE_2560X1440P25].stExp[0].u16Def;
+			g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def;
 
-		pstAeSnsDft->u32MaxIntTime = pstSnsState->u32FLStd - 8;
-		pstAeSnsDft->u32MinIntTime = g_astCV4001_mode[CV4001_MODE_2560X1440P25].stExp[0].u16Min;
+		break;
+
+	case WDR_MODE_2To1_LINE:
+		pstAeSnsDft->f32Fps = pstMode->f32MaxFps;
+		pstAeSnsDft->f32MinFps = pstMode->f32MinFps;
+		pstAeSnsDft->au8HistThresh[0] = 0xC;
+		pstAeSnsDft->au8HistThresh[1] = 0x18;
+		pstAeSnsDft->au8HistThresh[2] = 0x60;
+		pstAeSnsDft->au8HistThresh[3] = 0x80;
+
+		pstAeSnsDft->u32MaxIntTime = pstMode->stExp[0].u16Max;
+		pstAeSnsDft->u32MinIntTime = pstMode->stExp[0].u16Min;
 		pstAeSnsDft->u32MaxIntTimeTarget = 65535;
 		pstAeSnsDft->u32MinIntTimeTarget = 1;
+
+		pstAeSnsDft->u32MaxAgain = pstMode->stAgain[0].u32Max;
+		pstAeSnsDft->u32MinAgain = pstMode->stAgain[0].u32Min;
+		pstAeSnsDft->u32MaxAgainTarget = pstAeSnsDft->u32MaxAgain;
+		pstAeSnsDft->u32MinAgainTarget = pstAeSnsDft->u32MinAgain;
+
+		pstAeSnsDft->u32MaxDgain = pstMode->stDgain[0].u32Max;
+		pstAeSnsDft->u32MinDgain = pstMode->stDgain[0].u32Min;
+		pstAeSnsDft->u32MaxDgainTarget = pstAeSnsDft->u32MaxDgain;
+		pstAeSnsDft->u32MinDgainTarget = pstAeSnsDft->u32MinDgain;
+		pstAeSnsDft->u32MaxISPDgainTarget = 16 << pstAeSnsDft->u32ISPDgainShift;
+
+		pstAeSnsDft->u32InitAESpeed = 64;
+		pstAeSnsDft->u32InitAETolerance = 5;
+		pstAeSnsDft->u32AEResponseFrame = 4;
+		pstAeSnsDft->u32InitExposure = g_au32InitExposure[ViPipe] ?
+			g_au32InitExposure[ViPipe] : pstMode->stExp[0].u16Def;
+
+		if (genFSWDRMode[ViPipe] == ISP_FSWDR_LONG_FRAME_MODE) {
+			pstAeSnsDft->u8AeCompensation = 64;
+			pstAeSnsDft->enAeExpMode = AE_EXP_HIGHLIGHT_PRIOR;
+		} else {
+			pstAeSnsDft->u8AeCompensation = 40;
+			pstAeSnsDft->enAeExpMode = AE_EXP_LOWLIGHT_PRIOR;
+		}
+
 		break;
 	}
+	CVI_TRACE_SNS(CVI_DBG_INFO, "again[%d, %d], dgain[%d, %d]\n",
+		pstAeSnsDft->u32MinAgain, pstAeSnsDft->u32MaxAgain, pstAeSnsDft->u32MinDgain, pstAeSnsDft->u32MaxDgain);
 
 	return CVI_SUCCESS;
 }
@@ -168,27 +227,37 @@ static CVI_S32 cmos_fps_set(VI_PIPE ViPipe, CVI_FLOAT f32Fps, AE_SENSOR_DEFAULT_
 	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
 	CMOS_CHECK_POINTER(pstSnsState);
 
-	u32Vts = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
 	pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
+	u32Vts = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
 	f32MaxFps = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MaxFps;
 	f32MinFps = g_astCV4001_mode[pstSnsState->u8ImgMode].f32MinFps;
 
-	if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
-		u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
-	} else {
-		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
-		return CVI_FAILURE;
-	}
-
-	u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX) ? CV4001_FULL_LINES_MAX : u32VMAX;
-
 	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
-		pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = ((u32VMAX & 0xFF0000) >> 16);
-		pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = ((u32VMAX & 0xFF00) >> 8);
-		pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = (u32VMAX & 0xFF);
+		if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
+			u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
+		} else {
+			CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
+			return CVI_FAILURE;
+		}
+
+		u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX) ?
+				CV4001_FULL_LINES_MAX : u32VMAX;
+		pstSnsRegsInfo->astI2cData[LINEAR_VTS_0].u32Data = (((u32VMAX * 2) & 0xFF0000) >> 16);
+		pstSnsRegsInfo->astI2cData[LINEAR_VTS_1].u32Data = (((u32VMAX * 2) & 0xFF00) >> 8);
+		pstSnsRegsInfo->astI2cData[LINEAR_VTS_2].u32Data = ((u32VMAX * 2) & 0xFF);
 	} else {
-		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
-		return CVI_FAILURE;
+		if ((f32Fps <= f32MaxFps) && (f32Fps >= f32MinFps)) {
+			u32VMAX = u32Vts * f32MaxFps / DIV_0_TO_1_FLOAT(f32Fps);
+		} else {
+			CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport Fps: %f\n", f32Fps);
+			return CVI_FAILURE;
+		}
+
+		u32VMAX = (u32VMAX > CV4001_FULL_LINES_MAX_2TO1_WDR) ?
+				CV4001_FULL_LINES_MAX_2TO1_WDR : u32VMAX;
+		pstSnsRegsInfo->astI2cData[WDR2_VTS_0].u32Data = (((u32VMAX * 4) & 0xFF0000) >> 16);
+		pstSnsRegsInfo->astI2cData[WDR2_VTS_1].u32Data = (((u32VMAX * 4) & 0xFF00) >> 8);
+		pstSnsRegsInfo->astI2cData[WDR2_VTS_2].u32Data = ((u32VMAX * 4) & 0xFF);
 	}
 
 	pstSnsState->u32FLStd = u32VMAX;
@@ -209,20 +278,37 @@ static CVI_S32 cmos_inttime_update(VI_PIPE ViPipe, CVI_U32 *u32IntTime)
 {
 	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
 	ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
-	CVI_S32 Cur_Vts;
-	CVI_S32 Reg_IntTime;
+	CVI_S32 Reg_IntTime1;
+	CVI_S32 Reg_IntTime2;
 
 	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
 	CMOS_CHECK_POINTER(pstSnsState);
 	CMOS_CHECK_POINTER(u32IntTime);
-
-	Cur_Vts = pstSnsState->u32FLStd;
-	Reg_IntTime = ((Cur_Vts / 2) - u32IntTime[0]) * 2;
-
 	pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
-	pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime >> 16) & 0x0F);
-	pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime >> 8) & 0xFF);
-	pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime & 0xFF);
+
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
+		Reg_IntTime1 = (pstSnsState->u32FLStd  - u32IntTime[0]) * 2;
+
+		pstSnsRegsInfo->astI2cData[LINEAR_EXP_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F);
+		pstSnsRegsInfo->astI2cData[LINEAR_EXP_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF);
+		pstSnsRegsInfo->astI2cData[LINEAR_EXP_2].u32Data = (Reg_IntTime1 & 0xFF);
+	} else {
+		/* short exposure */
+		pstSnsState->au32WDRIntTime[0] = u32IntTime[0];//?
+		/* long exposure */
+		pstSnsState->au32WDRIntTime[1] = u32IntTime[1];
+
+		Reg_IntTime1 = (pstSnsState->u32FLStd  - u32IntTime[1]) * 4;//u32IntTime[1] long exposure
+		Reg_IntTime2 = (pstSnsState->u32FLStd  - u32IntTime[0]) * 4 + 2;//u32IntTime[0] short exposure
+
+		pstSnsRegsInfo->astI2cData[WDR2_EXP1_0].u32Data = ((Reg_IntTime1 >> 16) & 0x0F);
+		pstSnsRegsInfo->astI2cData[WDR2_EXP1_1].u32Data = ((Reg_IntTime1 >> 8) & 0xFF);
+		pstSnsRegsInfo->astI2cData[WDR2_EXP1_2].u32Data = (Reg_IntTime1 & 0xFF);
+
+		pstSnsRegsInfo->astI2cData[WDR2_EXP2_0].u32Data = ((Reg_IntTime2 >> 16) & 0x0F);
+		pstSnsRegsInfo->astI2cData[WDR2_EXP2_1].u32Data = ((Reg_IntTime2 >> 8) & 0xFF);
+		pstSnsRegsInfo->astI2cData[WDR2_EXP2_2].u32Data = (Reg_IntTime2 & 0xFF);
+	}
 
 	return CVI_SUCCESS;
 }
@@ -340,8 +426,13 @@ static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu
 		pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_H].u32Data = (u32Dgain >> 8);
 		pstSnsRegsInfo->astI2cData[LINEAR_DGAIN_L].u32Data = (u32Dgain & 0xFF);
 	} else {
-		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
-		return CVI_FAILURE;
+		pstSnsRegsInfo->astI2cData[WDR2_AGAIN1].u32Data = u32Again;
+		pstSnsRegsInfo->astI2cData[WDR2_AGAIN2].u32Data = u32Again;
+
+		pstSnsRegsInfo->astI2cData[WDR2_DGAIN1_H].u32Data = (u32Dgain >> 8);
+		pstSnsRegsInfo->astI2cData[WDR2_DGAIN1_L].u32Data = (u32Dgain & 0xFF);
+		pstSnsRegsInfo->astI2cData[WDR2_DGAIN2_H].u32Data = (u32Dgain >> 8);
+		pstSnsRegsInfo->astI2cData[WDR2_DGAIN2_L].u32Data = (u32Dgain & 0xFF);
 	}
 	return CVI_SUCCESS;
 }
@@ -349,14 +440,62 @@ static CVI_S32 cmos_gains_update(VI_PIPE ViPipe, CVI_U32 *pu32Again, CVI_U32 *pu
 static CVI_S32 cmos_get_inttime_max(VI_PIPE ViPipe, CVI_U16 u16ManRatioEnable, CVI_U32 *au32Ratio,
 				    CVI_U32 *au32IntTimeMax, CVI_U32 *au32IntTimeMin, CVI_U32 *pu32LFMaxIntTime)
 {
-	UNUSED(ViPipe);
-	UNUSED(u16ManRatioEnable);
-	UNUSED(au32Ratio);
-	UNUSED(au32IntTimeMax);
-	UNUSED(au32IntTimeMin);
-	UNUSED(pu32LFMaxIntTime);
+	CVI_U32 u32IntTimeMaxTmp  = 0, u32IntTimeMaxTmp0 = 0;
+	CVI_U32 u32RatioTmp = 0x40;
+	CVI_U32 u32ShortTimeMinLimit = 0;
+	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
+
+	CMOS_CHECK_POINTER(au32Ratio);
+	CMOS_CHECK_POINTER(au32IntTimeMax);
+	CMOS_CHECK_POINTER(au32IntTimeMin);
+	CMOS_CHECK_POINTER(pu32LFMaxIntTime);
+	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
+	CMOS_CHECK_POINTER(pstSnsState);
+
+	u32ShortTimeMinLimit = 1;
+	/*
+	 * Long exp + Short exp < VTS
+	 */
+	u32IntTimeMaxTmp0 = ((pstSnsState->au32FL[1] - 1 - g_astCV4001_mode[pstSnsState->u8ImgMode].u32IspResTime -
+			pstSnsState->au32WDRIntTime[0]) * 0x40) / DIV_0_TO_1(au32Ratio[0]);
+	u32IntTimeMaxTmp  = ((pstSnsState->au32FL[0] - 1 - g_astCV4001_mode[pstSnsState->u8ImgMode].u32IspResTime)
+			* 0x40) / DIV_0_TO_1(au32Ratio[0] + 0x40);
+	u32IntTimeMaxTmp = (u32IntTimeMaxTmp > u32IntTimeMaxTmp0) ? u32IntTimeMaxTmp0 : u32IntTimeMaxTmp;
+	u32IntTimeMaxTmp  = (!u32IntTimeMaxTmp) ? u32ShortTimeMinLimit : u32IntTimeMaxTmp;
+
+	if (u32IntTimeMaxTmp >= u32ShortTimeMinLimit) {
+		if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
+			au32IntTimeMax[0] = u32IntTimeMaxTmp;
+			au32IntTimeMax[1] = au32IntTimeMax[0] * au32Ratio[0] >> 6;
+			au32IntTimeMax[2] = au32IntTimeMax[1] * au32Ratio[1] >> 6;
+			au32IntTimeMax[3] = au32IntTimeMax[2] * au32Ratio[2] >> 6;
+			au32IntTimeMin[0] = u32ShortTimeMinLimit;
+			au32IntTimeMin[1] = au32IntTimeMin[0] * au32Ratio[0] >> 6;
+			au32IntTimeMin[2] = au32IntTimeMin[1] * au32Ratio[1] >> 6;
+			au32IntTimeMin[3] = au32IntTimeMin[2] * au32Ratio[2] >> 6;
+		} else {
+		}
+	} else {
+		if (u16ManRatioEnable) {
+			CVI_TRACE_SNS(CVI_DBG_ERR, "Manaul ExpRatio is too large!\n");
+			return CVI_FAILURE;
+		}
+		u32IntTimeMaxTmp = u32ShortTimeMinLimit;
+
+		if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
+			u32RatioTmp = 0xFFF;
+			au32IntTimeMax[0] = u32IntTimeMaxTmp;
+			au32IntTimeMax[1] = au32IntTimeMax[0] * u32RatioTmp >> 6;
+		} else {
+		}
+		au32IntTimeMin[0] = au32IntTimeMax[0];
+		au32IntTimeMin[1] = au32IntTimeMax[1];
+		au32IntTimeMin[2] = au32IntTimeMax[2];
+		au32IntTimeMin[3] = au32IntTimeMax[3];
+	}
+	CVI_TRACE_SNS(CVI_DBG_DEBUG, "sexp[%d, %d], lexp[%d, %d], ratio:%d\n",
+			au32IntTimeMin[0], au32IntTimeMax[0], au32IntTimeMin[1], au32IntTimeMax[1], au32Ratio[0]);
 
-	CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode\n");
 	return CVI_SUCCESS;
 }
 
@@ -390,8 +529,9 @@ static CVI_S32 cmos_init_ae_exp_function(AE_SENSOR_EXP_FUNC_S *pstExpFuncs)
 
 static CVI_S32 cmos_get_awb_default(VI_PIPE ViPipe, AWB_SENSOR_DEFAULT_S *pstAwbSnsDft)
 {
-	CMOS_CHECK_POINTER(pstAwbSnsDft);
 	UNUSED(ViPipe);
+	CMOS_CHECK_POINTER(pstAwbSnsDft);
+
 	memset(pstAwbSnsDft, 0, sizeof(AWB_SENSOR_DEFAULT_S));
 
 	pstAwbSnsDft->u16InitGgain = 1024;
@@ -414,6 +554,7 @@ static CVI_S32 cmos_init_awb_exp_function(AWB_SENSOR_EXP_FUNC_S *pstExpFuncs)
 static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
 {
 	UNUSED(ViPipe);
+
 	memset(pstDef, 0, sizeof(ISP_CMOS_DEFAULT_S));
 
 	return CVI_SUCCESS;
@@ -421,12 +562,22 @@ static CVI_S32 cmos_get_isp_default(VI_PIPE ViPipe, ISP_CMOS_DEFAULT_S *pstDef)
 
 static CVI_S32 cmos_get_blc_default(VI_PIPE ViPipe, ISP_CMOS_BLACK_LEVEL_S *pstBlc)
 {
-	CMOS_CHECK_POINTER(pstBlc);
+	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
+
 	UNUSED(ViPipe);
+	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
+	CMOS_CHECK_POINTER(pstSnsState);
+	CMOS_CHECK_POINTER(pstBlc);
+
 	memset(pstBlc, 0, sizeof(ISP_CMOS_BLACK_LEVEL_S));
 
-	memcpy(pstBlc,
-		&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE)
+		memcpy(pstBlc,
+			&g_stIspBlcCalibratio, sizeof(ISP_CMOS_BLACK_LEVEL_S));
+	else
+		memcpy(pstBlc,
+			&g_stIspBlcCalibratio_wdr, sizeof(ISP_CMOS_BLACK_LEVEL_S));
+
 	return CVI_SUCCESS;
 }
 
@@ -439,11 +590,13 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
 	CMOS_CHECK_POINTER(pstSnsState);
 	pstMode = &g_astCV4001_mode[pstSnsState->u8ImgMode];
 
-	if (pstSnsState->enWDRMode != WDR_MODE_NONE) {
-		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport WDRMode: %d\n", pstSnsState->enWDRMode);
-	} else {
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
 		pstIspCfg->frm_num = 1;
 		memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
+	} else {
+		pstIspCfg->frm_num = 2;
+		memcpy(&pstIspCfg->img_size[0], &pstMode->astImg[0], sizeof(ISP_WDR_SIZE_S));
+		memcpy(&pstIspCfg->img_size[1], &pstMode->astImg[1], sizeof(ISP_WDR_SIZE_S));
 	}
 
 	return CVI_SUCCESS;
@@ -451,9 +604,42 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg)
 
 static CVI_S32 cmos_set_wdr_mode(VI_PIPE ViPipe, CVI_U8 u8Mode)
 {
-	UNUSED(ViPipe);
-	UNUSED(u8Mode);
-	CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
+	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
+
+	CV4001_SENSOR_GET_CTX(ViPipe, pstSnsState);
+	CMOS_CHECK_POINTER(pstSnsState);
+
+	pstSnsState->bSyncInit = CVI_FALSE;
+
+	switch (u8Mode) {
+	case WDR_MODE_NONE:
+		if (pstSnsState->u8ImgMode == CV4001_MODE_2560X1440P15_WDR)
+			pstSnsState->u8ImgMode = CV4001_MODE_2560X1440P25;
+
+		pstSnsState->enWDRMode = WDR_MODE_NONE;
+		pstSnsState->u32FLStd = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
+		syslog(LOG_INFO, "WDR_MODE_NONE\n");
+		break;
+
+	case WDR_MODE_2To1_LINE:
+		if (pstSnsState->u8ImgMode == CV4001_MODE_2560X1440P25) {
+			pstSnsState->u8ImgMode = CV4001_MODE_2560X1440P15_WDR;
+		}
+
+		pstSnsState->enWDRMode = WDR_MODE_2To1_LINE;
+		pstSnsState->u32FLStd = g_astCV4001_mode[pstSnsState->u8ImgMode].u32VtsDef;
+		syslog(LOG_INFO, "WDR_MODE_2To1_LINE 1440p mode(60fps->30fps)\n");
+		break;
+
+	default:
+		CVI_TRACE_SNS(CVI_DBG_ERR, "Unsupport sensor mode!\n");
+		return CVI_FAILURE;
+	}
+
+	pstSnsState->au32FL[0] = pstSnsState->u32FLStd;
+	pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
+	memset(pstSnsState->au32WDRIntTime, 0, sizeof(pstSnsState->au32WDRIntTime));
+
 	return CVI_SUCCESS;
 }
 
@@ -505,7 +691,8 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 		pstCfg0->snsCfg.unComBus.s8I2cDev = g_aunCV4001_BusInfo[ViPipe].s8I2cDev;
 		pstCfg0->snsCfg.u8Cfg2ValidDelayMax = 0;
 		pstCfg0->snsCfg.use_snsr_sram = CVI_TRUE;
-		pstCfg0->snsCfg.u32RegNum = LINEAR_REGS_NUM;
+		pstCfg0->snsCfg.u32RegNum = (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) ?
+					WDR2_REGS_NUM : LINEAR_REGS_NUM;
 
 		for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
 			pstI2c_data[i].bUpdate = CVI_TRUE;
@@ -514,65 +701,54 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 			pstI2c_data[i].u32DataByteNum = cv4001_data_byte;
 		}
 
-		pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV4001_EXP_ADDR0;
-		pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV4001_EXP_ADDR1;
-		pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV4001_EXP_ADDR2;
-		pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV4001_AGAIN_ADDR;
-		pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV4001_DGAIN_H_ADDR;
-		pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV4001_DGAIN_L_ADDR;
-		pstI2c_data[LINEAR_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
-		pstI2c_data[LINEAR_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
-		pstI2c_data[LINEAR_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
-		pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
-
+		switch (pstSnsState->enWDRMode) {
+		case WDR_MODE_2To1_LINE:
+			pstI2c_data[WDR2_EXP1_0].u32RegAddr = CV4001_EXP1_ADDR0;
+			pstI2c_data[WDR2_EXP1_1].u32RegAddr = CV4001_EXP1_ADDR1;
+			pstI2c_data[WDR2_EXP1_2].u32RegAddr = CV4001_EXP1_ADDR2;
+			pstI2c_data[WDR2_EXP2_0].u32RegAddr = CV4001_EXP2_ADDR0;
+			pstI2c_data[WDR2_EXP2_1].u32RegAddr = CV4001_EXP2_ADDR1;
+			pstI2c_data[WDR2_EXP2_2].u32RegAddr = CV4001_EXP2_ADDR2;
+			pstI2c_data[WDR2_AGAIN1].u32RegAddr = CV4001_AGAIN1_ADDR;
+			pstI2c_data[WDR2_AGAIN2].u32RegAddr = CV4001_AGAIN2_ADDR;
+			pstI2c_data[WDR2_DGAIN1_H].u32RegAddr = CV4001_DGAIN1_H_ADDR;
+			pstI2c_data[WDR2_DGAIN1_L].u32RegAddr = CV4001_DGAIN1_L_ADDR;
+			pstI2c_data[WDR2_DGAIN2_H].u32RegAddr = CV4001_DGAIN2_H_ADDR;
+			pstI2c_data[WDR2_DGAIN2_L].u32RegAddr = CV4001_DGAIN2_L_ADDR;
+			pstI2c_data[WDR2_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
+			pstI2c_data[WDR2_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
+			pstI2c_data[WDR2_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
+			pstI2c_data[WDR2_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
+			break;
+		default:
+			pstI2c_data[LINEAR_EXP_0].u32RegAddr = CV4001_EXP1_ADDR0;
+			pstI2c_data[LINEAR_EXP_1].u32RegAddr = CV4001_EXP1_ADDR1;
+			pstI2c_data[LINEAR_EXP_2].u32RegAddr = CV4001_EXP1_ADDR2;
+			pstI2c_data[LINEAR_AGAIN].u32RegAddr = CV4001_AGAIN1_ADDR;
+			pstI2c_data[LINEAR_DGAIN_H].u32RegAddr = CV4001_DGAIN1_H_ADDR;
+			pstI2c_data[LINEAR_DGAIN_L].u32RegAddr = CV4001_DGAIN1_L_ADDR;
+			pstI2c_data[LINEAR_VTS_0].u32RegAddr = CV4001_VTS_ADDR0;
+			pstI2c_data[LINEAR_VTS_1].u32RegAddr = CV4001_VTS_ADDR1;
+			pstI2c_data[LINEAR_VTS_2].u32RegAddr = CV4001_VTS_ADDR2;
+			pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = CV4001_FLIP_MIRROR_ADDR;
+			break;
+		}
 		pstSnsState->bSyncInit = CVI_TRUE;
 		pstCfg0->snsCfg.need_update = CVI_TRUE;
 		/* recalcualte WDR size */
 		cmos_get_wdr_size(ViPipe, &pstCfg0->ispCfg);
 		pstCfg0->ispCfg.need_update = CVI_TRUE;
 	} else {
-
-		CVI_U32 gainsUpdate = 0, shutterUpdate = 0, vtsUpdate = 0;
-
 		pstCfg0->snsCfg.need_update = CVI_FALSE;
 		for (i = 0; i < pstCfg0->snsCfg.u32RegNum; i++) {
 			if (pstCfg0->snsCfg.astI2cData[i].u32Data == pstCfg1->snsCfg.astI2cData[i].u32Data) {
 				pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_FALSE;
 			} else {
-
-				if ((i >= LINEAR_AGAIN) && (i <= LINEAR_DGAIN_L)) {
-					gainsUpdate = 1;
-				}
-
-				if (i <= LINEAR_EXP_2) {
-					shutterUpdate = 1;
-				}
-
-				if ((i >= LINEAR_VTS_0) && (i <= LINEAR_VTS_2)) {
-					vtsUpdate = 1;
-				}
-
 				pstCfg0->snsCfg.astI2cData[i].bUpdate = CVI_TRUE;
 				pstCfg0->snsCfg.need_update = CVI_TRUE;
 			}
 		}
 
-		if (gainsUpdate) {
-			pstCfg0->snsCfg.astI2cData[LINEAR_AGAIN].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_H].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_DGAIN_L].bUpdate = CVI_TRUE;
-		}
-		if (shutterUpdate) {
-			pstCfg0->snsCfg.astI2cData[LINEAR_EXP_0].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_EXP_1].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_EXP_2].bUpdate = CVI_TRUE;
-		}
-		if (vtsUpdate) {
-			pstCfg0->snsCfg.astI2cData[LINEAR_VTS_0].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_VTS_1].bUpdate = CVI_TRUE;
-			pstCfg0->snsCfg.astI2cData[LINEAR_VTS_2].bUpdate = CVI_TRUE;
-		}
-
 		/* check update isp crop or not */
 		pstCfg0->ispCfg.need_update = (sensor_cmp_wdr_size(&pstCfg0->ispCfg, &pstCfg1->ispCfg) ?
 				CVI_TRUE : CVI_FALSE);
@@ -582,7 +758,12 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 	memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
 	memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
 	pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
-	pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
+
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
+		pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
+	} else {
+		pstCfg0->snsCfg.astI2cData[WDR2_FLIP_MIRROR].bDropFrm = CVI_FALSE;
+	}
 
 	return CVI_SUCCESS;
 }
@@ -611,6 +792,17 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
 					      pstSnsState->enWDRMode);
 				return CVI_FAILURE;
 			}
+		} else if (pstSnsState->enWDRMode == WDR_MODE_2To1_LINE) {
+			if (CV4001_RES_IS_1440P(pstSensorImageMode->u16Width, pstSensorImageMode->u16Height)) {
+				u8SensorImageMode = CV4001_MODE_2560X1440P15_WDR;
+			} else {
+				CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
+				       pstSensorImageMode->u16Width,
+				       pstSensorImageMode->u16Height,
+				       pstSensorImageMode->f32Fps,
+				       pstSnsState->enWDRMode);
+				return CVI_FAILURE;
+			}
 		} else {
 			CVI_TRACE_SNS(CVI_DBG_ERR, "Not support! Width:%d, Height:%d, Fps:%f, WDRMode:%d\n",
 				      pstSensorImageMode->u16Width,
@@ -677,9 +869,17 @@ static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSn
 			return;
 		}
 
-		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
-		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
-		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
+		if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
+			pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
+			pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
+			pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
+		} else {
+			start_x = 0;
+			start_y = 0;
+			pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].u32Data = value;
+			pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].bDropFrm = 1;
+			pstSnsRegsInfo->astI2cData[WDR2_FLIP_MIRROR].u8DropFrmNum = 2;
+		}
 		g_aeCV4001_MirrorFip[ViPipe] = eSnsMirrorFlip;
 		pstIspCfg0->img_size[0].stWndRect.s32X = start_x;
 		pstIspCfg0->img_size[0].stWndRect.s32Y = start_y;
@@ -718,8 +918,11 @@ static CVI_S32 sensor_rx_attr(VI_PIPE ViPipe, SNS_COMBO_DEV_ATTR_S *pstRxAttr)
 
 	pstRxAttr->img_size.width = g_astCV4001_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Width;
 	pstRxAttr->img_size.height = g_astCV4001_mode[pstSnsState->u8ImgMode].astImg[0].stSnsSize.u32Height;
-	if (pstSnsState->enWDRMode == WDR_MODE_NONE)
+	if (pstSnsState->enWDRMode == WDR_MODE_NONE) {
 		pstRxAttr->mipi_attr.wdr_mode = CVI_MIPI_WDR_MODE_NONE;
+	} else {
+		pstRxAttr->mac_clk = RX_MAC_CLK_400M;
+	}
 
 	return CVI_SUCCESS;
 
diff --git a/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_ex.h
index b133ecfcb..610eec99a 100644
--- a/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_ex.h
+++ b/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_ex.h
@@ -36,8 +36,30 @@ enum cv4001_linear_regs_e {
 	LINEAR_REGS_NUM
 };
 
+enum cv4001_wdr2_regs_e {
+	WDR2_EXP1_0,
+	WDR2_EXP1_1,
+	WDR2_EXP1_2,
+	WDR2_EXP2_0,
+	WDR2_EXP2_1,
+	WDR2_EXP2_2,
+	WDR2_AGAIN1,
+	WDR2_AGAIN2,
+	WDR2_DGAIN1_H,
+	WDR2_DGAIN1_L,
+	WDR2_DGAIN2_H,
+	WDR2_DGAIN2_L,
+	WDR2_VTS_0,
+	WDR2_VTS_1,
+	WDR2_VTS_2,
+	WDR2_FLIP_MIRROR,
+	WDR2_REGS_NUM
+};
+
 typedef enum _CV4001_MODE_E {
 	CV4001_MODE_2560X1440P25 = 0,
+	CV4001_MODE_LINEAR_NUM,
+	CV4001_MODE_2560X1440P15_WDR = CV4001_MODE_LINEAR_NUM,
 	CV4001_MODE_NUM
 } CV4001_MODE_E;
 
@@ -52,6 +74,7 @@ typedef struct _CV4001_MODE_S {
 	CVI_U32 u32HtsDef;
 	CVI_U32 u32VtsDef;
 	SNS_ATTR_S stExp[2];
+	CVI_U32 u32IspResTime;
 	SNS_ATTR_LARGE_S stAgain[2];
 	SNS_ATTR_LARGE_S stDgain[2];
 	char name[64];
diff --git a/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_param.h b/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_param.h
index 62e9187c1..74855f389 100644
--- a/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_param.h
+++ b/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_cmos_param.h
@@ -39,13 +39,13 @@ static const CV4001_MODE_S g_astCV4001_mode[CV4001_MODE_NUM] = {
 			},
 		},
 		.f32MaxFps = 25,
-		.f32MinFps = 0.076, /* 3200 * 25 / 0x0FFFFF  */
-		.u32HtsDef = 743,
-		.u32VtsDef = 3200,
+		.f32MinFps = 0.072, /* 1500 * 25 / (0x0FFFFF / 2)  */
+		.u32HtsDef = 1480,	//hts_reg * 2
+		.u32VtsDef = 1500,	//vts_reg / 2
 		.stExp[0] = {
-			.u16Min = 8,
-			.u16Max = 3200-4,
-			.u16Def = 8,
+			.u16Min = 4,
+			.u16Max = 1500-2,
+			.u16Def = 4,
 			.u16Step = 1,
 		},
 		.stAgain[0] = {
@@ -61,6 +61,81 @@ static const CV4001_MODE_S g_astCV4001_mode[CV4001_MODE_NUM] = {
 			.u32Step = 64,
 		},
 	},
+	[CV4001_MODE_2560X1440P15_WDR] = {
+		.name = "2560X1440P15_WDR",
+		.astImg[0] = {
+			.stSnsSize = {
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+			.stWndRect = {
+				.s32X = 0,
+				.s32Y = 0,
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+			.stMaxSize = {
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+		},
+		.astImg[1] = {
+			.stSnsSize = {
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+			.stWndRect = {
+				.s32X = 0,
+				.s32Y = 0,
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+			.stMaxSize = {
+				.u32Width = 2560,
+				.u32Height = 1440,
+			},
+		},
+		.f32MaxFps = 15,
+		.f32MinFps = 0.084, /* 1474 * 15 / (0x0FFFFF / 4) */
+		.u32HtsDef = 5088,	//hts_reg * 4
+		.u32VtsDef = 1474,	//vts_reg / 4
+		.stExp[0] = {
+			.u16Min = 4,
+			.u16Max = 1474-1,
+			.u16Def = 4,
+			.u16Step = 1,
+		},
+		.stExp[1] = {
+			.u16Min = 4,
+			.u16Max = 98,
+			.u16Def = 4,
+			.u16Step = 1,
+		},
+		.stAgain[0] = {
+			.u32Min = 1024,
+			.u32Max = 16384,
+			.u32Def = 1024,
+			.u32Step = 1,
+		},
+		.stAgain[1] = {
+			.u32Min = 1024,
+			.u32Max = 16384,
+			.u32Def = 1024,
+			.u32Step = 1,
+		},
+		.stDgain[0] = {
+			.u32Min = 1024,
+			.u32Max = 16384,
+			.u32Def = 1024,
+			.u32Step = 64,
+		},
+		.stDgain[1] = {
+			.u32Min = 1024,
+			.u32Max = 16384,
+			.u32Def = 1024,
+			.u32Step = 64,
+		},
+	}
 };
 
 
@@ -97,6 +172,39 @@ static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio = {
 	},
 };
 
+static ISP_CMOS_BLACK_LEVEL_S g_stIspBlcCalibratio_wdr = {
+	.bUpdate = CVI_TRUE,
+	.blcAttr = {
+		.Enable = 1,
+		.enOpType = OP_TYPE_AUTO,
+		.stManual = {196, 196, 196, 196, 0, 0, 0, 0
+#ifdef ARCH_CV182X
+			, 1075, 1075, 1075, 1075
+#endif
+		},
+		.stAuto = {
+			{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
+			{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
+			{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
+			{196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196, 196 },
+			{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+			{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+			{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+			{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+#ifdef ARCH_CV182X
+			{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
+				1075, 1075},
+			{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
+				1075, 1075},
+			{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
+				1075, 1075},
+			{1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075, 1075,
+				1075, 1075},
+#endif
+		},
+	},
+};
+
 struct combo_dev_attr_s cv4001_rx_attr = {
 	.input_mode = INPUT_MODE_MIPI,
 	.mac_clk = RX_MAC_CLK_200M,
@@ -104,7 +212,7 @@ struct combo_dev_attr_s cv4001_rx_attr = {
 		.raw_data_type = RAW_DATA_12BIT,
 		.lane_id = {1, 2, 0, -1, -1},
 		.pn_swap = {1, 1, 1, 0, 0},
-		.wdr_mode = CVI_MIPI_WDR_MODE_NONE,
+		.wdr_mode = CVI_MIPI_WDR_MODE_VC,
 	},
 	.mclk = {
 		.cam = 0,
diff --git a/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_sensor_ctl.c
index af0253489..c6ddd0d7e 100644
--- a/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_sensor_ctl.c
+++ b/middleware/v2/component/isp/sensor/cv181x/cvsens_cv4001/cv4001_sensor_ctl.c
@@ -19,9 +19,10 @@
 
 #define CV4001_CHIP_ID_ADDR_H	0x3003
 #define CV4001_CHIP_ID_ADDR_L	0x3002
-#define CV4001_CHIP_ID		0x4001
+#define CV4001_CHIP_ID			0x4001
 
 static void cv4001_linear_1440p25_init(VI_PIPE ViPipe);
+static void cv4001_wdr_1440p15_2to1_init(VI_PIPE ViPipe);
 
 CVI_U8 cv4001_i2c_addr = 0x35;
 const CVI_U32 cv4001_addr_byte = 2;
@@ -198,9 +199,23 @@ int cv4001_probe(VI_PIPE ViPipe)
 
 void cv4001_init(VI_PIPE ViPipe)
 {
+	WDR_MODE_E        enWDRMode;
+	CVI_U8            u8ImgMode;
+
+	enWDRMode   = g_pastCV4001[ViPipe]->enWDRMode;
+	u8ImgMode   = g_pastCV4001[ViPipe]->u8ImgMode;
+
 	cv4001_i2c_init(ViPipe);
 
-	cv4001_linear_1440p25_init(ViPipe);
+	if (enWDRMode == WDR_MODE_2To1_LINE) {
+		if (u8ImgMode == CV4001_MODE_2560X1440P15_WDR) {
+			cv4001_wdr_1440p15_2to1_init(ViPipe);
+		}
+	} else {
+		if (u8ImgMode == CV4001_MODE_2560X1440P25) {
+			cv4001_linear_1440p25_init(ViPipe);
+		}
+	}
 
 	g_pastCV4001[ViPipe]->bInit = CVI_TRUE;
 }
@@ -292,3 +307,99 @@ static void cv4001_linear_1440p25_init(VI_PIPE ViPipe)
 
 	printf("ViPipe:%d,===CV4001 1440P 25fps 12bit LINEAR Init OK!===\n", ViPipe);
 }
+
+static void cv4001_wdr_1440p15_2to1_init(VI_PIPE ViPipe)
+{
+	cv4001_write_register(ViPipe, 0x3028, 0x08);
+	cv4001_write_register(ViPipe, 0x3029, 0x17);
+	cv4001_write_register(ViPipe, 0x302C, 0xF8);
+	cv4001_write_register(ViPipe, 0x302D, 0x04);
+	cv4001_write_register(ViPipe, 0x3908, 0x4B);
+	cv4001_write_register(ViPipe, 0x3304, 0x01);
+	cv4001_write_register(ViPipe, 0x3305, 0x02);
+	cv4001_write_register(ViPipe, 0x3306, 0x01);
+	cv4001_write_register(ViPipe, 0x343E, 0x00);
+	cv4001_write_register(ViPipe, 0x3401, 0x03);
+	cv4001_write_register(ViPipe, 0x3035, 0x01);
+	cv4001_write_register(ViPipe, 0x3036, 0x01);
+	cv4001_write_register(ViPipe, 0x3020, 0x04);
+	cv4001_write_register(ViPipe, 0x3048, 0x44);
+	cv4001_write_register(ViPipe, 0x3049, 0x00);
+	cv4001_write_register(ViPipe, 0x304A, 0x00);
+	cv4001_write_register(ViPipe, 0x304B, 0x0A);
+	cv4001_write_register(ViPipe, 0x3054, 0x2C);
+	cv4001_write_register(ViPipe, 0x3056, 0xA8);
+	cv4001_write_register(ViPipe, 0x3057, 0x05);
+	cv4001_write_register(ViPipe, 0x3030, 0x05);
+	cv4001_write_register(ViPipe, 0x3060, 0x2C);
+	cv4001_write_register(ViPipe, 0x3064, 0x12);
+	cv4001_write_register(ViPipe, 0x3070, 0x1A);//62
+	cv4001_write_register(ViPipe, 0x3071, 0x00);
+	cv4001_write_register(ViPipe, 0x343C, 0x01);
+	cv4001_write_register(ViPipe, 0x3930, 0x00);
+	cv4001_write_register(ViPipe, 0x3040, 0x01);
+	cv4001_write_register(ViPipe, 0x3044, 0x04);
+	cv4001_write_register(ViPipe, 0x3046, 0xA0);
+	cv4001_write_register(ViPipe, 0x3047, 0x05);
+	cv4001_write_register(ViPipe, 0x362A, 0x00);
+	cv4001_write_register(ViPipe, 0x3625, 0x01);
+	cv4001_write_register(ViPipe, 0x35A4, 0x09);
+	cv4001_write_register(ViPipe, 0x35A8, 0x09);
+	cv4001_write_register(ViPipe, 0x35AE, 0x07);
+	cv4001_write_register(ViPipe, 0x35AF, 0x07);
+	cv4001_write_register(ViPipe, 0x34A2, 0x2C);
+	cv4001_write_register(ViPipe, 0x3416, 0x0F);
+	cv4001_write_register(ViPipe, 0x3418, 0x9F);
+	cv4001_write_register(ViPipe, 0x341A, 0x57);
+	cv4001_write_register(ViPipe, 0x341C, 0x57);
+	cv4001_write_register(ViPipe, 0x341E, 0x6F);
+	cv4001_write_register(ViPipe, 0x341F, 0x01);
+	cv4001_write_register(ViPipe, 0x3420, 0x57);
+	cv4001_write_register(ViPipe, 0x3422, 0x9F);
+	cv4001_write_register(ViPipe, 0x3424, 0x57);
+	cv4001_write_register(ViPipe, 0x3426, 0x8F);
+	cv4001_write_register(ViPipe, 0x3428, 0x47);
+	cv4001_write_register(ViPipe, 0x3348, 0x00);
+	cv4001_write_register(ViPipe, 0x3000, 0x00);
+	cv4001_write_register(ViPipe, 0x3220, 0x03);
+	cv4001_write_register(ViPipe, 0x3347, 0x01);
+	cv4001_write_register(ViPipe, 0x3348, 0x00);
+	cv4001_write_register(ViPipe, 0x3804, 0x0F);
+	cv4001_write_register(ViPipe, 0x3576, 0x06);
+	cv4001_write_register(ViPipe, 0x350F, 0x18);
+	cv4001_write_register(ViPipe, 0x3513, 0x07);
+	cv4001_write_register(ViPipe, 0x3517, 0x07);
+	cv4001_write_register(ViPipe, 0x351A, 0x05);
+	cv4001_write_register(ViPipe, 0x351E, 0x0B);
+	cv4001_write_register(ViPipe, 0x357A, 0x0B);
+	cv4001_write_register(ViPipe, 0x3244, 0x08);
+	cv4001_write_register(ViPipe, 0x3270, 0x60);
+	cv4001_write_register(ViPipe, 0x3271, 0x00);
+	cv4001_write_register(ViPipe, 0x3272, 0x00);
+	cv4001_write_register(ViPipe, 0x3890, 0x01);
+	cv4001_write_register(ViPipe, 0x3894, 0x05);
+	cv4001_write_register(ViPipe, 0x3690, 0x00);
+	cv4001_write_register(ViPipe, 0x3898, 0x20);
+	cv4001_write_register(ViPipe, 0x3899, 0x20);
+	cv4001_write_register(ViPipe, 0x389a, 0x20);
+	cv4001_write_register(ViPipe, 0x389b, 0x20);
+	cv4001_write_register(ViPipe, 0x389c, 0x20);
+	cv4001_write_register(ViPipe, 0x389d, 0x15);
+	cv4001_write_register(ViPipe, 0x389e, 0x05);
+	cv4001_write_register(ViPipe, 0x3583, 0x2f);
+	cv4001_write_register(ViPipe, 0x3b75, 0x00);
+	cv4001_write_register(ViPipe, 0x3b5E, 0x01);
+	cv4001_write_register(ViPipe, 0x3a10, 0x06);
+	cv4001_write_register(ViPipe, 0x3a11, 0x06);
+	cv4001_write_register(ViPipe, 0x316C, 0x64);
+	cv4001_write_register(ViPipe, 0x3162, 0x01);
+	cv4001_write_register(ViPipe, 0x3180, 0x00);
+	cv4001_write_register(ViPipe, 0x3178, 0x40);
+	cv4001_write_register(ViPipe, 0x3179, 0x00);
+
+	cv4001_default_reg_init(ViPipe);
+	delay_ms(100);
+
+	printf("ViPipe:%d,===CV4001 1440P 15fps 12bit WDR2TO1 Init OK!===\n", ViPipe);
+}
+
diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_k06/k06_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/soi_k06/k06_sensor_ctl.c
index d97d23e85..e9b8cd3d8 100644
--- a/middleware/v2/component/isp/sensor/cv181x/soi_k06/k06_sensor_ctl.c
+++ b/middleware/v2/component/isp/sensor/cv181x/soi_k06/k06_sensor_ctl.c
@@ -160,26 +160,36 @@ void k06_default_reg_init(VI_PIPE ViPipe)
 
 void k06_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
 {
-	CVI_U8 val = k06_read_register(ViPipe, 0x12) & (~0x30);
+	CVI_U8 val1 = k06_read_register(ViPipe, 0x12);
+	CVI_U8 val2 = k06_read_register(ViPipe, 0xAA);
+	CVI_U8 val3 = k06_read_register(ViPipe, 0x27);
 
 	switch (eSnsMirrorFlip) {
 	case ISP_SNS_NORMAL:
-		val |= 0x30;
+		val1 = 0x30;
+		val2 = 0x84;
 		break;
 	case ISP_SNS_MIRROR:
-		val |= (0x1 << 4);
+		val1 = 0x10;
+		val2 = 0x8B;
+		val3 += 1;
 		break;
 	case ISP_SNS_FLIP:
-		val |= (0x2 << 4);
+		val1 = 0x20;
+		val2 = 0x84;
 		break;
 	case ISP_SNS_MIRROR_FLIP:
-		val &= ~(0x1 << 4);
+		val1 = 0x00;
+		val2 = 0x8B;
+		val3 += 1;
 		break;
 	default:
 		return;
 	}
 
-	k06_write_register(ViPipe, 0x12, val);
+	k06_write_register(ViPipe, 0x12, val1);
+	k06_write_register(ViPipe, 0xAA, val2);
+	k06_write_register(ViPipe, 0x27, val3);
 }
 
 int k06_probe(VI_PIPE ViPipe)
@@ -235,6 +245,7 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x10, 0x48);
 	k06_write_register(ViPipe, 0x11, 0x80);
 	k06_write_register(ViPipe, 0x46, 0x08);
+	k06_write_register(ViPipe, 0x7F, 0x5E);
 	k06_write_register(ViPipe, 0x0D, 0xA0);
 	k06_write_register(ViPipe, 0x57, 0x67);
 	k06_write_register(ViPipe, 0x58, 0x1F);
@@ -247,10 +258,10 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x24, 0x80);
 	k06_write_register(ViPipe, 0x25, 0xA0);
 	k06_write_register(ViPipe, 0x26, 0x52);
-	k06_write_register(ViPipe, 0x27, 0x27);
+	k06_write_register(ViPipe, 0x27, 0x46);
 	k06_write_register(ViPipe, 0x28, 0x15);
 	k06_write_register(ViPipe, 0x29, 0x04);
-	k06_write_register(ViPipe, 0x2A, 0x20);
+	k06_write_register(ViPipe, 0x2A, 0x40);
 	k06_write_register(ViPipe, 0x2B, 0x14);
 	k06_write_register(ViPipe, 0x2C, 0x00);
 	k06_write_register(ViPipe, 0x2D, 0x00);
@@ -263,36 +274,35 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x77, 0x0C);
 	k06_write_register(ViPipe, 0x80, 0x01);
 	k06_write_register(ViPipe, 0xAF, 0x12);
-	k06_write_register(ViPipe, 0xAA, 0x04);
+	k06_write_register(ViPipe, 0xAA, 0x84);
 	k06_write_register(ViPipe, 0x1D, 0x00);
 	k06_write_register(ViPipe, 0x1E, 0x04);
 	k06_write_register(ViPipe, 0x6C, 0x40);
 	k06_write_register(ViPipe, 0x9E, 0xF8);
-	k06_write_register(ViPipe, 0x0C, 0x30);
-	k06_write_register(ViPipe, 0x6F, 0x80);
+	k06_write_register(ViPipe, 0x0C, 0x00);
 	k06_write_register(ViPipe, 0x6E, 0x2C);
 	k06_write_register(ViPipe, 0x70, 0xF9);
 	k06_write_register(ViPipe, 0x71, 0xDD);
 	k06_write_register(ViPipe, 0x72, 0xD5);
 	k06_write_register(ViPipe, 0x73, 0x5A);
 	k06_write_register(ViPipe, 0x74, 0x02);
-	k06_write_register(ViPipe, 0x78, 0x1D);
+	k06_write_register(ViPipe, 0x78, 0x1C);
 	k06_write_register(ViPipe, 0x89, 0x01);
 	k06_write_register(ViPipe, 0x6B, 0x20);
 	k06_write_register(ViPipe, 0x86, 0x40);
+	k06_write_register(ViPipe, 0x6F, 0x00);
 	k06_write_register(ViPipe, 0x30, 0x8D);
 	k06_write_register(ViPipe, 0x31, 0x08);
 	k06_write_register(ViPipe, 0x32, 0x20);
 	k06_write_register(ViPipe, 0x33, 0x5C);
 	k06_write_register(ViPipe, 0x34, 0x30);
 	k06_write_register(ViPipe, 0x35, 0x30);
-	k06_write_register(ViPipe, 0x3A, 0xB6);
+	k06_write_register(ViPipe, 0x3A, 0xB9);
 	k06_write_register(ViPipe, 0x56, 0x92);
-	k06_write_register(ViPipe, 0x59, 0x48);
+	k06_write_register(ViPipe, 0x59, 0x60);
 	k06_write_register(ViPipe, 0x5A, 0x01);
 	k06_write_register(ViPipe, 0x61, 0x00);
 	k06_write_register(ViPipe, 0x64, 0xC0);
-	k06_write_register(ViPipe, 0x7F, 0x46);
 	k06_write_register(ViPipe, 0x85, 0x44);
 	k06_write_register(ViPipe, 0x8A, 0x00);
 	k06_write_register(ViPipe, 0x91, 0x58);
@@ -317,14 +327,14 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x8F, 0x90);
 	k06_write_register(ViPipe, 0xA4, 0xC7);
 	k06_write_register(ViPipe, 0xA5, 0xAF);
-	k06_write_register(ViPipe, 0xB7, 0x21);
+	k06_write_register(ViPipe, 0xB7, 0x61);
 	k06_write_register(ViPipe, 0x97, 0x20);
 	k06_write_register(ViPipe, 0x13, 0x81);
 	k06_write_register(ViPipe, 0x96, 0x84);
 	k06_write_register(ViPipe, 0x4A, 0x01);
 	k06_write_register(ViPipe, 0x7E, 0x4C);
 	k06_write_register(ViPipe, 0x50, 0x02);
-	k06_write_register(ViPipe, 0x93, 0xC0);
+	k06_write_register(ViPipe, 0x93, 0x00);
 	k06_write_register(ViPipe, 0xB5, 0x4C);
 	k06_write_register(ViPipe, 0xB1, 0x00);
 	k06_write_register(ViPipe, 0xA1, 0x0F);
@@ -340,10 +350,12 @@ static void k06_linear_1440p25_init(VI_PIPE ViPipe)
 	k06_write_register(ViPipe, 0x1B, 0x4F);
 
 	k06_default_reg_init(ViPipe);
-//	k06_write_register(ViPipe, 0x12, 0x00);
+
 	k06_write_register(ViPipe, 0x12, 0x30);
 	k06_write_register(ViPipe, 0x48, 0x86);
 	k06_write_register(ViPipe, 0x48, 0x06);
+	k06_write_register(ViPipe, 0x00, 0x10);
+
 	printf("ViPipe:%d,===K06 1440P 25fps 10bit LINE Init OK!===\n", ViPipe);
 }
 
diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos.c b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos.c
index cd81e2fd9..606f9615b 100644
--- a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos.c
+++ b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos.c
@@ -64,10 +64,11 @@ static CVI_S32 cmos_get_wdr_size(VI_PIPE ViPipe, ISP_SNS_ISP_INFO_S *pstIspCfg);
 #define Q03P_FULL_LINES_MAX  (0xFFFF)
 
 /*****Q03P Register Address*****/
-#define Q03P_SHS1_ADDR		0x01
-#define Q03P_GAIN_ADDR		0x00
-#define Q03P_VMAX_ADDR		0x22
-#define Q03P_TABLE_END		0xff
+#define Q03P_SHS1_ADDR			0x01
+#define Q03P_GAIN_ADDR			0x00
+#define Q03P_VMAX_ADDR			0x22
+#define Q03P_FLIP_MIRROR_ADDR	0x12
+#define Q03P_TABLE_END			0xff
 
 #define Q03P_RES_IS_1296P(w, h)      ((w) <= 2304 && (h) <= 1296)
 
@@ -500,6 +501,8 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 			pstI2c_data[LINEAR_VMAX_1_DATA].u32RegAddr = Q03P_VMAX_ADDR + 1;
 			pstI2c_data[LINEAR_VMAX_1_DATA].u8DelayFrmNum = 2;
 
+			pstI2c_data[LINEAR_FLIP_MIRROR].u32RegAddr = Q03P_FLIP_MIRROR_ADDR;
+
 			break;
 		default:
 			CVI_TRACE_SNS(CVI_DBG_ERR, "Not support WDR: %d\n", pstSnsState->enWDRMode);
@@ -529,6 +532,7 @@ static CVI_S32 cmos_get_sns_regs_info(VI_PIPE ViPipe, ISP_SNS_SYNC_INFO_S *pstSn
 	memcpy(pstSnsSyncInfo, &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
 	memcpy(&pstSnsState->astSyncInfo[1], &pstSnsState->astSyncInfo[0], sizeof(ISP_SNS_SYNC_INFO_S));
 	pstSnsState->au32FL[1] = pstSnsState->au32FL[0];
+	pstCfg0->snsCfg.astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = CVI_FALSE;
 
 	return CVI_SUCCESS;
 }
@@ -579,12 +583,38 @@ static CVI_S32 cmos_set_image_mode(VI_PIPE ViPipe, ISP_CMOS_SENSOR_IMAGE_MODE_S
 
 static CVI_VOID sensor_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
 {
+	CVI_U8 value = q03p_read_register(ViPipe, Q03P_FLIP_MIRROR_ADDR) & ~0x30;
+
 	ISP_SNS_STATE_S *pstSnsState = CVI_NULL;
+	ISP_SNS_REGS_INFO_S *pstSnsRegsInfo = CVI_NULL;
 
 	Q03P_SENSOR_GET_CTX(ViPipe, pstSnsState);
 	CMOS_CHECK_POINTER_VOID(pstSnsState);
+
+	pstSnsRegsInfo = &pstSnsState->astSyncInfo[0].snsCfg;
+
+	/* Apply the setting on the fly  */
 	if (pstSnsState->bInit == CVI_TRUE && g_aeQ03P_MirrorFip[ViPipe] != eSnsMirrorFlip) {
-		q03p_mirror_flip(ViPipe, eSnsMirrorFlip);
+		switch (eSnsMirrorFlip) {
+		case ISP_SNS_NORMAL:
+			value |= 0x00;
+			break;
+		case ISP_SNS_MIRROR:
+			value |= 0x20;
+			break;
+		case ISP_SNS_FLIP:
+			value |= 0x10;
+			break;
+		case ISP_SNS_MIRROR_FLIP:
+			value |= 0x30;
+			break;
+		default:
+			return;
+		}
+
+		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u32Data = value;
+		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].bDropFrm = 1;
+		pstSnsRegsInfo->astI2cData[LINEAR_FLIP_MIRROR].u8DropFrmNum = 2;
 		g_aeQ03P_MirrorFip[ViPipe] = eSnsMirrorFlip;
 	}
 }
diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h
index 0e41820f2..465186df6 100644
--- a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h
+++ b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_cmos_ex.h
@@ -28,6 +28,7 @@ enum q03p_linear_regs_e {
 	LINEAR_AGAIN_DATA,
 	LINEAR_VMAX_0_DATA,
 	LINEAR_VMAX_1_DATA,
+	LINEAR_FLIP_MIRROR,
 	LINEAR_REGS_NUM
 };
 
@@ -64,7 +65,6 @@ extern CVI_U16 g_au16Q03P_L2SMode[];
 extern CVI_U8 q03p_i2c_addr;
 extern const CVI_U32 q03p_addr_byte;
 extern const CVI_U32 q03p_data_byte;
-extern void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip);
 extern void q03p_init(VI_PIPE ViPipe);
 extern void q03p_exit(VI_PIPE ViPipe);
 extern void q03p_standby(VI_PIPE ViPipe);
diff --git a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_sensor_ctl.c b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_sensor_ctl.c
index 207faafae..04bbfd2de 100644
--- a/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_sensor_ctl.c
+++ b/middleware/v2/component/isp/sensor/cv181x/soi_q03p/q03p_sensor_ctl.c
@@ -175,29 +175,6 @@ void q03p_default_reg_init(VI_PIPE ViPipe)
 	}
 }
 
-void q03p_mirror_flip(VI_PIPE ViPipe, ISP_SNS_MIRRORFLIP_TYPE_E eSnsMirrorFlip)
-{
-	CVI_U8 val = q03p_read_register(ViPipe, 0x12) & ~0x30;
-
-	switch (eSnsMirrorFlip) {
-	case ISP_SNS_NORMAL:
-		break;
-	case ISP_SNS_MIRROR:
-		val |= 0x20;
-		break;
-	case ISP_SNS_FLIP:
-		val |= 0x10;
-		break;
-	case ISP_SNS_MIRROR_FLIP:
-		val |= 0x30;
-		break;
-	default:
-		return;
-	}
-
-	q03p_write_register(ViPipe, 0x12, val);
-}
-
 int q03p_probe(VI_PIPE ViPipe)
 {
 	int nVal;
diff --git a/middleware/v2/component/panel/cv180x/bt656_tp2803.h b/middleware/v2/component/panel/cv180x/bt656_tp2803.h
index 19d784cc0..9da7dd8eb 100644
--- a/middleware/v2/component/panel/cv180x/bt656_tp2803.h
+++ b/middleware/v2/component/panel/cv180x/bt656_tp2803.h
@@ -3,7 +3,7 @@
 
 #include <linux/cvi_comm_vo.h>
 
-const struct VO_BT_PINS tp2803_pins_cfg = {
+const struct VO_PINMUX tp2803_pins_cfg = {
 	.pin_num = 9,
 	.d_pins = {
 		{VO_VIVO_D0, VO_MUX_BT_DATA0},
@@ -20,8 +20,6 @@ const struct VO_BT_PINS tp2803_pins_cfg = {
 
 const VO_BT_ATTR_S stTP2803Cfg = {
 	.pins = tp2803_pins_cfg,
-	.mode = VO_BT_MODE_656,
-	.bt_clk = VO_BT_CLK_MODE_72M,
 };
 
 #endif // _I80_PARAM_ST7789V_H_
diff --git a/middleware/v2/component/panel/cv180x/hw_mcu_st7789v3.h b/middleware/v2/component/panel/cv180x/hw_mcu_st7789v3.h
new file mode 100644
index 000000000..cdd9d3c8b
--- /dev/null
+++ b/middleware/v2/component/panel/cv180x/hw_mcu_st7789v3.h
@@ -0,0 +1,117 @@
+#ifndef _MCU_PARAM_ST7789V_H_
+#define _MCU_PARAM_ST7789V_H_
+
+#include <linux/cvi_comm_vo.h>
+
+#define COMMAND 0
+#define DATA	1
+
+const struct VO_PINMUX st7789v3_pins_cfg = {
+	.pin_num = 11,
+	.d_pins = {
+		{VO_MIPI_TXM4, VO_MUX_MCU_DATA0},
+		{VO_MIPI_TXP4, VO_MUX_MCU_DATA1},
+		{VO_MIPI_TXM3, VO_MUX_MCU_DATA2},
+		{VO_MIPI_TXP3, VO_MUX_MCU_DATA3},
+		{VO_MIPI_TXM2, VO_MUX_MCU_DATA4},
+		{VO_MIPI_TXP2, VO_MUX_MCU_DATA5},
+		{VO_MIPI_TXM1, VO_MUX_MCU_DATA6},
+		{VO_MIPI_TXP1, VO_MUX_MCU_DATA7},
+		{VO_MIPI_TXM0, VO_MUX_MCU_RD},
+		{VO_MIPI_TXP0, VO_MUX_MCU_WR},
+		{VO_VIVO_D10, VO_MUX_MCU_RS},
+	}
+};
+
+const struct VO_MCU_INSTRS st7789v3_instrs = {
+	.instr_num = 72,
+	.instr_cmd = {
+		{.delay = 0,   .data_type = COMMAND, .data = 0x11},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x35},
+		{.delay = 0,   .data_type = DATA,    .data = 0x00},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x36},//Display Setting
+		{.delay = 0,   .data_type = DATA,    .data = (1<<6)/*(1<<5)|(1<<6)*/},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x3A},
+		{.delay = 0,   .data_type = DATA,    .data = 0x05},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xB2},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x00},
+		{.delay = 0,   .data_type = DATA,    .data = 0x33},
+		{.delay = 0,   .data_type = DATA,    .data = 0x33},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xB7},
+		{.delay = 0,   .data_type = DATA,    .data = 0x75},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xBB},
+		{.delay = 0,   .data_type = DATA,    .data = 0x19},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC0},
+		{.delay = 0,   .data_type = DATA,    .data = 0x2C},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC2},
+		{.delay = 0,   .data_type = DATA,    .data = 0x01},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC3},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC4},
+		{.delay = 0,   .data_type = DATA,    .data = 0x20},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC6},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0F},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xD0},
+		{.delay = 0,   .data_type = DATA,    .data = 0xA4},
+		{.delay = 0,   .data_type = DATA,    .data = 0xA1},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xE0},//Gamma setting
+		{.delay = 0,   .data_type = DATA,    .data = 0xD0},
+		{.delay = 0,   .data_type = DATA,    .data = 0x04},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0E},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0E},
+		{.delay = 0,   .data_type = DATA,    .data = 0x29},
+		{.delay = 0,   .data_type = DATA,    .data = 0x37},
+		{.delay = 0,   .data_type = DATA,    .data = 0x44},
+		{.delay = 0,   .data_type = DATA,    .data = 0x47},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0B},
+		{.delay = 0,   .data_type = DATA,    .data = 0x17},
+		{.delay = 0,   .data_type = DATA,    .data = 0x16},
+		{.delay = 0,   .data_type = DATA,    .data = 0x1B},
+		{.delay = 0,   .data_type = DATA,    .data = 0x1F},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xE1},
+		{.delay = 0,   .data_type = DATA,    .data = 0xD0},
+		{.delay = 0,   .data_type = DATA,    .data = 0x04},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0E},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0F},
+		{.delay = 0,   .data_type = DATA,    .data = 0x29},
+		{.delay = 0,   .data_type = DATA,    .data = 0x37},
+		{.delay = 0,   .data_type = DATA,    .data = 0x44},
+		{.delay = 0,   .data_type = DATA,    .data = 0x4A},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x17},
+		{.delay = 0,   .data_type = DATA,    .data = 0x16},
+		{.delay = 0,   .data_type = DATA,    .data = 0x1B},
+		{.delay = 0,   .data_type = DATA,    .data = 0x1F},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x29},
+
+		{.delay = 0,   .data_type = COMMAND, .data = 0x2A},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },//Xstart
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },//Xend
+		{.delay = 0,   .data_type = DATA,    .data = 0xEF},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x2B},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },//Ystart
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },
+		{.delay = 0,   .data_type = DATA,    .data = 0x01},//Yend
+		{.delay = 0,   .data_type = DATA,    .data = 0x3F},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x2C},
+	}
+};
+
+const VO_HW_MCU_CFG_S st7789v3Cfg = {
+	.pins = st7789v3_pins_cfg,
+	.mode = VO_MCU_MODE_RGB565,
+	.lcd_power_gpio_num = GPIOB_03,
+	.lcd_power_avtive = GPIO_ACTIVE_HIGH,
+	.backlight_gpio_num = GPIOA_30,
+	.backlight_avtive = GPIO_ACTIVE_HIGH,
+	.reset_gpio_num = GPIOE_13,
+	.reset_avtive = GPIO_ACTIVE_LOW,
+	.instrs = st7789v3_instrs,
+};
+
+#endif // _MCU_PARAM_ST7789V_H_
diff --git a/middleware/v2/component/panel/cv180x/lvds_lcm185x56.h b/middleware/v2/component/panel/cv180x/lvds_lcm185x56.h
new file mode 100644
index 000000000..43f32f682
--- /dev/null
+++ b/middleware/v2/component/panel/cv180x/lvds_lcm185x56.h
@@ -0,0 +1,15 @@
+#ifndef _LVDS_PARAM_LCM185X56_H_
+#define _LVDS_PARAM_LCM185X56_H_
+
+#include <linux/cvi_comm_vo.h>
+
+const VO_LVDS_ATTR_S lvds_lcm185x56_cfg = {
+	.lvds_vesa_mode = VO_LVDS_MODE_JEIDA,
+	.out_bits = VO_LVDS_OUT_8BIT,
+	.chn_num = 1,
+	.data_big_endian = 0,
+	.lane_id = {VO_LVDS_LANE_0, VO_LVDS_LANE_1, VO_LVDS_LANE_CLK, VO_LVDS_LANE_2, VO_LVDS_LANE_3},
+	.lane_pn_swap = {false, false, false, false, false},
+};
+
+#endif // _LVDS_PARAM_LCM185X56_H_
diff --git a/middleware/v2/component/panel/cv181x/bt656_tp2803.h b/middleware/v2/component/panel/cv181x/bt656_tp2803.h
index 19d784cc0..9da7dd8eb 100644
--- a/middleware/v2/component/panel/cv181x/bt656_tp2803.h
+++ b/middleware/v2/component/panel/cv181x/bt656_tp2803.h
@@ -3,7 +3,7 @@
 
 #include <linux/cvi_comm_vo.h>
 
-const struct VO_BT_PINS tp2803_pins_cfg = {
+const struct VO_PINMUX tp2803_pins_cfg = {
 	.pin_num = 9,
 	.d_pins = {
 		{VO_VIVO_D0, VO_MUX_BT_DATA0},
@@ -20,8 +20,6 @@ const struct VO_BT_PINS tp2803_pins_cfg = {
 
 const VO_BT_ATTR_S stTP2803Cfg = {
 	.pins = tp2803_pins_cfg,
-	.mode = VO_BT_MODE_656,
-	.bt_clk = VO_BT_CLK_MODE_72M,
 };
 
 #endif // _I80_PARAM_ST7789V_H_
diff --git a/middleware/v2/component/panel/cv181x/hw_mcu_st7789v3.h b/middleware/v2/component/panel/cv181x/hw_mcu_st7789v3.h
new file mode 100644
index 000000000..cdd9d3c8b
--- /dev/null
+++ b/middleware/v2/component/panel/cv181x/hw_mcu_st7789v3.h
@@ -0,0 +1,117 @@
+#ifndef _MCU_PARAM_ST7789V_H_
+#define _MCU_PARAM_ST7789V_H_
+
+#include <linux/cvi_comm_vo.h>
+
+#define COMMAND 0
+#define DATA	1
+
+const struct VO_PINMUX st7789v3_pins_cfg = {
+	.pin_num = 11,
+	.d_pins = {
+		{VO_MIPI_TXM4, VO_MUX_MCU_DATA0},
+		{VO_MIPI_TXP4, VO_MUX_MCU_DATA1},
+		{VO_MIPI_TXM3, VO_MUX_MCU_DATA2},
+		{VO_MIPI_TXP3, VO_MUX_MCU_DATA3},
+		{VO_MIPI_TXM2, VO_MUX_MCU_DATA4},
+		{VO_MIPI_TXP2, VO_MUX_MCU_DATA5},
+		{VO_MIPI_TXM1, VO_MUX_MCU_DATA6},
+		{VO_MIPI_TXP1, VO_MUX_MCU_DATA7},
+		{VO_MIPI_TXM0, VO_MUX_MCU_RD},
+		{VO_MIPI_TXP0, VO_MUX_MCU_WR},
+		{VO_VIVO_D10, VO_MUX_MCU_RS},
+	}
+};
+
+const struct VO_MCU_INSTRS st7789v3_instrs = {
+	.instr_num = 72,
+	.instr_cmd = {
+		{.delay = 0,   .data_type = COMMAND, .data = 0x11},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x35},
+		{.delay = 0,   .data_type = DATA,    .data = 0x00},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x36},//Display Setting
+		{.delay = 0,   .data_type = DATA,    .data = (1<<6)/*(1<<5)|(1<<6)*/},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x3A},
+		{.delay = 0,   .data_type = DATA,    .data = 0x05},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xB2},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x00},
+		{.delay = 0,   .data_type = DATA,    .data = 0x33},
+		{.delay = 0,   .data_type = DATA,    .data = 0x33},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xB7},
+		{.delay = 0,   .data_type = DATA,    .data = 0x75},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xBB},
+		{.delay = 0,   .data_type = DATA,    .data = 0x19},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC0},
+		{.delay = 0,   .data_type = DATA,    .data = 0x2C},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC2},
+		{.delay = 0,   .data_type = DATA,    .data = 0x01},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC3},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC4},
+		{.delay = 0,   .data_type = DATA,    .data = 0x20},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xC6},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0F},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xD0},
+		{.delay = 0,   .data_type = DATA,    .data = 0xA4},
+		{.delay = 0,   .data_type = DATA,    .data = 0xA1},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xE0},//Gamma setting
+		{.delay = 0,   .data_type = DATA,    .data = 0xD0},
+		{.delay = 0,   .data_type = DATA,    .data = 0x04},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0E},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0E},
+		{.delay = 0,   .data_type = DATA,    .data = 0x29},
+		{.delay = 0,   .data_type = DATA,    .data = 0x37},
+		{.delay = 0,   .data_type = DATA,    .data = 0x44},
+		{.delay = 0,   .data_type = DATA,    .data = 0x47},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0B},
+		{.delay = 0,   .data_type = DATA,    .data = 0x17},
+		{.delay = 0,   .data_type = DATA,    .data = 0x16},
+		{.delay = 0,   .data_type = DATA,    .data = 0x1B},
+		{.delay = 0,   .data_type = DATA,    .data = 0x1F},
+		{.delay = 0,   .data_type = COMMAND, .data = 0xE1},
+		{.delay = 0,   .data_type = DATA,    .data = 0xD0},
+		{.delay = 0,   .data_type = DATA,    .data = 0x04},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0E},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0F},
+		{.delay = 0,   .data_type = DATA,    .data = 0x29},
+		{.delay = 0,   .data_type = DATA,    .data = 0x37},
+		{.delay = 0,   .data_type = DATA,    .data = 0x44},
+		{.delay = 0,   .data_type = DATA,    .data = 0x4A},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0C},
+		{.delay = 0,   .data_type = DATA,    .data = 0x17},
+		{.delay = 0,   .data_type = DATA,    .data = 0x16},
+		{.delay = 0,   .data_type = DATA,    .data = 0x1B},
+		{.delay = 0,   .data_type = DATA,    .data = 0x1F},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x29},
+
+		{.delay = 0,   .data_type = COMMAND, .data = 0x2A},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },//Xstart
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },//Xend
+		{.delay = 0,   .data_type = DATA,    .data = 0xEF},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x2B},
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },//Ystart
+		{.delay = 0,   .data_type = DATA,    .data = 0x0 },
+		{.delay = 0,   .data_type = DATA,    .data = 0x01},//Yend
+		{.delay = 0,   .data_type = DATA,    .data = 0x3F},
+		{.delay = 0,   .data_type = COMMAND, .data = 0x2C},
+	}
+};
+
+const VO_HW_MCU_CFG_S st7789v3Cfg = {
+	.pins = st7789v3_pins_cfg,
+	.mode = VO_MCU_MODE_RGB565,
+	.lcd_power_gpio_num = GPIOB_03,
+	.lcd_power_avtive = GPIO_ACTIVE_HIGH,
+	.backlight_gpio_num = GPIOA_30,
+	.backlight_avtive = GPIO_ACTIVE_HIGH,
+	.reset_gpio_num = GPIOE_13,
+	.reset_avtive = GPIO_ACTIVE_LOW,
+	.instrs = st7789v3_instrs,
+};
+
+#endif // _MCU_PARAM_ST7789V_H_
diff --git a/middleware/v2/component/panel/cv181x/lvds_lcm185x56.h b/middleware/v2/component/panel/cv181x/lvds_lcm185x56.h
new file mode 100644
index 000000000..43f32f682
--- /dev/null
+++ b/middleware/v2/component/panel/cv181x/lvds_lcm185x56.h
@@ -0,0 +1,15 @@
+#ifndef _LVDS_PARAM_LCM185X56_H_
+#define _LVDS_PARAM_LCM185X56_H_
+
+#include <linux/cvi_comm_vo.h>
+
+const VO_LVDS_ATTR_S lvds_lcm185x56_cfg = {
+	.lvds_vesa_mode = VO_LVDS_MODE_JEIDA,
+	.out_bits = VO_LVDS_OUT_8BIT,
+	.chn_num = 1,
+	.data_big_endian = 0,
+	.lane_id = {VO_LVDS_LANE_0, VO_LVDS_LANE_1, VO_LVDS_LANE_CLK, VO_LVDS_LANE_2, VO_LVDS_LANE_3},
+	.lane_pn_swap = {false, false, false, false, false},
+};
+
+#endif // _LVDS_PARAM_LCM185X56_H_
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\ No newline at end of file
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diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libraw_dump.so b/middleware/v2/cv181x/lib_musl_riscv64/libraw_dump.so
index c41136e26..43d01a098 100755
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libraw_dump.so and b/middleware/v2/cv181x/lib_musl_riscv64/libraw_dump.so differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libraw_replay.a b/middleware/v2/cv181x/lib_musl_riscv64/libraw_replay.a
index 8316cb251..1c8f4c2b4 100644
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libraw_replay.a and b/middleware/v2/cv181x/lib_musl_riscv64/libraw_replay.a differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libraw_replay.so b/middleware/v2/cv181x/lib_musl_riscv64/libraw_replay.so
index cc9554dc7..369e1514a 100755
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libraw_replay.so and b/middleware/v2/cv181x/lib_musl_riscv64/libraw_replay.so differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libsys.a b/middleware/v2/cv181x/lib_musl_riscv64/libsys.a
index 6c887300f..bafd29a34 100644
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diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libsys.so b/middleware/v2/cv181x/lib_musl_riscv64/libsys.so
index 86357b369..90cfac591 100755
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libsys.so and b/middleware/v2/cv181x/lib_musl_riscv64/libsys.so differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libvdec.a b/middleware/v2/cv181x/lib_musl_riscv64/libvdec.a
index 6fd0495e4..aa9d64bb6 100644
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libvdec.a and b/middleware/v2/cv181x/lib_musl_riscv64/libvdec.a differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libvdec.so b/middleware/v2/cv181x/lib_musl_riscv64/libvdec.so
index 67baa7889..09910f9fa 100755
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libvdec.so and b/middleware/v2/cv181x/lib_musl_riscv64/libvdec.so differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libvenc.a b/middleware/v2/cv181x/lib_musl_riscv64/libvenc.a
index 7663cd593..1fa554880 100644
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libvenc.a and b/middleware/v2/cv181x/lib_musl_riscv64/libvenc.a differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libvenc.so b/middleware/v2/cv181x/lib_musl_riscv64/libvenc.so
index c79795883..b59bc802a 100755
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libvenc.so and b/middleware/v2/cv181x/lib_musl_riscv64/libvenc.so differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libvpu.a b/middleware/v2/cv181x/lib_musl_riscv64/libvpu.a
index 1e05eee3d..13a77cd2f 100644
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libvpu.a and b/middleware/v2/cv181x/lib_musl_riscv64/libvpu.a differ
diff --git a/middleware/v2/cv181x/lib_musl_riscv64/libvpu.so b/middleware/v2/cv181x/lib_musl_riscv64/libvpu.so
index c44e641ec..3a9c2618a 100755
Binary files a/middleware/v2/cv181x/lib_musl_riscv64/libvpu.so and b/middleware/v2/cv181x/lib_musl_riscv64/libvpu.so differ
diff --git a/middleware/v2/include/cvi_sns_ctrl.h b/middleware/v2/include/cvi_sns_ctrl.h
index 92f4ad44d..5602e34ee 100644
--- a/middleware/v2/include/cvi_sns_ctrl.h
+++ b/middleware/v2/include/cvi_sns_ctrl.h
@@ -133,6 +133,7 @@ extern ISP_SNS_OBJ_S stSnsGc4023_Obj;
 extern ISP_SNS_OBJ_S stSnsGc4653_Obj;
 extern ISP_SNS_OBJ_S stSnsGc4653_Slave_Obj;
 extern ISP_SNS_OBJ_S stSnsMIS2008_Obj;
+extern ISP_SNS_OBJ_S stSnsMIS2008_1L_Obj;
 extern ISP_SNS_OBJ_S stSnsN5_Obj;
 extern ISP_SNS_OBJ_S stSnsN6_Obj;
 extern ISP_SNS_OBJ_S stSnsOs02d10_Obj;
diff --git a/middleware/v2/include/cvi_vo.h b/middleware/v2/include/cvi_vo.h
index fa4c5587e..64ea54896 100644
--- a/middleware/v2/include/cvi_vo.h
+++ b/middleware/v2/include/cvi_vo.h
@@ -261,6 +261,16 @@ CVI_S32 CVI_VO_ShowChn(VO_LAYER VoLayer, VO_CHN VoChn);
  */
 CVI_S32 CVI_VO_HideChn(VO_LAYER VoLayer, VO_CHN VoChn);
 
+/**
+ * @brief Show vo Pattern.
+ *
+ * @param VoDev(In), VoDev ID.
+ * @param PatternId(In), PatternId ID.
+ *
+ * @return CVI_S32 Return CVI_SUCCESS if succeed.
+ */
+CVI_S32 CVI_VO_ShowPattern(VO_DEV VoDev, enum VO_PATTERN_MODE PatternId);
+
 /**
  * @brief Send frame to vo channel.
  *
diff --git a/middleware/v2/include/linux/cvi_comm_vdec.h b/middleware/v2/include/linux/cvi_comm_vdec.h
index 6924aae22..7c9838d29 100644
--- a/middleware/v2/include/linux/cvi_comm_vdec.h
+++ b/middleware/v2/include/linux/cvi_comm_vdec.h
@@ -115,6 +115,7 @@ extern vdec_dbg vdecDbg;
 	CVI_TRACE(level, CVI_ID_VDEC, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
 
 #else
+#ifndef VC_DEBUG_BASIC_LEVEL
 #define CVI_VDEC_PRNT(msg, ...)	\
 			pr_info(msg, ##__VA_ARGS__)
 
@@ -161,7 +162,26 @@ extern vdec_dbg vdecDbg;
 
 #define CVI_TRACE_VDEC(level, fmt, ...)                                           \
 	CVI_TRACE(level, CVI_ID_VDEC, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
-
+#else
+#define CVI_VDEC_PRNT(msg, ...)
+#define CVI_VDEC_ERR(msg, ...)	\
+	do {	\
+		if (vdecDbg.currMask & CVI_VDEC_MASK_ERR) \
+		pr_err("[ERR] %s = %d, "msg, __func__, __LINE__, ## __VA_ARGS__); \
+	} while (0)
+#define CVI_VDEC_WARN(msg, ...)	\
+	do {	\
+		if (vdecDbg.currMask & CVI_VDEC_MASK_WARN) \
+		pr_warn("[WARN] %s = %d, "msg, __func__, __LINE__, ## __VA_ARGS__); \
+	} while (0)
+#define CVI_VDEC_DISP(msg, ...)
+#define CVI_VDEC_INFO(msg, ...)
+#define CVI_VDEC_MEM(msg, ...)
+#define CVI_VDEC_API(msg, ...)
+#define CVI_VDEC_TRACE(msg, ...)
+#define CVI_VDEC_PERF(msg, ...)
+#define CVI_TRACE_VDEC(level, fmt, ...)
+#endif
 #endif
 
 #define CVI_IO_BLOCK CVI_TRUE
diff --git a/middleware/v2/include/linux/cvi_comm_venc.h b/middleware/v2/include/linux/cvi_comm_venc.h
index f40eef8f8..0d8ba442b 100644
--- a/middleware/v2/include/linux/cvi_comm_venc.h
+++ b/middleware/v2/include/linux/cvi_comm_venc.h
@@ -196,7 +196,7 @@ extern pthread_t gs_VencTask[VENC_MAX_CHN_NUM];
 	CVI_TRACE(level, CVI_ID_VENC, "%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
 
 #else
-
+#ifndef VC_DEBUG_BASIC_LEVEL
 #define CVI_VENC_DEBUG(msg, ...)		\
 	do { \
 		if (vencDbg.currMask & CVI_VENC_MASK_DEBUG) { \
@@ -295,6 +295,45 @@ extern pthread_t gs_VencTask[VENC_MAX_CHN_NUM];
 
 #define CVI_TRACE_VENC(level, fmt, ...)                                           \
 	pr_debug("%s:%d:%s(): " fmt, __FILENAME__, __LINE__, __func__, ##__VA_ARGS__)
+
+#else
+#define CVI_VENC_DEBUG(msg, ...)		\
+	do { \
+		if (vencDbg.currMask & CVI_VENC_MASK_DEBUG) { \
+			struct timespec64 ts;	\
+			ktime_get_ts64(&ts);	\
+			pr_info("[DEBUG][%llu] %s = %d," msg, ts.tv_sec * 1000 + ts.tv_nsec / 1000000, __func__, \
+			__LINE__, ## __VA_ARGS__); \
+		} \
+	} while (0)
+#define CVI_VENC_ERR(msg, ...)		\
+	do { \
+		if (vencDbg.currMask & CVI_VENC_MASK_ERR) \
+		pr_err("[ERR] %s = %d, "msg, __func__, __LINE__, ## __VA_ARGS__); \
+	} while (0)
+#define CVI_VENC_WARN(msg, ...)		\
+	do { \
+		if (vencDbg.currMask & CVI_VENC_MASK_WARN) \
+		pr_warn("[WARN] %s = %d, "msg, __func__, __LINE__, ## __VA_ARGS__); \
+	} while (0)
+
+#define CVI_VENC_BS(msg, ...)
+#define CVI_VENC_SRC(msg, ...)
+#define CVI_VENC_PERF(msg, ...)
+#define CVI_VENC_CFG(msg, ...)
+#define CVI_VENC_FRC(msg, ...)
+#define CVI_VENC_BIND(msg, ...)
+#define CVI_VENC_INFO(msg, ...)
+#define CVI_VENC_FLOW(msg, ...)
+#define CVI_VENC_API(msg, ...)
+#define CVI_VENC_DBG(msg, ...)
+#define CVI_VENC_SYNC(msg, ...)
+#define CVI_VENC_TRACE(msg, ...)
+#define CVI_VENC_DUMP_YUV(msg, ...)
+#define CVI_VENC_DUMP_BS(msg, ...)
+#define CVI_TRACE_VENC(level, fmt, ...)
+
+#endif
 #endif
 
 // TODO: refinememt for hardcode
diff --git a/middleware/v2/include/linux/cvi_comm_vo.h b/middleware/v2/include/linux/cvi_comm_vo.h
index a3813af6f..c5aa45583 100644
--- a/middleware/v2/include/linux/cvi_comm_vo.h
+++ b/middleware/v2/include/linux/cvi_comm_vo.h
@@ -34,10 +34,13 @@ extern "C" {
 #define VO_INTF_MIPI_SLAVE (0x01L << 14)
 #define VO_INTF_HDMI (0x01L << 15)
 #define VO_INTF_I80 (0x01L << 16)
+#define VO_INTF_LVDS (0x01L << 17)
+#define VO_INTF_HW_MCU (0x01L << 18)
 
 #define VO_GAMMA_NODENUM 65
 
-#define MAX_BT_PINS 20
+#define MAX_VO_PINS 32
+#define MAX_MCU_INSTR 256
 
 typedef CVI_U32 VO_INTF_TYPE_E;
 
@@ -96,6 +99,20 @@ typedef enum _VO_CSC_MATRIX_E {
 	VO_CSC_MATRIX_BUTT
 } VO_CSC_MATRIX_E;
 
+enum VO_PATTERN_MODE {
+	VO_PAT_OFF = 0,
+	VO_PAT_SNOW,
+	VO_PAT_AUTO,
+	VO_PAT_RED,
+	VO_PAT_GREEN,
+	VO_PAT_BLUE,
+	VO_PAT_COLORBAR,
+	VO_PAT_GRAY_GRAD_H,
+	VO_PAT_GRAY_GRAD_V,
+	VO_PAT_BLACK,
+	VO_PAT_MAX,
+};
+
 typedef enum _VO_I80_FORMAT {
 	VO_I80_FORMAT_RGB444 = 0,
 	VO_I80_FORMAT_RGB565,
@@ -143,7 +160,8 @@ GPIOA_16,   GPIOA_17,   GPIOA_18,   GPIOA_19,   GPIOA_20,
 GPIOA_21,   GPIOA_22,   GPIOA_23,   GPIOA_24,   GPIOA_25,
 GPIOA_26,   GPIOA_27,   GPIOA_28,   GPIOA_29,   GPIOA_30,
 GPIOA_31,
-#ifdef ARCH_CV182X
+#if 1
+// #ifdef ARCH_CV182X
 GPIOE_00 = 380,
 GPIOE_01,   GPIOE_02,   GPIOE_03,   GPIOE_04,   GPIOE_05,
 GPIOE_06,   GPIOE_07,   GPIOE_08,   GPIOE_09,   GPIOE_10,
@@ -274,14 +292,18 @@ struct VO_LVDS_CTL_PIN_S {
 
 /* Define LVDS's config
  *
- * lvds_vesa_mode: true for VESA mode; false for JEIDA mode
+ * out_bits: 6 bit, 8 bit or 10 bit
+ * mode: LVDS_MODE_VESA for VESA mode; LVDS_MODE_JEIDA for JEIDA mode
+ * chn_num: 2 for dual link, 1 and others for single link
  * data_big_endian: true for big endian; true for little endian
  * lane_id: lane mapping, -1 no used
  * lane_pn_swap: lane pn-swap if true
+ * pixelclock: pixel clock
  */
 typedef struct _VO_LVDS_ATTR_S {
 	enum VO_LVDS_OUT_BIT_E out_bits;
-	uint8_t chn_num;
+	enum VO_LVDS_MODE_E mode;
+	CVI_U8 chn_num;
 	CVI_BOOL data_big_endian;
 	enum VO_LVDS_LANE_ID lane_id[VO_LVDS_LANE_MAX];
 	CVI_BOOL lane_pn_swap[VO_LVDS_LANE_MAX];
@@ -291,7 +313,7 @@ typedef struct _VO_LVDS_ATTR_S {
 	enum VO_LVDS_MODE_E lvds_vesa_mode;
 } VO_LVDS_ATTR_S;
 
-enum VO_TOP_MUX {
+enum VO_TOP_BT_MUX {
 	VO_MUX_BT_VS = 0,
 	VO_MUX_BT_HS,
 	VO_MUX_BT_HDE,
@@ -313,7 +335,23 @@ enum VO_TOP_MUX {
 	VO_MUX_BT_DATA15,
 	VO_MUX_TG_HS_TILE = 30,
 	VO_MUX_TG_VS_TILE,
-	VO_MUX_MAX,
+	VO_BT_MUX_MAX,
+};
+
+enum VO_TOP_MCU_MUX {
+	VO_MUX_MCU_CS = 0,
+	VO_MUX_MCU_RS,
+	VO_MUX_MCU_WR,
+	VO_MUX_MCU_RD,
+	VO_MUX_MCU_DATA0,
+	VO_MUX_MCU_DATA1,
+	VO_MUX_MCU_DATA2,
+	VO_MUX_MCU_DATA3,
+	VO_MUX_MCU_DATA4,
+	VO_MUX_MCU_DATA5,
+	VO_MUX_MCU_DATA6,
+	VO_MUX_MCU_DATA7,
+	VO_MCU_MUX_MAX,
 };
 
 enum VO_TOP_SEL {
@@ -386,42 +424,41 @@ enum VO_TOP_D_SEL {
 
 struct VO_D_REMAP {
 	enum VO_TOP_D_SEL sel;
-	enum VO_TOP_MUX mux;
+	CVI_U32 mux;
 };
 
-struct VO_BT_PINS {
+struct VO_PINMUX {
 	unsigned char pin_num;
-	struct VO_D_REMAP d_pins[MAX_BT_PINS];
+	struct VO_D_REMAP d_pins[MAX_VO_PINS];
 };
 
-enum VO_BT_MODE {
-	VO_BT_MODE_656 = 0,
-	VO_BT_MODE_1120,
-	VO_BT_MODE_601,
-	VO_BT_MODE_MAX,
-};
-
-enum VO_BT_CLK_MODE {
-	VO_BT_CLK_MODE_27M = 0,
-	VO_BT_CLK_MODE_36M,
-	VO_BT_CLK_MODE_37P125M,
-	VO_BT_CLK_MODE_72M,
-	VO_BT_CLK_MODE_74P25M,
-	VO_BT_CLK_MODE_148P5M,
-};
-
-/* Define BT's config
- *
- * bt_clk: bt clk sel
- * mode: bt mode
- * pins: bt pinmux cfg
- */
 typedef struct _VO_BT_ATTR_S {
-	enum VO_BT_CLK_MODE bt_clk;
-	enum VO_BT_MODE mode;
-	struct VO_BT_PINS pins;
+	struct VO_PINMUX pins;
 } VO_BT_ATTR_S;
 
+enum VO_MCU_MODE {
+	VO_MCU_MODE_RGB565 = 0,
+	VO_MCU_MODE_RGB888,
+	VO_MCU_MODE_MAX,
+};
+
+struct VO_MCU_INSTRS {
+	unsigned char instr_num;
+	VO_I80_INSTR_S instr_cmd[MAX_MCU_INSTR];
+};
+
+typedef struct _VO_HW_MCU_CFG_S {
+	enum VO_MCU_MODE mode;
+	struct VO_PINMUX pins;
+	CVI_U32 lcd_power_gpio_num;
+	CVI_S8 lcd_power_avtive;
+	CVI_U32 backlight_gpio_num;
+	CVI_S8 backlight_avtive;
+	CVI_U32 reset_gpio_num;
+	CVI_S8 reset_avtive;
+	struct VO_MCU_INSTRS instrs;
+} VO_HW_MCU_CFG_S;
+
 /*
  * u32BgColor: Background color of a device, in RGB format.
  * enIntfType: Type of a VO interface.
@@ -437,6 +474,7 @@ typedef struct _VO_PUB_ATTR_S {
 	VO_SYNC_INFO_S stSyncInfo;
 	union {
 		VO_I80_CFG_S sti80Cfg;
+		VO_HW_MCU_CFG_S stMcuCfg;
 		VO_LVDS_ATTR_S stLvdsAttr;
 		VO_BT_ATTR_S stBtAttr;
 	};
diff --git a/middleware/v2/include/linux/vo_disp.h b/middleware/v2/include/linux/vo_disp.h
index 59290a228..db6587d04 100644
--- a/middleware/v2/include/linux/vo_disp.h
+++ b/middleware/v2/include/linux/vo_disp.h
@@ -5,12 +5,14 @@
 #define LANE_MAX_NUM   5
 #endif
 
-#define MAX_BT_PINS 20
+#define MAX_VO_PINS 32
+#define MAX_MCU_INSTR 256
 
 enum cvi_disp_intf {
 	CVI_VIP_DISP_INTF_DSI = 0,
 	CVI_VIP_DISP_INTF_BT,
 	CVI_VIP_DISP_INTF_I80,
+	CVI_VIP_DISP_INTF_HW_MCU,
 	CVI_VIP_DISP_INTF_LVDS,
 	CVI_VIP_DISP_INTF_MAX,
 };
@@ -56,7 +58,7 @@ struct cvi_lvds_intf_cfg {
 	__s8 backlight_avtive;
 };
 
-enum sclr_top_vo_mux {
+enum sclr_top_vo_bt_mux {
 	SCLR_VO_MUX_BT_VS = 0,
 	SCLR_VO_MUX_BT_HS,
 	SCLR_VO_MUX_BT_HDE,
@@ -78,7 +80,23 @@ enum sclr_top_vo_mux {
 	SCLR_VO_MUX_BT_DATA15,
 	SCLR_VO_MUX_TG_HS_TILE = 30,
 	SCLR_VO_MUX_TG_VS_TILE,
-	SCLR_VO_MUX_MAX,
+	SCLR_VO_BT_MUX_MAX,
+};
+
+enum sclr_top_vo_mcu_mux {
+	SCLR_VO_MUX_MCU_CS = 0,
+	SCLR_VO_MUX_MCU_RS,
+	SCLR_VO_MUX_MCU_WR,
+	SCLR_VO_MUX_MCU_RD,
+	SCLR_VO_MUX_MCU_DATA0,
+	SCLR_VO_MUX_MCU_DATA1,
+	SCLR_VO_MUX_MCU_DATA2,
+	SCLR_VO_MUX_MCU_DATA3,
+	SCLR_VO_MUX_MCU_DATA4,
+	SCLR_VO_MUX_MCU_DATA5,
+	SCLR_VO_MUX_MCU_DATA6,
+	SCLR_VO_MUX_MCU_DATA7,
+	SCLR_VO_MCU_MUX_MAX,
 };
 
 enum sclr_top_vo_sel {
@@ -151,12 +169,12 @@ enum sclr_top_vo_d_sel {
 
 struct vo_d_remap {
 	enum sclr_top_vo_d_sel sel;
-	enum sclr_top_vo_mux mux;
+	__u32 mux;
 };
 
-struct bt_pins {
+struct vo_pins {
 	unsigned char pin_num;
-	struct vo_d_remap d_pins[MAX_BT_PINS];
+	struct vo_d_remap d_pins[MAX_VO_PINS];
 };
 
 enum BT_MODE {
@@ -166,22 +184,43 @@ enum BT_MODE {
 	BT_MODE_MAX,
 };
 
-enum BT_CLK_MODE {
-	BT_CLK_MODE_27M = 0,
-	BT_CLK_MODE_36M,
-	BT_CLK_MODE_37P125M,
-	BT_CLK_MODE_72M,
-	BT_CLK_MODE_74P25M,
-	BT_CLK_MODE_148P5M,
-};
-
 /*
  * @pixelclock: pixel clock in kHz
  */
 struct cvi_bt_intf_cfg {
-	__u8 bt_clk;
+	__u32 pixelclock;
 	enum BT_MODE mode;
-	struct bt_pins pins;
+	struct vo_pins pins;
+};
+
+struct cvi_i80_instr {
+	__u8	delay;
+	__u8  data_type;
+	__u8	data;
+};
+
+enum MCU_MODE {
+	MCU_MODE_RGB565 = 0,
+	MCU_MODE_RGB888,
+	MCU_MODE_MAX,
+};
+
+struct MCU_INSTRS {
+	unsigned char instr_num;
+	struct cvi_i80_instr instr_cmd[MAX_MCU_INSTR];
+};
+
+struct cvi_hw_mcu_intf_cfg {
+	enum MCU_MODE mode;
+	struct vo_pins pins;
+	__u32 lcd_power_gpio_num;
+	__s8 lcd_power_avtive;
+	__u32 backlight_gpio_num;
+	__s8 backlight_avtive;
+	__u32 reset_gpio_num;
+	__s8 reset_avtive;
+	struct MCU_INSTRS instrs;
+	__u32 pixelclock;
 };
 
 struct cvi_disp_intf_cfg {
@@ -190,6 +229,7 @@ struct cvi_disp_intf_cfg {
 		struct cvi_dsi_intf_cfg dsi_cfg;
 		struct cvi_lvds_intf_cfg lvds_cfg;
 		struct cvi_bt_intf_cfg bt_cfg;
+		struct cvi_hw_mcu_intf_cfg mcu_cfg;
 	};
 };
 
diff --git a/middleware/v2/sample/common/sample_comm.h b/middleware/v2/sample/common/sample_comm.h
index ff47dc928..f7589af72 100644
--- a/middleware/v2/sample/common/sample_comm.h
+++ b/middleware/v2/sample/common/sample_comm.h
@@ -304,6 +304,7 @@ typedef enum _SAMPLE_SNS_TYPE_E {
 
 	/* ------ WDR 2TO1 BEGIN ------*/
 	BRIGATES_BG0808_MIPI_2M_30FPS_10BIT_WDR2TO1 = SAMPLE_SNS_TYPE_LINEAR_BUTT,
+	CVSENS_CV4001_MIPI_4M_1440P_15FPS_WDR2TO1,
 	GCORE_GC2093_MIPI_2M_30FPS_10BIT_WDR2TO1,
 	GCORE_GC2093_SLAVE_MIPI_2M_30FPS_10BIT_WDR2TO1,
 	OV_OS04A10_MIPI_4M_1440P_30FPS_10BIT_WDR2TO1,
@@ -1016,6 +1017,7 @@ CVI_S32 SAMPLE_PLAT_VPSS_INIT(VPSS_GRP VpssGrp, SIZE_S stSizeIn, SIZE_S stSizeOu
 CVI_S32 SAMPLE_PLAT_VO_INIT(void);
 CVI_S32 SAMPLE_PLAT_VO_INIT_BT656(void);
 
+CVI_S32 SAMPLE_COMM_GPIO_SetValue(unsigned int gpio, unsigned int value);
 CVI_S32 SAMPLE_COMM_I2C_Write(CVI_S32 file, CVI_U16 addr, CVI_U16 reg, CVI_U16 val, CVI_U16 reg_w, CVI_U16 val_w);
 CVI_S32 SAMPLE_COMM_I2C_Read(CVI_S32 file, CVI_U16 addr, CVI_U16 reg, CVI_U16 reg_w, CVI_U8 *r_val);
 CVI_S32 SAMPLE_COMM_I2C_Open(CVI_CHAR *i2c_bus);
diff --git a/middleware/v2/sample/common/sample_common_sensor.c b/middleware/v2/sample/common/sample_common_sensor.c
index 62bbd62df..64a4cb8bb 100644
--- a/middleware/v2/sample/common/sample_common_sensor.c
+++ b/middleware/v2/sample/common/sample_common_sensor.c
@@ -210,6 +210,7 @@ static const char *snsr_type_name[SAMPLE_SNS_TYPE_BUTT] = {
 
 	/* ------ WDR 2TO1 BEGIN ------*/
 	"BRIGATES_BG0808_MIPI_2M_30FPS_10BIT_WDR2TO1",
+	"CVSENS_CV4001_MIPI_4M_1440P_15FPS_WDR2TO1",
 	"GCORE_GC2093_MIPI_2M_30FPS_10BIT_WDR2TO1",
 	"GCORE_GC2093_SLAVE_MIPI_2M_30FPS_10BIT_WDR2TO1",
 	"OV_OS04A10_MIPI_4M_1440P_30FPS_10BIT_WDR2TO1",
@@ -413,6 +414,7 @@ CVI_S32 SAMPLE_COMM_SNS_GetSize(SAMPLE_SNS_TYPE_E enMode, PIC_SIZE_E *penSize)
 	case TECHPOINT_TP2850_MIPI_4M_30FPS_8BIT:
 	case VIVO_MCS369Q_4M_30FPS_12BIT:
 	case CVSENS_CV4001_MIPI_4M_1440P_25FPS_12BIT:
+	case CVSENS_CV4001_MIPI_4M_1440P_15FPS_WDR2TO1:
 		*penSize = PIC_1440P;
 		break;
 	case SMS_SC401AI_MIPI_3M_30FPS_10BIT:
@@ -832,6 +834,7 @@ CVI_S32 SAMPLE_COMM_SNS_GetDevAttr(SAMPLE_SNS_TYPE_E enSnsType, VI_DEV_ATTR_S *p
 	case GCORE_GC4023_MIPI_4M_30FPS_10BIT:
 	// cvsens
 	case CVSENS_CV4001_MIPI_4M_1440P_25FPS_12BIT:
+	case CVSENS_CV4001_MIPI_4M_1440P_15FPS_WDR2TO1:
 		pstViDevAttr->enBayerFormat = BAYER_FORMAT_RG;
 		break;
 		// brigates
@@ -938,6 +941,9 @@ CVI_S32 SAMPLE_COMM_SNS_GetIspAttrBySns(SAMPLE_SNS_TYPE_E enSnsType, ISP_PUB_ATT
 
 	// FPS
 	switch (enSnsType) {
+	case CVSENS_CV4001_MIPI_4M_1440P_15FPS_WDR2TO1:
+		pstPubAttr->f32FrameRate = 15;
+		break;
 	case SMS_SC035GS_MIPI_480P_120FPS_12BIT:
 	case SMS_SC035GS_1L_MIPI_480P_120FPS_10BIT:
 	case SMS_SC035HGS_MIPI_480P_120FPS_12BIT:
@@ -986,6 +992,7 @@ CVI_S32 SAMPLE_COMM_SNS_GetIspAttrBySns(SAMPLE_SNS_TYPE_E enSnsType, ISP_PUB_ATT
 		pstPubAttr->f32FrameRate = 10;
 		break;
 #endif
+	case CVSENS_CV4001_MIPI_4M_1440P_25FPS_12BIT:
 	case TECHPOINT_TP2863_MIPI_1M_25FPS_8BIT:
 	case TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT:
 		pstPubAttr->f32FrameRate = 25;
@@ -1057,6 +1064,7 @@ CVI_S32 SAMPLE_COMM_SNS_GetIspAttrBySns(SAMPLE_SNS_TYPE_E enSnsType, ISP_PUB_ATT
 	case GCORE_GC4023_MIPI_4M_30FPS_10BIT:
 	case IMGDS_MIS2008_MIPI_2M_1080P_30FPS_12BIT:
 	case CVSENS_CV4001_MIPI_4M_1440P_25FPS_12BIT:
+	case CVSENS_CV4001_MIPI_4M_1440P_15FPS_WDR2TO1:
 		pstPubAttr->enBayer = BAYER_RGGB;
 		break;
 	case GCORE_GC1084_MIPI_1M_30FPS_10BIT:
@@ -1096,6 +1104,7 @@ CVI_VOID *SAMPLE_COMM_SNS_GetSnsObj(SAMPLE_SNS_TYPE_E enSnsType)
 #endif
 #if defined(SENSOR_CVSENS_CV4001)
 	case CVSENS_CV4001_MIPI_4M_1440P_25FPS_12BIT:
+	case CVSENS_CV4001_MIPI_4M_1440P_15FPS_WDR2TO1:
 		return &stSnsCV4001_Obj;
 #endif
 #if defined(SENSOR_GCORE_GC02M1)
diff --git a/middleware/v2/sample/common/sample_common_vo.c b/middleware/v2/sample/common/sample_common_vo.c
index 698b9defe..b3d276b8a 100644
--- a/middleware/v2/sample/common/sample_common_vo.c
+++ b/middleware/v2/sample/common/sample_common_vo.c
@@ -22,6 +22,8 @@
 #include "dsi_hx8394_evb.h"
 #include "i80_st7789v.h"
 #include "bt656_tp2803.h"
+#include "hw_mcu_st7789v3.h"
+#include "lvds_lcm185x56.h"
 
 static CVI_S32 sample_vo_i2c_file = -1;
 static CVI_S32 sample_vo_i2c_slave_addr;
@@ -173,6 +175,9 @@ CVI_S32 SAMPLE_COMM_VO_FillIntfAttr(VO_PUB_ATTR_S *pstPubAttr)
 	case VO_INTF_I80:
 		pstPubAttr->sti80Cfg = stI80Cfg;
 		break;
+	case VO_INTF_HW_MCU:
+		pstPubAttr->stMcuCfg = st7789v3Cfg;
+		break;
 	case VO_INTF_CVBS:
 	case VO_INTF_YPBPR:
 	case VO_INTF_VGA:
@@ -183,6 +188,7 @@ CVI_S32 SAMPLE_COMM_VO_FillIntfAttr(VO_PUB_ATTR_S *pstPubAttr)
 	case VO_INTF_LCD:
 	case VO_INTF_LCD_18BIT:
 	case VO_INTF_LCD_24BIT:
+		pstPubAttr->stLvdsAttr = lvds_lcm185x56_cfg;
 	case VO_INTF_LCD_30BIT:
 	case VO_INTF_HDMI:
 		break;
diff --git a/middleware/v2/sample/ive/.gitignore b/middleware/v2/sample/ive/.gitignore
new file mode 100644
index 000000000..0564bb2a8
--- /dev/null
+++ b/middleware/v2/sample/ive/.gitignore
@@ -0,0 +1,36 @@
+sample_add
+sample_sub
+sample_and
+sample_xor
+sample_or
+sample_erode
+sample_dilate
+sample_thresh
+sample_thresh_U16
+sample_thresh_S16
+sample_ordstatfilter
+sample_resize
+sample_sad
+sample_ncc
+sample_map
+sample_lbp
+sample_integ
+sample_hist
+sample_gradfg
+sample_csc
+sample_filter
+sample_filterandcsc
+sample_cannyhysedge
+sample_cannyedge
+sample_dma
+sample_magandang
+sample_bernsen
+sample_sobel
+sample_normgrad
+sample_16bitto8bit
+sample_stcandicorner
+sample_framediffmotion
+sample_gmm
+sample_gmm2
+sample_bgmodel
+sample_query
diff --git a/middleware/v2/sample/sample_panel/Makefile b/middleware/v2/sample/sample_panel/Makefile
new file mode 100644
index 000000000..7adc814f8
--- /dev/null
+++ b/middleware/v2/sample/sample_panel/Makefile
@@ -0,0 +1,46 @@
+SHELL = /bin/bash
+ifeq ($(PARAM_FILE), )
+	PARAM_FILE:=../../Makefile.param
+	include $(PARAM_FILE)
+endif
+include ../sample.mk
+
+PANEL_INC =../../component/panel/$(shell echo $(CHIP_ARCH) | tr A-Z a-z)
+SDIR = $(PWD)
+SRCS = $(wildcard $(SDIR)/*.c)
+INCS = -I$(MW_INC) -I$(ISP_INC) -I$(KERNEL_INC) -I$(PANEL_INC) -I../common
+OBJS = $(SRCS:.c=.o)
+DEPS = $(SRCS:.c=.d)
+
+TARGET = sample_panel
+ifeq ($(CONFIG_ENABLE_SDK_ASAN), y)
+TARGET = sample_panel_asan
+endif
+
+LIBS = -lvpu -lsys -lmipi_tx -lmisc
+
+ifeq ($(MULTI_PROCESS_SUPPORT), 1)
+DEFS += -DRPC_MULTI_PROCESS
+LIBS += -lnanomsg
+LIBS += -lvenc -lvdec -lmisc
+endif
+
+EXTRA_CFLAGS = $(INCS)
+EXTRA_LDFLAGS = $(LIBS) -lm -lpthread -latomic
+EXTRA_LDFLAGS += -lcvi_bin -lcvi_bin_isp $(ISP_LIB)
+
+.PHONY : clean all
+all: $(TARGET)
+
+$(SDIR)/%.o: $(SDIR)/%.c
+	@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -o $@ -c $<
+	@echo [$(notdir $(CC))] $(notdir $@)
+
+$(TARGET): $(OBJS) $(MW_LIB)/libvpu.a $(MW_LIB)/libsys.a $(MW_LIB)/libmipi_tx.a
+	@$(CXX) -o $@ $(OBJS) $(ELFFLAGS) $(EXTRA_LDFLAGS)
+	@echo -e $(BLUE)[LINK]$(END)[$(notdir $(CC))] $(notdir $@)
+
+clean:
+	@rm -f $(OBJS) $(DEPS) $(TARGET)
+
+-include $(DEPS)
diff --git a/middleware/v2/sample/sample_panel/sample_panel.c b/middleware/v2/sample/sample_panel/sample_panel.c
new file mode 100644
index 000000000..340ac1fdd
--- /dev/null
+++ b/middleware/v2/sample/sample_panel/sample_panel.c
@@ -0,0 +1,689 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <assert.h>
+#include <unistd.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include <inttypes.h>
+
+#include "sample_comm.h"
+#include "mipi_tx.h"
+#include "sample_panel.h"
+
+static int fd;
+
+#define MAX_OPTIONS	128
+#define LANE_MAX_NUM   5
+
+typedef enum _ARG_TYPE_ {
+	ARG_INT = 0,
+	ARG_UINT,
+	ARG_STRING,
+} ARG_TYPE;
+
+typedef struct _optionExt_ {
+	struct option opt;
+	int type;
+	int64_t min;
+	int64_t max;
+	const char *help;
+} optionExt;
+
+typedef enum {
+	DSI_PANEL_3AML069LP01G,
+	DSI_PANEL_GM8775C,
+	DSI_PANEL_HX8394_EVB,
+	DSI_PANEL_HX8399_1080P,
+	DSI_PANEL_ICN9707,
+	DSI_PANEL_ILI9881C,
+	DSI_PANEL_ILI9881D,
+	DSI_PANEL_JD9366AB,
+	DSI_PANEL_LT9611_1920x1080_60,
+	DSI_PANEL_LT9611_1920x1080_30,
+	DSI_PANEL_LT9611_1280x720_60,
+	DSI_PANEL_LT9611_1024x768_60,
+	DSI_PANEL_LT9611_1280x1024_60,
+	DSI_PANEL_LT9611_1600x1200_60,
+	DSI_PANEL_NT35521,
+	DSI_PANEL_OTA7290B_1920,
+	DSI_PANEL_OTA7290B,
+	DSI_PANEL_ST7701,
+	LVDS_PANEL_LCM185X56,
+	BT_PANEL_TP2803_BT656_1280x720_25FPS_72M,
+	I80_PANEL_ST7789V3_HW_MCU_240x320_60FPS,
+	PANEL_MAX
+} PANEL_MODEL;
+
+typedef struct _inputPara_ {
+	enum mipi_tx_lane_id    lane_id[LANE_MAX_NUM];
+	bool                    lane_pn_swap[LANE_MAX_NUM];
+	bool					lane_id_flag;
+	bool					pn_swap_flag;
+	PANEL_MODEL			panel_model;
+} inputPara;
+
+inputPara g_input_para = {
+	.panel_model = DSI_PANEL_HX8394_EVB,
+};
+
+static struct panel_desc_s g_panel_desc = {
+	.panel_mode = "HX8394_EVB",
+	.panel_type = PANEL_MODE_DSI,
+	.stdsicfg.dev_cfg = &dev_cfg_hx8394_720x1280,
+	.stdsicfg.hs_timing_cfg = &hs_timing_cfg_hx8394_720x1280,
+	.stdsicfg.dsi_init_cmds = dsi_init_cmds_hx8394_720x1280,
+	.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_hx8394_720x1280)
+};
+
+static optionExt long_option_ext[] = {
+	{{"panel",  optional_argument, NULL, 'm'},   ARG_STRING,   0,   0,
+		"choose diaply panel model"},
+	{{"laneid",    optional_argument, NULL, 'l'},   ARG_STRING,    0,   0,
+		"laneid sequence by order"},
+	{{"pnswap",    optional_argument, NULL, 'p'},   ARG_STRING,   0,   0,
+		"pnswap sequence by order"},
+	{{"dsi-control",     no_argument, NULL, 'd'}, ARG_STRING, 0,   0,
+		"set/get dsi status or settings." },
+	{{"help",      no_argument, NULL, 'h'},       ARG_STRING, 0,   0,
+		"print usage."},
+	{{NULL, 0, NULL, 0}, ARG_INT, 0, 0, "no param: just init the panel."}
+};
+
+static char *s_panel_model_type_arr[] = {
+	"3AML069LP01G",
+	"GM8775C",
+	"HX8394_EVB",
+	"HX8399_1080P",
+	"ICN9707",
+	"ILI9881C",
+	"ILI9881D",
+	"JD9366AB",
+	"LT9611_1920x1080_60",
+	"LT9611_1920x1080_30",
+	"LT9611_1280x720_60",
+	"LT9611_1024x768_60",
+	"LT9611_1280x1024_60",
+	"LT9611_1600x1200_60",
+	"NT35521",
+	"OTA7290B_1920",
+	"OTA7290B",
+	"ST7701",
+	"LCM185X56",
+	"TP2803_BT656_1280x720_25FPS_72M",
+	"ST7789V3_HW_MCU_RGB565_240x320_60FPS",
+};
+
+void printdsiHelp(void)
+{
+	printf("\n// ------------------------dsi-control------------------------\n");
+	printf(" 0: dcs send\n");
+	printf(" 1: dcs get\n");
+	printf(" 2: switch to lp\n");
+	printf(" 3: switch to hs\n");
+	printf(" 4: get hs settle settings\n");
+	printf(" 5: set hs settle settings\n");
+}
+
+void printHelp(char **argv)
+{
+	CVI_U32 idx;
+
+	printf("// ------------------------help------------------------\n");
+	printf("\noptional panel mode support list:\n");
+	for (idx = 0; idx < sizeof(s_panel_model_type_arr) / sizeof(char *); idx++) {
+		printf(" %s\n", s_panel_model_type_arr[idx]);
+	}
+
+	printf("\n.for mipi/lvds panel you can cfg lane seq or pnswap");
+	printf("\nEX.\n");
+	printf(" %s --panel=HX8394_EVB --laneid=1,2,0,3,4 --pnswap=0,0,0,0,0\n", argv[0]);
+	printf("\n.for mipi panel You can also manually set the dsi by -d");
+	printf("\nEX.\n");
+	printf(" %s -d\n\n", argv[0]);
+
+	for (idx = 0; idx < sizeof(long_option_ext) / sizeof(optionExt); idx++) {
+		if (long_option_ext[idx].opt.name == NULL) {
+			break;
+		}
+
+		printf("--%s\n", long_option_ext[idx].opt.name);
+		printf("    %s\n", long_option_ext[idx].help);
+	}
+
+	printf("// ------------------------------------------------\n");
+}
+
+int dsi_init(int devno, const struct dsc_instr *cmds, int size)
+{
+	int ret;
+
+	if (cmds == NULL) {
+		return CVI_FAILURE;
+	}
+
+	for (int i = 0; i < size; i++) {
+		const struct dsc_instr *instr = &cmds[i];
+		struct cmd_info_s cmd_info = {
+			.devno = devno,
+			.cmd_size = instr->size,
+			.data_type = instr->data_type,
+			.cmd = (void *)instr->data
+		};
+
+		ret = mipi_tx_send_cmd(fd, &cmd_info);
+		if (instr->delay)
+			usleep(instr->delay * 1000);
+
+		if (ret) {
+			printf("dsi init failed at %d instr.\n", i);
+			return ret;
+		}
+	}
+	return ret;
+}
+
+CVI_S32 SAMPLE_MIPI_TX_ENABLE(void)
+{
+	CVI_S32 ret = 0;
+
+	fd = open(MIPI_TX_NAME, O_RDWR | O_NONBLOCK, 0);
+	if (fd == -1) {
+		printf("Cannot open '%s': %d, %s\n", MIPI_TX_NAME, errno, strerror(errno));
+		return CVI_FAILURE;
+	}
+
+	ret = mipi_tx_disable(fd);
+	if (ret != CVI_SUCCESS) {
+		printf("mipi_tx_disable fail!\n");
+		return CVI_FAILURE;
+	}
+
+	ret = mipi_tx_cfg(fd, (struct combo_dev_cfg_s *)g_panel_desc.stdsicfg.dev_cfg);
+	if (ret != CVI_SUCCESS) {
+		printf("mipi_tx_cfg fail!\n");
+		return CVI_FAILURE;
+	}
+	ret = dsi_init(0, g_panel_desc.stdsicfg.dsi_init_cmds, g_panel_desc.stdsicfg.dsi_init_cmds_size);
+	if (ret != CVI_SUCCESS) {
+		printf("dsi_init fail!\n");
+		return CVI_FAILURE;
+	}
+
+	ret = mipi_tx_set_hs_settle(fd, g_panel_desc.stdsicfg.hs_timing_cfg);
+	if (ret != CVI_SUCCESS) {
+		printf("mipi_tx_set_hs_settle fail!\n");
+		return CVI_FAILURE;
+	}
+
+	ret = mipi_tx_enable(fd);
+	if (ret != CVI_SUCCESS) {
+		printf("mipi_tx_enable fail!\n");
+		return CVI_FAILURE;
+	}
+
+	printf("Init for MIPI-Driver-%s\n", g_panel_desc.panel_mode);
+
+	return CVI_SUCCESS;
+}
+
+CVI_S32 SAMPLE_PANEL_ENABLE(void)
+{
+	CVI_S32 ret = 0;
+	VO_DEV VoDev = 0;
+
+	if (g_panel_desc.panel_type == PANEL_MODE_DSI) {
+		ret = SAMPLE_MIPI_TX_ENABLE();
+		if (ret != CVI_SUCCESS) {
+			printf("SAMPLE_MIPI_TX_ENABLE fail!\n");
+			return CVI_FAILURE;
+		}
+	} else {
+		ret = CVI_VO_SetPubAttr(VoDev, &g_panel_desc.stVoPubAttr);
+		if (ret != CVI_SUCCESS) {
+			printf("failed with %#x!\n", ret);
+			return CVI_FAILURE;
+		}
+		printf("Init for Driver-%s\n", g_panel_desc.panel_mode);
+	}
+
+	ret = CVI_VO_ShowPattern(VoDev, VO_PAT_COLORBAR);
+	if (ret != CVI_SUCCESS) {
+		printf("failed with %#x!\n", ret);
+		return CVI_FAILURE;
+	}
+
+	return CVI_SUCCESS;
+}
+
+void SAMPLE_DSI_CONTROLE(void)
+{
+	CVI_U32 tmp;
+
+	do {
+		printdsiHelp();
+		printf(" others: exit\n");
+		scanf("%d", &tmp);
+		if (tmp == 0) {
+			struct cmd_info_s cmd_info;
+			CVI_U8 data[16] = { 0 };
+			int len = 0;
+
+			printf("data size:\n");
+			scanf("%d", &tmp);
+			cmd_info.cmd_size = tmp;
+
+			printf("data type: 0x\n");
+			scanf("%x", &tmp);
+			cmd_info.data_type = tmp;
+
+			do {
+				printf("data[%d]: 0x\n", len);
+				scanf("%x", &tmp);
+				data[len++] = tmp;
+			} while (len < cmd_info.cmd_size);
+			cmd_info.cmd = data;
+			mipi_tx_send_cmd(fd, &cmd_info);
+		} else if (tmp == 1) {
+			struct get_cmd_info_s cmd_info;
+			CVI_U8 data[4] = { 0 };
+
+			printf("get data size:\n");
+			scanf("%d", &tmp);
+			cmd_info.get_data_size = tmp;
+
+			printf("data type: 0x\n");
+			scanf("%x", &tmp);
+			cmd_info.data_type = tmp;
+
+			printf("data param: 0x\n");
+			scanf("%x", &tmp);
+			cmd_info.data_param = tmp;
+
+			cmd_info.get_data = data;
+			mipi_tx_recv_cmd(fd, &cmd_info);
+			printf("data[0]: %#x [1]: %#x [2]: %#x [3]: %#x\n"
+				, cmd_info.get_data[0], cmd_info.get_data[1]
+				, cmd_info.get_data[2], cmd_info.get_data[3]);
+		} else if (tmp == 2) {
+			mipi_tx_disable(fd);
+		} else if (tmp == 3) {
+			mipi_tx_enable(fd);
+		} else if (tmp == 4) {
+			struct hs_settle_s hs_cfg;
+
+			mipi_tx_get_hs_settle(fd, &hs_cfg);
+			printf("prepare(%d) zero(%d) trail(%d)\n",
+				hs_cfg.prepare, hs_cfg.zero, hs_cfg.trail);
+		} else if (tmp == 5) {
+			struct hs_settle_s hs_cfg;
+
+			printf("prepare:\n");
+			scanf("%d", &tmp);
+			hs_cfg.prepare = tmp;
+
+			printf("zero:\n");
+			scanf("%d", &tmp);
+			hs_cfg.zero = tmp;
+
+			printf("trail:\n");
+			scanf("%d", &tmp);
+			hs_cfg.trail = tmp;
+
+			mipi_tx_set_hs_settle(fd, &hs_cfg);
+		} else
+			break;
+	} while (1);
+}
+
+void SAMPLE_SET_PANEL_DESC(void)
+{
+	switch (g_input_para.panel_model) {
+	case DSI_PANEL_ILI9881C:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_ili9881c_720x1280;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_ili9881c_720x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_ili9881c_720x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_ili9881c_720x1280);
+		break;
+	case DSI_PANEL_ILI9881D:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_ili9881d_720x1280;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_ili9881d_720x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_ili9881d_720x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_ili9881d_720x1280);
+		break;
+	case DSI_PANEL_JD9366AB:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_jd9366ab_800x1280;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_jd9366ab_800x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_jd9366ab_800x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_jd9366ab_800x1280);
+		break;
+	case DSI_PANEL_NT35521:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_nt35521_800x1280;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_nt35521_800x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_nt35521_800x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_nt35521_800x1280);
+		break;
+	case DSI_PANEL_OTA7290B:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_ota7290b_320x1280;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_ota7290b_320x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_ota7290b_320x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_ota7290b_320x1280);
+		break;
+	case DSI_PANEL_OTA7290B_1920:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_ota7290b_440x1920;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_ota7290b_440x1920;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_ota7290b_440x1920;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_ota7290b_440x1920);
+		break;
+	case DSI_PANEL_ICN9707:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_icn9707_480x1920;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_icn9707_480x1920;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_icn9707_480x1920;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_icn9707_480x1920);
+		break;
+	case DSI_PANEL_3AML069LP01G:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_3AML069LP01G_600x1024;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_3AML069LP01G_600x1024;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_3AML069LP01G_600x1024;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_3AML069LP01G_600x1024);
+		break;
+	case DSI_PANEL_ST7701:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_st7701_480x800;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_st7701_480x800;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_st7701_480x800;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_480x800);
+		break;
+	case DSI_PANEL_HX8399_1080P:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_hx8399_1080x1920;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_hx8399_1080x1920;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_hx8399_1080x1920;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_hx8399_1080x1920);
+		break;
+	case DSI_PANEL_GM8775C:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_gm8775c;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_gm8775c;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_gm8775c;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_gm8775c);
+		break;
+	case DSI_PANEL_LT9611_1920x1080_60:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_lt9611_1920x1080_60Hz;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_lt9611;
+		g_panel_desc.stdsicfg.dsi_init_cmds = NULL;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = 0;
+		break;
+	case DSI_PANEL_LT9611_1920x1080_30:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_lt9611_1920x1080_30Hz;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_lt9611;
+		g_panel_desc.stdsicfg.dsi_init_cmds = NULL;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = 0;
+		break;
+	case DSI_PANEL_LT9611_1280x720_60:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_lt9611_1280x720_60Hz;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_lt9611;
+		g_panel_desc.stdsicfg.dsi_init_cmds = NULL;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = 0;
+		break;
+	case DSI_PANEL_LT9611_1024x768_60:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_lt9611_1024x768_60Hz;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_lt9611;
+		g_panel_desc.stdsicfg.dsi_init_cmds = NULL;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = 0;
+		break;
+	case DSI_PANEL_LT9611_1280x1024_60:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_lt9611_1280x1024_60Hz;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_lt9611;
+		g_panel_desc.stdsicfg.dsi_init_cmds = NULL;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = 0;
+		break;
+	case DSI_PANEL_LT9611_1600x1200_60:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_lt9611_1600x1200_60Hz;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_lt9611;
+		g_panel_desc.stdsicfg.dsi_init_cmds = NULL;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = 0;
+		break;
+	case DSI_PANEL_HX8394_EVB:
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_hx8394_720x1280;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_hx8394_720x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_hx8394_720x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_hx8394_720x1280);
+		break;
+	case LVDS_PANEL_LCM185X56:
+		g_panel_desc.panel_type = PANEL_MODE_LVDS;
+		g_panel_desc.stVoPubAttr.enIntfType = VO_INTF_LCD_24BIT;
+		g_panel_desc.stVoPubAttr.enIntfSync = VO_OUTPUT_USER;
+		VO_SYNC_INFO_S stLcm185x56_SyncInfo = {.bSynm = 1, .bIop = 1, .u16FrameRate = 60
+		, .u16Vact = 768, .u16Vbb = 20, .u16Vfb = 10
+		, .u16Hact = 1366, .u16Hbb = 100, .u16Hfb = 88
+		, .u16Vpw = 2, .u16Hpw = 20, .bIdv = 0, .bIhs = 0, .bIvs = 0};
+		g_panel_desc.stVoPubAttr.stSyncInfo = stLcm185x56_SyncInfo;
+		g_panel_desc.stVoPubAttr.stLvdsAttr = lvds_lcm185x56_cfg;
+		break;
+	case BT_PANEL_TP2803_BT656_1280x720_25FPS_72M:
+		g_panel_desc.panel_type = PANEL_MODE_BT;
+		g_panel_desc.stVoPubAttr.enIntfType = VO_INTF_BT656;
+		g_panel_desc.stVoPubAttr.enIntfSync = VO_OUTPUT_USER;
+		VO_SYNC_INFO_S stTp2803_SyncInfo = {.bSynm = 1, .bIop = 1, .u16FrameRate = 50
+		, .u16Vact = 720, .u16Vbb = 20, .u16Vfb = 5
+		, .u16Hact = 1280, .u16Hbb = 200, .u16Hfb = 400
+		, .u16Vpw = 5, .u16Hpw = 40, .bIdv = 0, .bIhs = 0, .bIvs = 0};
+		g_panel_desc.stVoPubAttr.stSyncInfo = stTp2803_SyncInfo;
+		g_panel_desc.stVoPubAttr.stBtAttr = stTP2803Cfg;
+		break;
+	case I80_PANEL_ST7789V3_HW_MCU_240x320_60FPS:
+		g_panel_desc.panel_type = PANEL_MODE_MCU;
+		g_panel_desc.stVoPubAttr.enIntfType = VO_INTF_HW_MCU;
+		g_panel_desc.stVoPubAttr.enIntfSync = VO_OUTPUT_USER;
+		VO_SYNC_INFO_S st7789V3_SyncInfo = {.bSynm = 1, .bIop = 1, .u16FrameRate = 60
+		, .u16Vact = 320, .u16Vbb = 0, .u16Vfb = 32
+		, .u16Hact = 240, .u16Hbb = 0, .u16Hfb = 16
+		, .u16Vpw = 2, .u16Hpw = 2, .bIdv = 0, .bIhs = 1, .bIvs = 1};
+		g_panel_desc.stVoPubAttr.stSyncInfo = st7789V3_SyncInfo;
+		g_panel_desc.stVoPubAttr.stMcuCfg = st7789v3Cfg;
+		break;
+	default:
+		printf("default\n");
+		g_panel_desc.panel_type = PANEL_MODE_DSI;
+		g_panel_desc.stdsicfg.dev_cfg = &dev_cfg_hx8394_720x1280;
+		g_panel_desc.stdsicfg.hs_timing_cfg = &hs_timing_cfg_hx8394_720x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds = dsi_init_cmds_hx8394_720x1280;
+		g_panel_desc.stdsicfg.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_hx8394_720x1280);
+		break;
+	}
+	if (g_input_para.pn_swap_flag) {
+		if (g_panel_desc.panel_type == PANEL_MODE_LVDS) {
+			for (CVI_U32 i = 0; i < LANE_MAX_NUM; i++) {
+				g_panel_desc.stVoPubAttr.stLvdsAttr.lane_pn_swap[i] =
+				(enum VO_LVDS_LANE_ID)g_input_para.lane_pn_swap[i];
+			}
+		} else if (g_panel_desc.panel_type == PANEL_MODE_DSI) {
+			for (CVI_U32 i = 0; i < LANE_MAX_NUM; i++) {
+				g_panel_desc.stdsicfg.dev_cfg->lane_pn_swap[i] = g_input_para.lane_pn_swap[i];
+			}
+		}
+	}
+	if (g_input_para.lane_id_flag) {
+		if (g_panel_desc.panel_type == PANEL_MODE_LVDS) {
+			for (CVI_U32 i = 0; i < LANE_MAX_NUM; i++) {
+				g_panel_desc.stVoPubAttr.stLvdsAttr.lane_id[i] =
+				(enum VO_LVDS_LANE_ID)g_input_para.lane_id[i];
+			}
+		} else if (g_panel_desc.panel_type == PANEL_MODE_DSI) {
+			for (CVI_U32 i = 0; i < LANE_MAX_NUM; i++) {
+				g_panel_desc.stdsicfg.dev_cfg->lane_id[i] = g_input_para.lane_id[i];
+			}
+		}
+	}
+}
+
+CVI_S32 SAMPLE_SET_PANEL_MODEL(char *pinput_str)
+{
+	CVI_S32 i = 0;
+	bool is_find = false;
+	PANEL_MODEL panel_model = DSI_PANEL_HX8394_EVB;
+
+	for (i = 0; i < PANEL_MAX; i++) {
+		if (strcmp(pinput_str, s_panel_model_type_arr[i]) == 0) {
+			is_find = true;
+			break;
+		}
+	}
+
+	if (is_find) {
+		panel_model = (PANEL_MODEL)i;
+	} else {
+		return CVI_FAILURE;
+	}
+
+	g_input_para.panel_model = panel_model;
+	g_panel_desc.panel_mode = s_panel_model_type_arr[i];
+	return CVI_SUCCESS;
+}
+
+CVI_S32 SAMPLE_SET_LANEID(char *pLaneid)
+{
+	CVI_S32 lane_id[] = {0, 0, 0, 0, 0};
+
+	if (pLaneid == NULL)
+		return CVI_FAILURE;
+
+	CVI_S32 n = sscanf(pLaneid, "%02d,%02d,%02d,%02d,%02d",
+		&lane_id[0], &lane_id[1], &lane_id[2], &lane_id[3], &lane_id[4]);
+
+	if (n != sizeof(lane_id)/sizeof(CVI_S32)) {
+		return CVI_FAILURE;
+	}
+	g_input_para.lane_id_flag = true;
+	for (CVI_U32 i = 0; i < sizeof(lane_id)/sizeof(CVI_S32); i++) {
+		if (lane_id[i] < -1 || lane_id[i] > 5) {
+			return CVI_FAILURE;
+		}
+		g_input_para.lane_id[i] = lane_id[i];
+	}
+
+	return CVI_SUCCESS;
+}
+
+CVI_S32 SAMPLE_SET_PNSWAP(char *pPnswap)
+{
+	CVI_U32 pnswap[] = {0, 0, 0, 0, 0};
+
+	if (pPnswap == NULL)
+		return CVI_FAILURE;
+
+	CVI_S32 n = sscanf(pPnswap, "%02d,%02d,%02d,%02d,%02d",
+		&pnswap[0], &pnswap[1], &pnswap[2], &pnswap[3], &pnswap[4]);
+
+	if (n != sizeof(pnswap)/sizeof(CVI_U32)) {
+		return CVI_FAILURE;
+	}
+	g_input_para.pn_swap_flag = true;
+	for (CVI_U32 i = 0; i < sizeof(pnswap)/sizeof(CVI_U32); i++) {
+		if ((pnswap[i] != 0) && (pnswap[i] != 1)) {
+			return CVI_FAILURE;
+		}
+		g_input_para.lane_pn_swap[i] = (bool)(pnswap[i]);
+	}
+
+	return CVI_SUCCESS;
+}
+
+int main(int argc, char *argv[])
+{
+	if (argc == 1) {
+		printHelp(argv);
+		return CVI_SUCCESS;
+	}
+
+	struct option long_options[MAX_OPTIONS + 1];
+	CVI_S32 ch, idx, ret;
+
+	memset((void *)long_options, 0, sizeof(long_options));
+
+	for (idx = 0; idx < MAX_OPTIONS; idx++) {
+		if (long_option_ext[idx].opt.name == NULL)
+			break;
+
+		if (idx >= MAX_OPTIONS) {
+			printf("too many options\n");
+			return -1;
+		}
+
+		memcpy(&long_options[idx], &long_option_ext[idx].opt, sizeof(struct option));
+	}
+
+	optind = 0;
+	while ((ch = getopt_long(argc, argv, "dh", long_options, &idx)) != -1) {
+		switch (ch) {
+		case 'l':
+			ret = SAMPLE_SET_LANEID(optarg);
+			if (ret != CVI_SUCCESS) {
+				printf("invalid laneid parameter\n");
+				return ret;
+			}
+			break;
+		case 'p':
+			ret = SAMPLE_SET_PNSWAP(optarg);
+			if (ret != CVI_SUCCESS) {
+				printf("invalid pnswap parameter\n");
+				return ret;
+			}
+			break;
+		case 'm':
+			ret = SAMPLE_SET_PANEL_MODEL(optarg);
+			if (ret != CVI_SUCCESS) {
+				printf("invalid input panel model\n");
+				return ret;
+			}
+			break;
+		case 'd':
+			if (argc > 2) {
+				printf("usage:%s -d. -d can't use in the same time with other command\n", argv[0]);
+				return CVI_FAILURE;
+			}
+			SAMPLE_DSI_CONTROLE();
+			break;
+		case 'h':
+			printHelp(argv);
+			return CVI_SUCCESS;
+		default:
+			printf("ch = %c\n", ch);
+			printHelp(argv);
+			return CVI_FAILURE;
+		}
+	}
+
+	if (optind < argc) {
+		printHelp(argv);
+	}
+
+	SAMPLE_SET_PANEL_DESC();
+	SAMPLE_PANEL_ENABLE();
+
+	while (1) {
+		sleep(1);
+	}
+
+	return CVI_SUCCESS;
+}
\ No newline at end of file
diff --git a/middleware/v2/sample/sample_panel/sample_panel.h b/middleware/v2/sample/sample_panel/sample_panel.h
new file mode 100644
index 000000000..c1a87d13b
--- /dev/null
+++ b/middleware/v2/sample/sample_panel/sample_panel.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
+ *
+ * File Name: sample_dsi_panel.h
+ * Description:
+ */
+
+#ifndef __SAMPLE_DSI_PANEL_H__
+#define __SAMPLE_DSI_PANEL_H__
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif
+#endif /* End of #ifdef __cplusplus */
+
+#include <linux/cvi_comm_vo.h>
+#include "dsi_hx8394_evb.h"
+#include "dsi_ili9881c.h"
+#include "dsi_ili9881d.h"
+#include "dsi_jd9366ab.h"
+#include "dsi_nt35521.h"
+#include "dsi_ota7290b.h"
+#include "dsi_ota7290b_1920.h"
+#include "dsi_icn9707.h"
+#include "dsi_3aml069lp01g.h"
+#include "dsi_st7701.h"
+#include "dsi_hx8399_1080p.h"
+#include "dsi_gm8775c.h"
+#include "dsi_lt9611.h"
+#include "lvds_lcm185x56.h"
+#include "hw_mcu_st7789v3.h"
+#include "bt656_tp2803.h"
+
+typedef enum {
+	PANEL_MODE_DSI,
+	PANEL_MODE_LVDS,
+	PANEL_MODE_BT,
+	PANEL_MODE_MCU,
+} PANEL_TYPE;
+
+typedef struct dsi_panel_desc_s {
+	struct combo_dev_cfg_s *dev_cfg;
+	const struct hs_settle_s *hs_timing_cfg;
+	const struct dsc_instr *dsi_init_cmds;
+	int dsi_init_cmds_size;
+} dsi_panel_desc;
+
+struct panel_desc_s {
+	char *panel_mode;
+	PANEL_TYPE panel_type;
+	union {
+		dsi_panel_desc stdsicfg;
+		VO_PUB_ATTR_S stVoPubAttr;
+	};
+};
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif
+#endif /* End of #ifdef __cplusplus */
+
+#endif
diff --git a/middleware/v2/sample/tp2863_tp2803/Makefile b/middleware/v2/sample/tp2863_tp2803/Makefile
deleted file mode 100644
index 050d88fc9..000000000
--- a/middleware/v2/sample/tp2863_tp2803/Makefile
+++ /dev/null
@@ -1,64 +0,0 @@
-SHELL = /bin/bash
-ifeq ($(PARAM_FILE), )
-	PARAM_FILE:=../../Makefile.param
-	include $(PARAM_FILE)
-endif
-include ../sample.mk
-
-SDIR = $(PWD)
-SRCS = $(wildcard $(SDIR)/*.c)
-INCS = -I$(MW_INC) -I$(ISP_INC) -I../common/ -I$(KERNEL_INC)
-OBJS = $(SRCS:.c=.o)
-DEPS = $(SRCS:.c=.d)
-
-TARGET = sample_test_tp2863_tp2803
-ifeq ($(CONFIG_ENABLE_SDK_ASAN), y)
-TARGET = sample_test_tp2863_tp2803_asan
-endif
-
-PKG_CONFIG_PATH = $(MW_PATH)/pkgconfig
-REQUIRES = cvi_common cvi_sample
-
-MW_LIBS = $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) pkg-config --libs --define-variable=mw_dir=$(MW_PATH) $(REQUIRES))
-
-LIBS = $(MW_LIBS)
-ifeq ($(MULTI_PROCESS_SUPPORT), 1)
-DEFS += -DRPC_MULTI_PROCESS
-LIBS += -lnanomsg
-endif
-
-EXTRA_CFLAGS = $(INCS) $(DEFS)
-EXTRA_LDFLAGS = $(LIBS) -lpthread -lm -lini
-
-# IVE_SUPPORT = 1
-ifeq ($(IVE_SUPPORT), 1)
-CFLAGS += -DIVE_SUPPORT
-
-IVE_PATH = $(MW_PATH)/../install/soc_cv1835_wevb_0002a_spinand/tpu_64/cvitek_ive_sdk
-EXTRA_CFLAGS += -I$(IVE_PATH)/include/ive
-EXTRA_LDFLAGS += -L$(IVE_PATH)/lib -lcvi_ive_tpu-static
-
-TPU_PATH = $(MW_PATH)/../install/soc_cv1835_wevb_0002a_spinand/tpu_64/cvitek_tpu_sdk
-EXTRA_CFLAGS += -I$(TPU_PATH)/include
-EXTRA_LDFLAGS += -L$(TPU_PATH)/lib -lcviruntime-static -lcvimath-static -lcvikernel-static -lcnpy -lglog -lz
-endif
-
-.PHONY : clean all
-all: $(TARGET)
-
-$(COMMON_DIR)/%.o: $(COMMON_DIR)/%.c
-	@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -o $@ -c $<
-	@echo [$(notdir $(CC))] $(notdir $@)
-
-$(SDIR)/%.o: $(SDIR)/%.c
-	@$(CC) $(DEPFLAGS) $(CFLAGS) $(EXTRA_CFLAGS) -o $@ -c $<
-	@echo [$(notdir $(CC))] $(notdir $@)
-
-$(TARGET): $(COMM_OBJ) $(OBJS) $(ISP_OBJ) $(MW_LIB)/libvpu.a $(MW_LIB)/libsys.a
-	@$(CXX) -o $@ -Wl,--start-group $(OBJS) $(COMM_OBJS) -lsys $(MW_LIB)/libsys.a -Wl,--end-group $(ELFFLAGS) $(EXTRA_LDFLAGS)
-	@echo -e $(BLUE)[LINK]$(END)[$(notdir $(CXX))] $(notdir $@)
-
-clean:
-	@rm -f $(OBJS) $(DEPS) $(COMM_OBJ) $(COMM_DEPS) $(TARGET)
-
--include $(DEPS)
diff --git a/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.c b/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.c
deleted file mode 100644
index 28239c0ef..000000000
--- a/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.c
+++ /dev/null
@@ -1,280 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <stdbool.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <errno.h>
-#include <unistd.h>
-#include <sys/time.h>
-#include <sys/param.h>
-#include <sys/prctl.h>
-#include <inttypes.h>
-
-#include "cvi_buffer.h"
-#include "cvi_ae_comm.h"
-#include "cvi_awb_comm.h"
-#include "cvi_comm_isp.h"
-
-#include "sample_comm.h"
-#include "sample_vio_tp2863_tp2803.h"
-
-#define FILENAME "testpic.yuv"
-
-VI_PIPE ViPipe = 0;
-VI_CHN ViChn = 0;
-SAMPLE_VI_CONFIG_S stViConfig;
-VPSS_GRP VpssGrp = 0;
-VPSS_CHN VpssChn = VPSS_CHN0;
-CVI_BOOL abChnEnable[VPSS_MAX_PHY_CHN_NUM] = {0};
-SAMPLE_VO_CONFIG_S stVoConfig;
-VO_CHN VoChn = 0;
-
-CVI_S32 SAMPLE_VIO(void)
-{
-	SAMPLE_SNS_TYPE_E  enSnsType	    = TECHPOINT_TP2863_MIPI_2M_25FPS_8BIT;
-	WDR_MODE_E	   enWDRMode	    = WDR_MODE_NONE;
-	DYNAMIC_RANGE_E    enDynamicRange   = DYNAMIC_RANGE_SDR8;
-	PIXEL_FORMAT_E     enPixFormat	    = PIXEL_FORMAT_UYVY;
-	VIDEO_FORMAT_E     enVideoFormat    = VIDEO_FORMAT_LINEAR;
-	COMPRESS_MODE_E    enCompressMode   = COMPRESS_MODE_NONE;
-	VI_VPSS_MODE_E	   enMastPipeMode   = VI_OFFLINE_VPSS_OFFLINE;
-
-	VB_CONFIG_S        stVbConf;
-	PIC_SIZE_E         enPicSize;
-	CVI_U32	       u32BlkSize;
-	SIZE_S stSize;
-	CVI_S32 s32Ret = CVI_SUCCESS;
-
-	VI_DEV ViDev = 0;
-	CVI_S32 s32WorkSnsId = 0;
-	VI_PIPE_ATTR_S     stPipeAttr;
-
-	/************************************************
-	 * step1:  Config VI
-	 ************************************************/
-	SAMPLE_COMM_VI_GetSensorInfo(&stViConfig);
-
-	stViConfig.astViInfo[s32WorkSnsId].stSnsInfo.enSnsType	     = enSnsType;
-	stViConfig.s32WorkingViNum				     = 1;
-	stViConfig.as32WorkingViId[0]				     = 0;
-	stViConfig.astViInfo[s32WorkSnsId].stSnsInfo.MipiDev	     = 0xFF;
-	stViConfig.astViInfo[s32WorkSnsId].stSnsInfo.s32BusId	     = 3;
-	stViConfig.astViInfo[s32WorkSnsId].stDevInfo.ViDev	     = ViDev;
-	stViConfig.astViInfo[s32WorkSnsId].stDevInfo.enWDRMode	     = enWDRMode;
-	stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.enMastPipeMode = enMastPipeMode;
-	stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.aPipe[0]	     = ViPipe;
-	stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.aPipe[1]	     = -1;
-	stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.aPipe[2]	     = -1;
-	stViConfig.astViInfo[s32WorkSnsId].stPipeInfo.aPipe[3]	     = -1;
-	stViConfig.astViInfo[s32WorkSnsId].stChnInfo.ViChn	     = ViChn;
-	stViConfig.astViInfo[s32WorkSnsId].stChnInfo.enPixFormat     = enPixFormat;
-	stViConfig.astViInfo[s32WorkSnsId].stChnInfo.enDynamicRange  = enDynamicRange;
-	stViConfig.astViInfo[s32WorkSnsId].stChnInfo.enVideoFormat   = enVideoFormat;
-	stViConfig.astViInfo[s32WorkSnsId].stChnInfo.enCompressMode  = enCompressMode;
-
-	/************************************************
-	 * step2:  Get input size
-	 ************************************************/
-	s32Ret = SAMPLE_COMM_VI_GetSizeBySensor(stViConfig.astViInfo[s32WorkSnsId].stSnsInfo.enSnsType, &enPicSize);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("SAMPLE_COMM_VI_GetSizeBySensor failed with %#x\n", s32Ret);
-		return s32Ret;
-	}
-
-	s32Ret = SAMPLE_COMM_SYS_GetPicSize(enPicSize, &stSize);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("SAMPLE_COMM_SYS_GetPicSize failed with %#x\n", s32Ret);
-		return s32Ret;
-	}
-
-	/************************************************
-	 * step3:  Init SYS and common VB
-	 ************************************************/
-	memset(&stVbConf, 0, sizeof(VB_CONFIG_S));
-	stVbConf.u32MaxPoolCnt		= 1;
-
-	u32BlkSize = COMMON_GetPicBufferSize(stSize.u32Width, stSize.u32Height, enPixFormat, DATA_BITWIDTH_8
-					    , enCompressMode, DEFAULT_ALIGN);
-	stVbConf.astCommPool[0].u32BlkSize	= u32BlkSize;
-	stVbConf.astCommPool[0].u32BlkCnt	= 16;
-	SAMPLE_PRT("common pool[0] BlkSize %d\n", u32BlkSize);
-
-	s32Ret = SAMPLE_COMM_SYS_Init(&stVbConf);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("system init failed with %#x\n", s32Ret);
-		return -1;
-	}
-
-	/************************************************
-	 * step4:  Init VI ISP
-	 ************************************************/
-	s32Ret = SAMPLE_COMM_VI_StartSensor(&stViConfig);
-	if (s32Ret != CVI_SUCCESS) {
-		CVI_TRACE_LOG(CVI_DBG_ERR, "system start sensor failed with %#x\n", s32Ret);
-		return s32Ret;
-	}
-	s32Ret = SAMPLE_COMM_VI_StartDev(&stViConfig.astViInfo[ViDev]);
-	if (s32Ret != CVI_SUCCESS) {
-		CVI_TRACE_LOG(CVI_DBG_ERR, "VI_StartDev failed with %#x!\n", s32Ret);
-		return s32Ret;
-	}
-	s32Ret = SAMPLE_COMM_VI_StartMIPI(&stViConfig);
-	if (s32Ret != CVI_SUCCESS) {
-		CVI_TRACE_LOG(CVI_DBG_ERR, "system start MIPI failed with %#x\n", s32Ret);
-		return s32Ret;
-	}
-
-	stPipeAttr.bYuvSkip = CVI_FALSE;
-	stPipeAttr.u32MaxW = stSize.u32Width;
-	stPipeAttr.u32MaxH = stSize.u32Height;
-	stPipeAttr.enPixFmt = PIXEL_FORMAT_RGB_BAYER_12BPP;
-	stPipeAttr.enBitWidth = DATA_BITWIDTH_12;
-	stPipeAttr.stFrameRate.s32SrcFrameRate = -1;
-	stPipeAttr.stFrameRate.s32DstFrameRate = -1;
-	stPipeAttr.bYuvBypassPath = CVI_TRUE;
-	stPipeAttr.bNrEn = CVI_TRUE;
-	s32Ret = CVI_VI_CreatePipe(ViPipe, &stPipeAttr);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("CVI_VI_CreatePipe failed with %#x!\n", s32Ret);
-		return s32Ret;
-	}
-
-	s32Ret = CVI_VI_StartPipe(ViPipe);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("CVI_VI_StartPipe failed with %#x!\n", s32Ret);
-		return s32Ret;
-	}
-
-	s32Ret = CVI_VI_GetPipeAttr(ViPipe, &stPipeAttr);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("CVI_VI_StartPipe failed with %#x!\n", s32Ret);
-		return s32Ret;
-	}
-
-	s32Ret = SAMPLE_COMM_VI_CreateIsp(&stViConfig);
-	if (s32Ret != CVI_SUCCESS) {
-		CVI_TRACE_LOG(CVI_DBG_ERR, "VI_CreateIsp failed with %#x!\n", s32Ret);
-		return s32Ret;
-	}
-
-	SAMPLE_COMM_VI_StartViChn(&stViConfig);
-
-	/************************************************
-	 * step5:  Init VPSS
-	 ************************************************/
-	VPSS_GRP_ATTR_S    stVpssGrpAttr;
-	VPSS_CHN_ATTR_S    astVpssChnAttr[VPSS_MAX_PHY_CHN_NUM] = {0};
-
-	stVpssGrpAttr.stFrameRate.s32SrcFrameRate    = -1;
-	stVpssGrpAttr.stFrameRate.s32DstFrameRate    = -1;
-	stVpssGrpAttr.enPixelFormat                  = PIXEL_FORMAT_UYVY;
-	stVpssGrpAttr.u32MaxW                        = stSize.u32Width;
-	stVpssGrpAttr.u32MaxH                        = stSize.u32Height;
-	stVpssGrpAttr.u8VpssDev                      = 0;
-
-	astVpssChnAttr[VpssChn].u32Width                    = 1280;
-	astVpssChnAttr[VpssChn].u32Height                   = 720;
-	astVpssChnAttr[VpssChn].enVideoFormat               = VIDEO_FORMAT_LINEAR;
-	astVpssChnAttr[VpssChn].enPixelFormat               = PIXEL_FORMAT_NV21;
-	astVpssChnAttr[VpssChn].stFrameRate.s32SrcFrameRate = -1;
-	astVpssChnAttr[VpssChn].stFrameRate.s32DstFrameRate = -1;
-	astVpssChnAttr[VpssChn].u32Depth                    = 0;
-	astVpssChnAttr[VpssChn].bMirror                     = CVI_FALSE;
-	astVpssChnAttr[VpssChn].bFlip                       = CVI_FALSE;
-	astVpssChnAttr[VpssChn].stAspectRatio.enMode        = ASPECT_RATIO_NONE;
-	astVpssChnAttr[VpssChn].stNormalize.bEnable         = CVI_FALSE;
-
-	/*start vpss*/
-	abChnEnable[0] = CVI_TRUE;
-	s32Ret = SAMPLE_COMM_VPSS_Init(VpssGrp, abChnEnable, &stVpssGrpAttr, astVpssChnAttr);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("init vpss group failed. s32Ret: 0x%x !\n", s32Ret);
-		return s32Ret;
-	}
-
-	s32Ret = SAMPLE_COMM_VPSS_Start(VpssGrp, abChnEnable, &stVpssGrpAttr, astVpssChnAttr);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("start vpss group failed. s32Ret: 0x%x !\n", s32Ret);
-		return s32Ret;
-	}
-
-	s32Ret = SAMPLE_COMM_VI_Bind_VPSS(ViPipe, ViChn, VpssGrp);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("vi bind vpss failed. s32Ret: 0x%x !\n", s32Ret);
-		return s32Ret;
-	}
-
-	/************************************************
-	 * step6:  Init VO
-	 ************************************************/
-	RECT_S stDefDispRect  = {0, 0, 1280, 720};
-	SIZE_S stDefImageSize = {1280, 720};
-
-	s32Ret = SAMPLE_COMM_VO_GetDefConfig(&stVoConfig);
-	if (s32Ret != CVI_SUCCESS) {
-		CVI_TRACE_LOG(CVI_DBG_ERR, "SAMPLE_COMM_VO_GetDefConfig failed with %#x\n", s32Ret);
-		return s32Ret;
-	}
-
-	stVoConfig.VoDev	 = 0;
-	stVoConfig.stVoPubAttr.enIntfType  = VO_INTF_BT656;
-	stVoConfig.stVoPubAttr.enIntfSync  = VO_OUTPUT_720P50;
-	stVoConfig.stDispRect	 = stDefDispRect;
-	stVoConfig.stImageSize	 = stDefImageSize;
-	stVoConfig.enPixFormat	 = PIXEL_FORMAT_NV21;
-	stVoConfig.enVoMode	 = VO_MODE_1MUX;
-
-	s32Ret = SAMPLE_COMM_VO_StartVO(&stVoConfig);
-	if (s32Ret != CVI_SUCCESS) {
-		SAMPLE_PRT("SAMPLE_COMM_VO_StartVO failed with %#x\n", s32Ret);
-		return s32Ret;
-	}
-
-	SAMPLE_COMM_VPSS_Bind_VO(VpssGrp, VpssChn, 0, 0);
-
-	// s32Ret = SAMPLE_COMM_VPSS_SendFrame(VpssGrp, &stSize, PIXEL_FORMAT_UYVY, FILENAME);
-	// if (s32Ret != CVI_SUCCESS) {
-	// 	SAMPLE_PRT("SAMPLE_COMM_VPSS_SendFrame for grp0 chn0. s32Ret: 0x%x !\n", s32Ret);
-	// 	return s32Ret;
-	// }
-
-	// VIDEO_FRAME_INFO_S stVideoFrame;
-	// s32Ret = CVI_VPSS_GetChnFrame(VpssGrp, VpssChn, &stVideoFrame, -1/*10000*/);
-	// if (s32Ret != CVI_SUCCESS) {
-	// 	SAMPLE_PRT("CVI_VPSS_GetChnFrame for grp0 chn0. s32Ret: 0x%x !\n", s32Ret);
-	// 	return s32Ret;
-	// }
-
-	// s32Ret = SAMPLE_COMM_FRAME_SaveToFile("vpss.yuv", &stVideoFrame);
-	// if (s32Ret != CVI_SUCCESS) {
-	// 	SAMPLE_PRT("SAMPLE_COMM_FRAME_SaveToFile. s32Ret: 0x%x !\n", s32Ret);
-	// }
-
-	return s32Ret;
-}
-
-void SAMPLE_VIO_HandleSig(CVI_S32 signo)
-{
-	signal(SIGINT, SIG_IGN);
-	signal(SIGTERM, SIG_IGN);
-
-	if (SIGINT == signo || SIGTERM == signo) {
-
-		SAMPLE_COMM_VPSS_UnBind_VO(VpssGrp, VpssChn, stVoConfig.VoDev, VoChn);
-
-		SAMPLE_COMM_VO_StopVO(&stVoConfig);
-
-		SAMPLE_COMM_VI_UnBind_VPSS(ViPipe, ViChn, VpssGrp);
-
-		SAMPLE_COMM_VPSS_Stop(VpssGrp, abChnEnable);
-
-		SAMPLE_COMM_VI_DestroyIsp(&stViConfig);
-
-		SAMPLE_COMM_VI_DestroyVi(&stViConfig);
-
-		SAMPLE_COMM_SYS_Exit();
-		//todo for release
-		SAMPLE_PRT("Program termination abnormally\n");
-	}
-	exit(-1);
-}
\ No newline at end of file
diff --git a/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.h b/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.h
deleted file mode 100644
index 1ec2085c9..000000000
--- a/middleware/v2/sample/tp2863_tp2803/sample_vio_tp2863_tp2803.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
- *
- * File Name: sample_vio.h
- * Description:
- */
-
-#ifndef __SAMPLE_VIO_H__
-#define __SAMPLE_VIO_H__
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif
-#endif /* End of #ifdef __cplusplus */
-
-#include <linux/cvi_common.h>
-#include <signal.h>
-
-CVI_S32 SAMPLE_VIO(void);
-void SAMPLE_VIO_HandleSig(CVI_S32 signo);
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif
-#endif /* End of #ifdef __cplusplus */
-
-#endif /* End of #ifndef __SAMPLE_VIO_H__*/
diff --git a/middleware/v2/sample/tp2863_tp2803/tp2863_tp2803_main.c b/middleware/v2/sample/tp2863_tp2803/tp2863_tp2803_main.c
deleted file mode 100644
index abb679592..000000000
--- a/middleware/v2/sample/tp2863_tp2803/tp2863_tp2803_main.c
+++ /dev/null
@@ -1,451 +0,0 @@
-#include <stdio.h>
-#include <stdbool.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-#include <pthread.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <sys/ioctl.h>
-#include <linux/i2c.h>
-#include <linux/i2c-dev.h>
-
-#include "sample_comm.h"
-#include "sample_vio_tp2863_tp2803.h"
-#include "cvi_sys.h"
-#include <linux/cvi_type.h>
-
-const CVI_U8 tp2803_master_i2c_addr = 0x45;        /* I2C slave address of tp2803 master chip*/
-const CVI_U32 tp2803_addr_byte = 1;
-const CVI_U32 tp2803_data_byte = 1;
-static int i2c_fd = -1;
-
-/*gpio*/
-enum CVI_GPIO_NUM_E {
-CVI_GPIOD_00 = 404,
-CVI_GPIOD_01,   CVI_GPIOD_02,   CVI_GPIOD_03,   CVI_GPIOD_04,   CVI_GPIOD_05,
-CVI_GPIOD_06,   CVI_GPIOD_07,   CVI_GPIOD_08,   CVI_GPIOD_09,   CVI_GPIOD_10,
-CVI_GPIOD_11,
-CVI_GPIOC_00 = 416,
-CVI_GPIOC_01,   CVI_GPIOC_02,   CVI_GPIOC_03,   CVI_GPIOC_04,   CVI_GPIOC_05,
-CVI_GPIOC_06,   CVI_GPIOC_07,   CVI_GPIOC_08,   CVI_GPIOC_09,   CVI_GPIOC_10,
-CVI_GPIOC_11,   CVI_GPIOC_12,   CVI_GPIOC_13,   CVI_GPIOC_14,   CVI_GPIOC_15,
-CVI_GPIOC_16,   CVI_GPIOC_17,   CVI_GPIOC_18,   CVI_GPIOC_19,   CVI_GPIOC_20,
-CVI_GPIOC_21,   CVI_GPIOC_22,   CVI_GPIOC_23,   CVI_GPIOC_24,   CVI_GPIOC_25,
-CVI_GPIOC_26,   CVI_GPIOC_27,   CVI_GPIOC_28,   CVI_GPIOC_29,   CVI_GPIOC_30,
-CVI_GPIOC_31,
-CVI_GPIOB_00 = 448,
-CVI_GPIOB_01,   CVI_GPIOB_02,   CVI_GPIOB_03,   CVI_GPIOB_04,   CVI_GPIOB_05,
-CVI_GPIOB_06,   CVI_GPIOB_07,   CVI_GPIOB_08,   CVI_GPIOB_09,   CVI_GPIOB_10,
-CVI_GPIOB_11,   CVI_GPIOB_12,   CVI_GPIOB_13,   CVI_GPIOB_14,   CVI_GPIOB_15,
-CVI_GPIOB_16,   CVI_GPIOB_17,   CVI_GPIOB_18,   CVI_GPIOB_19,   CVI_GPIOB_20,
-CVI_GPIOB_21,   CVI_GPIOB_22,   CVI_GPIOB_23,   CVI_GPIOB_24,   CVI_GPIOB_25,
-CVI_GPIOB_26,   CVI_GPIOB_27,   CVI_GPIOB_28,   CVI_GPIOB_29,   CVI_GPIOB_30,
-CVI_GPIOB_31,
-CVI_GPIOA_00 = 480,
-CVI_GPIOA_01,   CVI_GPIOA_02,   CVI_GPIOA_03,   CVI_GPIOA_04,   CVI_GPIOA_05,
-CVI_GPIOA_06,   CVI_GPIOA_07,   CVI_GPIOA_08,   CVI_GPIOA_09,   CVI_GPIOA_10,
-CVI_GPIOA_11,   CVI_GPIOA_12,   CVI_GPIOA_13,   CVI_GPIOA_14,   CVI_GPIOA_15,
-CVI_GPIOA_16,   CVI_GPIOA_17,   CVI_GPIOA_18,   CVI_GPIOA_19,   CVI_GPIOA_20,
-CVI_GPIOA_21,   CVI_GPIOA_22,   CVI_GPIOA_23,   CVI_GPIOA_24,   CVI_GPIOA_25,
-CVI_GPIOA_26,   CVI_GPIOA_27,   CVI_GPIOA_28,   CVI_GPIOA_29,   CVI_GPIOA_30,
-CVI_GPIOA_31,
-};
-
-#define CVI_GPIO_MIN CVI_GPIOD_00
-#define CVI_GPIO_MAX CVI_GPIOA_31
-
-#define SYSFS_GPIO_DIR "/sys/class/gpio"
-#define MAX_BUF 64
-
-static int tp2803_GPIO_Export(unsigned int gpio)
-{
-	int fd, len;
-	char buf[MAX_BUF];
-
-	fd = open(SYSFS_GPIO_DIR"/export", O_WRONLY);
-	if (fd < 0) {
-		perror("gpio/export");
-		return fd;
-	}
-
-	len = snprintf(buf, sizeof(buf), "%d", gpio);
-	write(fd, buf, len);
-	close(fd);
-
-	return 0;
-}
-
-static int tp2803_GPIO_SetDirection(unsigned int gpio, unsigned int out_flag)
-{
-	int fd;
-	char buf[MAX_BUF];
-
-	snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR"/gpio%d/direction", gpio);
-	if (access(buf, 0) == -1)
-		tp2803_GPIO_Export(gpio);
-
-	fd = open(buf, O_WRONLY);
-	if (fd < 0) {
-		perror("gpio/direction");
-		return fd;
-	}
-	//printf("mark %d , %s\n",out_flag, buf);
-	if (out_flag)
-		write(fd, "out", 4);
-	else
-		write(fd, "in", 3);
-
-	close(fd);
-	return 0;
-}
-
-static int tp2803_GPIO_SetValue(unsigned int gpio, unsigned int value)
-{
-	int fd;
-	char buf[MAX_BUF];
-
-	snprintf(buf, sizeof(buf), SYSFS_GPIO_DIR"/gpio%d/value", gpio);
-	if (access(buf, 0) == -1)
-		tp2803_GPIO_Export(gpio);
-
-	tp2803_GPIO_SetDirection(gpio, 1); //output
-
-	fd = open(buf, O_WRONLY);
-	if (fd < 0) {
-		perror("gpio/set-value");
-		return fd;
-	}
-
-	if (value)
-		write(fd, "1", 2);
-	else
-		write(fd, "0", 2);
-
-	close(fd);
-	return 0;
-}
-
-int tp2803_i2c_init(VI_PIPE ViPipe, CVI_U8 i2c_addr)
-{
-	UNUSED(ViPipe);
-	int ret;
-	char acDevFile[16] = {0};
-	CVI_U8 u8DevNum = 1;
-
-	snprintf(acDevFile, sizeof(acDevFile),  "/dev/i2c-%u", u8DevNum);
-	printf("open %s\n", acDevFile);
-
-	i2c_fd = open(acDevFile, O_RDWR, 0600);
-	if (i2c_fd < 0) {
-		printf("Open /dev/cvi_i2c_drv-%u error!\n", u8DevNum);
-		return CVI_FAILURE;
-	}
-
-	ret = ioctl(i2c_fd, I2C_SLAVE_FORCE, i2c_addr);
-	if (ret < 0) {
-		printf("I2C_SLAVE_FORCE error!\n");
-		close(i2c_fd);
-		i2c_fd = -1;
-		return ret;
-	}
-
-	return CVI_SUCCESS;
-}
-
-int tp2803_read_register(VI_PIPE ViPipe, int addr)
-{
-	UNUSED(ViPipe);
-	int ret, data;
-	CVI_U8 buf[8];
-	CVI_U8 idx = 0;
-
-	if (tp2803_addr_byte == 2)
-		buf[idx++] = (addr >> 8) & 0xff;
-
-	// add address byte 0
-	buf[idx++] = addr & 0xff;
-
-	ret = write(i2c_fd, buf, tp2803_addr_byte);
-	if (ret < 0) {
-		printf("I2C_READ error!\n");
-		return 0;
-	}
-
-	buf[0] = 0;
-	buf[1] = 0;
-	ret = read(i2c_fd, buf, tp2803_data_byte);
-	if (ret < 0) {
-		printf("I2C_READ error!\n");
-		return 0;
-	}
-
-	// pack read back data
-	data = 0;
-	if (tp2803_data_byte == 2) {
-		data = buf[0] << 8;
-		data += buf[1];
-	} else {
-		data = buf[0];
-	}
-
-	printf("i2c r 0x%x = 0x%x\n", addr, data);
-	return data;
-}
-
-int tp2803_write_register(VI_PIPE ViPipe, int addr, int data)
-{
-	UNUSED(ViPipe);
-	CVI_U8 idx = 0;
-	int ret;
-	CVI_U8 buf[8];
-
-	if (tp2803_addr_byte == 2)
-		buf[idx++] = (addr >> 8) & 0xff;
-
-	// add address byte 0
-	buf[idx++] = addr & 0xff;
-
-	if (tp2803_data_byte == 2)
-		buf[idx++] = (data >> 8) & 0xff;
-
-	// add data byte 0
-	buf[idx++] = data & 0xff;
-
-	ret = write(i2c_fd, buf, tp2803_addr_byte + tp2803_data_byte);
-	if (ret < 0) {
-		printf("I2C_WRITE error!\n");
-		return CVI_FAILURE;
-	}
-	printf("i2c w 0x%x 0x%x\n", addr, data);
-
-#if 0 // read back checing
-	ret = tp2803_read_register(ViPipe, addr);
-	if (ret != data)
-		printf("i2c readback-check fail, 0x%x != 0x%x\n", ret, data);
-#endif
-	return CVI_SUCCESS;
-}
-
-int tp2803_gpio_init(VI_PIPE ViPipe)
-{
-	(void) ViPipe;
-
-	//VO_RESET
-	if (tp2803_GPIO_SetValue(CVI_GPIOB_13, 0) != 0) {
-		printf("set power down gpio error!\n");
-		return CVI_FAILURE;
-	}
-
-	usleep(100 * 1000);
-
-	if (tp2803_GPIO_SetValue(CVI_GPIOB_13, 1) != 0) {
-		printf("set power down gpio error!\n");
-		return CVI_FAILURE;
-	}
-
-	usleep(100 * 1000);
-
-	return CVI_SUCCESS;
-}
-
-void tp2803_reg_init()
-{
-	//AHD 720P 25FPS
-	tp2803_write_register(0, 0xFF, 0x00); //Page 00
-	tp2803_write_register(0, 0x00, 0x00);
-	tp2803_write_register(0, 0x01, 0x00);
-	tp2803_write_register(0, 0x02, 0x9B);
-	tp2803_write_register(0, 0x03, 0x62);
-	tp2803_write_register(0, 0x04, 0x00);
-	tp2803_write_register(0, 0x05, 0x6C);
-	tp2803_write_register(0, 0x06, 0x00);
-	tp2803_write_register(0, 0x07, 0xC1);
-	tp2803_write_register(0, 0x08, 0x76);
-	tp2803_write_register(0, 0x09, 0x76);
-	tp2803_write_register(0, 0x0A, 0x76);
-	tp2803_write_register(0, 0x0B, 0x15);
-	tp2803_write_register(0, 0x0C, 0x04);
-	tp2803_write_register(0, 0x0D, 0xF0);
-	tp2803_write_register(0, 0x0E, 0x82);
-	tp2803_write_register(0, 0x0F, 0x80);
-	tp2803_write_register(0, 0x10, 0x17);
-	tp2803_write_register(0, 0x11, 0x80);
-	tp2803_write_register(0, 0x12, 0x01);
-	tp2803_write_register(0, 0x13, 0x3C);
-	tp2803_write_register(0, 0x14, 0x38);
-	tp2803_write_register(0, 0x15, 0x39);
-	tp2803_write_register(0, 0x16, 0xEB);
-	tp2803_write_register(0, 0x17, 0x10);
-	tp2803_write_register(0, 0x18, 0x10);
-	tp2803_write_register(0, 0x19, 0xF0);
-	tp2803_write_register(0, 0x1A, 0x10);
-	tp2803_write_register(0, 0x1B, 0xA4);
-	tp2803_write_register(0, 0x1C, 0x55);
-	tp2803_write_register(0, 0x1D, 0x76);
-	tp2803_write_register(0, 0x1E, 0x80);
-	tp2803_write_register(0, 0x1F, 0x00);
-	tp2803_write_register(0, 0x20, 0x28);
-	tp2803_write_register(0, 0x21, 0xC4);
-	tp2803_write_register(0, 0x22, 0x44);
-	tp2803_write_register(0, 0x23, 0x44);
-	tp2803_write_register(0, 0x24, 0x86);
-	tp2803_write_register(0, 0x25, 0x40);
-	tp2803_write_register(0, 0x26, 0x00);
-	tp2803_write_register(0, 0x27, 0x56);
-	tp2803_write_register(0, 0x28, 0x00);
-	tp2803_write_register(0, 0x29, 0x34);
-	tp2803_write_register(0, 0x2A, 0x19);
-	tp2803_write_register(0, 0x2B, 0x5e);
-	tp2803_write_register(0, 0x2C, 0x60);
-	tp2803_write_register(0, 0x2D, 0x00);
-	tp2803_write_register(0, 0x2E, 0x00);
-	tp2803_write_register(0, 0x2F, 0x00);
-	tp2803_write_register(0, 0x30, 0x01);
-	tp2803_write_register(0, 0x31, 0x00);
-	tp2803_write_register(0, 0x32, 0x00);
-	tp2803_write_register(0, 0x33, 0x00);
-	tp2803_write_register(0, 0x34, 0x00);
-	tp2803_write_register(0, 0x35, 0x00);
-	tp2803_write_register(0, 0x36, 0x00);
-	tp2803_write_register(0, 0x37, 0x00);
-	tp2803_write_register(0, 0x38, 0x00);
-	tp2803_write_register(0, 0x39, 0x00);
-	tp2803_write_register(0, 0x3A, 0x00);
-	tp2803_write_register(0, 0x3B, 0x90);
-	tp2803_write_register(0, 0x3C, 0x10);
-	tp2803_write_register(0, 0x3D, 0x80);
-	tp2803_write_register(0, 0x3E, 0x18);
-	tp2803_write_register(0, 0x3F, 0x00);
-	tp2803_write_register(0, 0x45, 0x41);
-	tp2803_write_register(0, 0xF0, 0x00);
-	tp2803_write_register(0, 0xF1, 0x08);
-	tp2803_write_register(0, 0xF2, 0x1e);
-	tp2803_write_register(0, 0xF3, 0x4a);
-	tp2803_write_register(0, 0xF4, 0x41);
-	tp2803_write_register(0, 0xF5, 0x00);
-
-	//AHD 720P 30FPS
-	// tp2803_write_register(0, 0xFF, 0x00);
-	// tp2803_write_register(0, 0x00, 0x00);
-	// tp2803_write_register(0, 0x01, 0x00);
-	// tp2803_write_register(0, 0x02, 0xCB);
-	// tp2803_write_register(0, 0x03, 0x62);
-	// tp2803_write_register(0, 0x04, 0x00);
-	// tp2803_write_register(0, 0x05, 0x6C);
-	// tp2803_write_register(0, 0x06, 0x00);
-	// tp2803_write_register(0, 0x07, 0xC1);
-	// tp2803_write_register(0, 0x08, 0x76);
-	// tp2803_write_register(0, 0x09, 0x76);
-	// tp2803_write_register(0, 0x0A, 0x76);
-	// tp2803_write_register(0, 0x0B, 0x00);
-	// tp2803_write_register(0, 0x0C, 0x04);
-	// tp2803_write_register(0, 0x0D, 0xF0);
-	// tp2803_write_register(0, 0x0E, 0x82);
-	// tp2803_write_register(0, 0x0F, 0x40);
-	// tp2803_write_register(0, 0x10, 0x06);
-	// tp2803_write_register(0, 0x11, 0x3E);
-	// tp2803_write_register(0, 0x12, 0x00);
-	// tp2803_write_register(0, 0x13, 0x3C);
-	// tp2803_write_register(0, 0x14, 0x38);
-	// tp2803_write_register(0, 0x15, 0x39);
-	// tp2803_write_register(0, 0x16, 0xEB);
-	// tp2803_write_register(0, 0x17, 0x10);
-	// tp2803_write_register(0, 0x18, 0x10);
-	// tp2803_write_register(0, 0x19, 0xF0);
-	// tp2803_write_register(0, 0x1A, 0x10);
-	// tp2803_write_register(0, 0x1B, 0xA4);
-	// tp2803_write_register(0, 0x1C, 0x55);
-	// tp2803_write_register(0, 0x1D, 0x76);
-	// tp2803_write_register(0, 0x1E, 0x80);
-	// tp2803_write_register(0, 0x1F, 0x00);
-	// tp2803_write_register(0, 0x20, 0x28);
-	// tp2803_write_register(0, 0x21, 0xAE);
-	// tp2803_write_register(0, 0x22, 0x14);
-	// tp2803_write_register(0, 0x23, 0x7A);
-	// tp2803_write_register(0, 0x24, 0x86);
-	// tp2803_write_register(0, 0x25, 0x40);
-	// tp2803_write_register(0, 0x26, 0x00);
-	// tp2803_write_register(0, 0x27, 0x56);
-	// tp2803_write_register(0, 0x28, 0x00);
-	// tp2803_write_register(0, 0x29, 0x34);
-	// tp2803_write_register(0, 0x2A, 0x19);
-	// tp2803_write_register(0, 0x2B, 0x5e);
-	// tp2803_write_register(0, 0x2C, 0x60);
-	// tp2803_write_register(0, 0x2D, 0x00);
-	// tp2803_write_register(0, 0x2E, 0x00);
-	// tp2803_write_register(0, 0x2F, 0x00);
-	// tp2803_write_register(0, 0x30, 0x01);
-	// tp2803_write_register(0, 0x31, 0x00);
-	// tp2803_write_register(0, 0x32, 0x00);
-	// tp2803_write_register(0, 0x33, 0x00);
-	// tp2803_write_register(0, 0x34, 0x00);
-	// tp2803_write_register(0, 0x35, 0x00);
-	// tp2803_write_register(0, 0x36, 0x00);
-	// tp2803_write_register(0, 0x37, 0x00);
-	// tp2803_write_register(0, 0x38, 0x00);
-	// tp2803_write_register(0, 0x39, 0x00);
-	// tp2803_write_register(0, 0x3A, 0x00);
-	// tp2803_write_register(0, 0x3B, 0xD0);
-	// tp2803_write_register(0, 0x3C, 0x10);
-	// tp2803_write_register(0, 0x3D, 0x80);
-	// tp2803_write_register(0, 0x3E, 0x18);
-	// tp2803_write_register(0, 0x3F, 0x00);
-	// tp2803_write_register(0, 0x45, 0x40);
-	// tp2803_write_register(0, 0xF0, 0x00);
-	// tp2803_write_register(0, 0xF1, 0x08);
-	// tp2803_write_register(0, 0xF2, 0x1e);
-	// tp2803_write_register(0, 0xF3, 0x4a);
-	// tp2803_write_register(0, 0xF4, 0x41);
-	// tp2803_write_register(0, 0xF5, 0x00);
-}
-
-int main(int argc, char *argv[])
-{
-	UNUSED(argc);
-	UNUSED(argv);
-
-	CVI_S32 s32Ret = CVI_FAILURE;
-
-	signal(SIGINT, SAMPLE_VIO_HandleSig);
-	signal(SIGTERM, SAMPLE_VIO_HandleSig);
-
-	s32Ret = SAMPLE_VIO();
-	if (s32Ret == CVI_SUCCESS){
-		SAMPLE_PRT("sample_vio exit success!\n");
-	}else{
-		SAMPLE_PRT("sample_vio exit abnormally!\n");
-		return s32Ret;
-	}
-
-	//output tp2803 mclk
-	SNS_MCLK_S mclk;
-	mclk.u8Cam = 0;
-	mclk.enFreq = MCLK_FREQ_27M;
-	CVI_MIPI_SetSnsMclk(&mclk);
-
-	//gpio reset
-	tp2803_gpio_init(0);
-
-	//i2c init
-	tp2803_i2c_init(0, tp2803_master_i2c_addr);
-
-	// check sensor chip id
-	if (tp2803_read_register(0, 0xfe) != 0x29 ||
-		tp2803_read_register(0, 0xff) != 0x12)
-	{
-		printf("read tp2803 chip id fail\n");
-		return CVI_FAILURE;
-	}
-
-	//tp2803 mode init
-	tp2803_reg_init();
-
-	while(1)
-	{
-		usleep(1000 * 1000);
-	}
-
-	return s32Ret;
-}
\ No newline at end of file
diff --git a/middleware/v2/sample/vio/sample_vio.c b/middleware/v2/sample/vio/sample_vio.c
index 57d5459f7..8ad986c3e 100644
--- a/middleware/v2/sample/vio/sample_vio.c
+++ b/middleware/v2/sample/vio/sample_vio.c
@@ -5218,3 +5218,150 @@ ERR_VPSS_COMBINE:
 	SAMPLE_COMM_SYS_Exit();
 	return s32Ret;
 }
+
+CVI_S32 SAMPLE_VO_LVDS_TEST(CVI_VOID)
+{
+	VB_CONFIG_S	   stVbConf;
+	CVI_U32		   u32BlkSize;
+	CVI_S32		   s32Ret = CVI_SUCCESS;
+	SAMPLE_VO_CONFIG_S stVoConfig;
+	VO_CHN_ATTR_S stChnAttr;
+	RECT_S stDefDispRect  = {0, 0, 1024, 600};
+	SIZE_S stDefImageSize = {1024, 600};
+	SIZE_S stSize = stDefImageSize;
+	VO_DEV VoDev = 0;
+	VO_LAYER VoLayer = VoDev;
+	VO_CHN VoChn = 0;
+
+	const VO_LVDS_ATTR_S lvds_ot07007_cfg = {
+		.mode = VO_LVDS_MODE_VESA,
+		.out_bits = VO_LVDS_OUT_6BIT,
+		.chn_num = 1,
+		.data_big_endian = 0,
+		.lane_id = {VO_LVDS_LANE_0, VO_LVDS_LANE_1, VO_LVDS_LANE_2, VO_LVDS_LANE_CLK, -1},
+		.lane_pn_swap = {false, false, false, false, false},
+		.stSyncInfo = {
+			.u16Hpw = 40,
+			.u16Hbb = 180,
+			.u16Hfb = 100,
+			.u16Hact = 1024,
+			.u16Vpw = 4,
+			.u16Vbb = 20,
+			.u16Vfb = 11,
+			.u16Vact = 600,
+			.bIvs = 0,
+			.bIhs = 0,
+			.bIop = 1,
+			.u16FrameRate = 60
+		},
+		.pixelclock = 51206,
+	};
+
+	system("devmem 0x03001100 32 0x3"); // set pinmux to GPIOB5
+	// set GPIOB5 to high
+	SAMPLE_COMM_GPIO_SetValue(453, 1);
+	// set GPIOE0 to low and GPIOE1 to high
+	system("devmem 0x05021000 32 0x2");
+
+	memset(&stVbConf, 0, sizeof(VB_CONFIG_S));
+	stVbConf.u32MaxPoolCnt = 1;
+
+	u32BlkSize = COMMON_GetPicBufferSize(stSize.u32Width, stSize.u32Height,
+						PIXEL_FORMAT_NV21,
+						DATA_BITWIDTH_8, COMPRESS_MODE_NONE, DEFAULT_ALIGN);
+	stVbConf.astCommPool[0].u32BlkSize	= u32BlkSize;
+	stVbConf.astCommPool[0].u32BlkCnt	= 3;
+	SAMPLE_PRT("common pool[%d] BlkSize %d\n", 0, u32BlkSize);
+
+	s32Ret = SAMPLE_COMM_SYS_Init(&stVbConf);
+	if (s32Ret != CVI_SUCCESS) {
+		SAMPLE_PRT("system init failed with %#x\n", s32Ret);
+		return s32Ret;
+	}
+
+	stVoConfig.VoDev	 = VoDev;
+	stVoConfig.stVoPubAttr.enIntfType  = VO_INTF_LCD_18BIT;
+	stVoConfig.stVoPubAttr.enIntfSync  = VO_OUTPUT_USER; //
+	stVoConfig.stVoPubAttr.stSyncInfo = lvds_ot07007_cfg.stSyncInfo;
+	stVoConfig.stVoPubAttr.u32BgColor = COLOR_10_RGB_BLUE;
+	stVoConfig.stDispRect	 = stDefDispRect;
+	stVoConfig.stImageSize	 = stDefImageSize;
+	stVoConfig.enPixFormat	 = PIXEL_FORMAT_NV21;
+	stVoConfig.u32DisBufLen  = 3;
+	stVoConfig.enVoMode	 = VO_MODE_1MUX;
+
+	/********************************
+	 * Set and start VO device VoDev#.
+	 ********************************/
+
+	stVoConfig.stVoPubAttr.stLvdsAttr = lvds_ot07007_cfg;
+
+	s32Ret = CVI_VO_SetPubAttr(VoDev, &stVoConfig.stVoPubAttr);
+	if (s32Ret != CVI_SUCCESS) {
+		SAMPLE_PRT("failed with %#x!\n", s32Ret);
+		goto ERR_VO_SETPUBATTR;
+	}
+
+	s32Ret = CVI_VO_Enable(VoDev);
+	if (s32Ret != CVI_SUCCESS) {
+		SAMPLE_PRT("failed with %#x!\n", s32Ret);
+		goto ERR_VO_ENABLE;
+	}
+
+	/******************************
+	 * Set and start layer VoDev#.
+	 ********************************/
+	VO_VIDEO_LAYER_ATTR_S stLayerAttr = { 0 };
+
+	stLayerAttr.stDispRect.s32X = 0;
+	stLayerAttr.stDispRect.s32Y = 0;
+	stLayerAttr.stDispRect = stDefDispRect;
+	stLayerAttr.enPixFormat = stVoConfig.enPixFormat;
+
+	stLayerAttr.stImageSize = stDefImageSize;
+
+	if (stVoConfig.u32DisBufLen) {
+		s32Ret = CVI_VO_SetDisplayBufLen(VoLayer, stVoConfig.u32DisBufLen);
+		if (s32Ret != CVI_SUCCESS) {
+			SAMPLE_PRT("CVI_VO_SetDisplayBufLen failed with %#x!\n", s32Ret);
+			goto ERR_VO_ENABLE;
+		}
+	}
+
+	s32Ret = CVI_VO_SetVideoLayerAttr(VoLayer, &stLayerAttr);
+	if (s32Ret != CVI_SUCCESS) {
+		SAMPLE_PRT("failed with %#x!\n", s32Ret);
+		goto ERR_VO_ENABLE;
+	}
+
+	s32Ret = CVI_VO_EnableVideoLayer(VoLayer);
+	if (s32Ret != CVI_SUCCESS) {
+		SAMPLE_PRT("failed with %#x!\n", s32Ret);
+		goto ERR_VO_ENABLE;
+	}
+
+	stChnAttr.stRect = stDefDispRect;
+	s32Ret = CVI_VO_SetChnAttr(VoLayer, VoChn, &stChnAttr);
+	if (s32Ret != CVI_SUCCESS) {
+		SAMPLE_PRT("failed with %#x!\n", s32Ret);
+		goto ERR_VO_ENABLE_VIDEOLAYER;
+	}
+
+	s32Ret = CVI_VO_EnableChn(VoLayer, VoChn);
+	if (s32Ret != CVI_SUCCESS) {
+		SAMPLE_PRT("failed with %#x!\n", s32Ret);
+		goto ERR_VO_ENABLE_VIDEOLAYER;
+	}
+
+	system("devmem 0x0a088094 32 0x0701000a"); //colorbar
+	PAUSE();
+
+	CVI_VO_DisableChn(VoLayer, VoChn);
+ERR_VO_ENABLE_VIDEOLAYER:
+	CVI_VO_DisableVideoLayer(VoLayer);
+ERR_VO_ENABLE:
+	CVI_VO_Disable(VoDev);
+ERR_VO_SETPUBATTR:
+	SAMPLE_COMM_SYS_Exit();
+	return s32Ret;
+}
diff --git a/middleware/v2/sample/vio/sample_vio.h b/middleware/v2/sample/vio/sample_vio.h
index 90c15262f..460be1700 100644
--- a/middleware/v2/sample/vio/sample_vio.h
+++ b/middleware/v2/sample/vio/sample_vio.h
@@ -35,6 +35,7 @@ CVI_S32 SAMPLE_PR2100_TEST(void);
 CVI_S32 SAMPLE_IMX335_PR2020_OFFLINE_ONLINE_TEST(void);
 CVI_S32 SAMPLE_IMX307_PR2020_OFFLINE_ONLINE_TEST(void);
 CVI_S32 SAMPLE_IMX307_ONTHEFLY_ONLINE_SC_TEST(void);
+CVI_S32 SAMPLE_VO_LVDS_TEST(void);
 
 #ifdef __cplusplus
 #if __cplusplus
diff --git a/middleware/v2/sample/vio/sample_vio_main.c b/middleware/v2/sample/vio/sample_vio_main.c
index 3569faf41..a240b10d0 100644
--- a/middleware/v2/sample/vio/sample_vio_main.c
+++ b/middleware/v2/sample/vio/sample_vio_main.c
@@ -54,6 +54,7 @@ void SAMPLE_VIO_Usage(char *sPrgNm)
 	printf("\t17)VI (IMX307 + PR2020) - online/offline VPSS - VO.\n");
 	printf("\t18)VI (IMX307) - onthefly online to VPSS - VO.\n");
 #endif
+	printf("\t50)VO (OT07007) - lvds colorbar test.\n");
 }
 
 int main(int argc, char *argv[])
@@ -161,6 +162,9 @@ int main(int argc, char *argv[])
 		s32Ret = SAMPLE_IMX307_ONTHEFLY_ONLINE_SC_TEST();
 		break;
 #endif
+	case 50:
+		s32Ret = SAMPLE_VO_LVDS_TEST();
+		break;
 	default:
 		SAMPLE_PRT("the index %d is invaild!\n", s32Index);
 		SAMPLE_VIO_Usage(argv[0]);