#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/cv1835-resets.h>
#include <dt-bindings/sound/cv1835-audio.h>

/dts-v1/;

/memreserve/	0x0000000100000000 0x0000000000020000; // ATF BL31

/ {
	compatible = "linux,dummy-virt";
	#size-cells = <0x2>;
	#address-cells = <0x2>;
	interrupt-parent = <&gic>;

	rst: reset-controller {
		#reset-cells = <1>;
		compatible = "cvitek,reset";
		reg = <0x0 0x03003000 0x0 0x10>;
	};

	gic: interrupt-controller {
		compatible = "arm,cortex-a15-gic";
		ranges;
		#size-cells = <0x2>;
		#address-cells = <0x2>;
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x0 0x01F01000 0x0 0x1000>,
		      <0x0 0x01F02000 0x0 0x2000>;
	};

	psci {
		migrate = <0xc4000005>;
		cpu_on = <0xc4000003>;
		cpu_off = <0x84000002>;
		cpu_suspend = <0xc4000001>;
		sys_poweroff = <0x84000008>;
		sys_reset = <0x84000009>;
		method = "smc";
		compatible = "arm,psci-0.2", "arm,psci";
	};

	cpus {
		#size-cells = <0x0>;
		#address-cells = <0x1>;

		A53_0: cpu@0 {
			reg = <0x0>;
			enable-method = "psci";
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			next-level-cache = <&CA53_L2>;
		};

		A53_1: cpu@1 {
			reg = <0x1>;
			enable-method = "psci";
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			next-level-cache = <&CA53_L2>;
		};

		CA53_L2: l2-cache0 {
			compatible = "cache";
		};
	};

	cvitek-ion {
		compatible = "cvitek,cvitek-ion";

		heap_carveout@0 {
			compatible = "cvitek,carveout";
			memory-region = <&ion_reserved>;
		};
	};

	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		cma_reserved: linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x1000000>; // 16MB
			alignment = <0x0 0x2000>; // 8KB
			linux,cma-default;
		};

		ion_reserved: ion {
			compatible = "ion-region";
			size = <0x0 0x07000000>; // 96MB + vip 16MB
		};

		vcodec_reserved: vcodec {
			/* <start, length> pair
			 * and restrict to 4G address range
			 */
			alloc-ranges = <0x1 0x00000000 0 0xF0000000>;
			size = <0x0 0x06000000>; // 96MB
			no-map;
		};

		jpu_reserved: jpu {
			/* <start, length> pair
			 * and restrict to 4G address range
			 */
			alloc-ranges = <0x1 0x00000000 0 0xFFFFFFFF>;
			size = <0x0 0x01000000>; // 16MB
			no-map;
		};
	};

	dmac: dma@0x4330000 {
		compatible = "snps,dmac-bm";
		reg = <0x0 0x04330000 0x0 0x1000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;

		dma-channels = /bits/ 8 <8>;
		#dma-cells = <3>;
		dma-requests = /bits/ 8 <16>;
		chan_allocation_order = /bits/ 8 <0>;
		chan_priority = /bits/ 8 <0>;
		block_size = <32>; /* max 32 data items */
		dma-masters = /bits/ 8 <2>;
		data-width = <4 4>; /* bytes */
		axi_tr_width = <4>; /* bytes */
		block-ts = <15>;
	};

	pwm0: pwm@3060000 {
		compatible = "cvitek,cvi-pwm";
		reg = <0x0 0x3060000 0x0 0x1000>;
		clocks = <&pclk>;
		#pwm-cells = <1>;
	};

	pwm1: pwm@3061000 {
		compatible = "cvitek,cvi-pwm";
		reg = <0x0 0x3061000 0x0 0x1000>;
		clocks = <&pclk>;
		#pwm-cells = <2>;
	};

	pwm2: pwm@3062000 {
		compatible = "cvitek,cvi-pwm";
		reg = <0x0 0x3062000 0x0 0x1000>;
		clocks = <&pclk>;
		#pwm-cells = <3>;
	};

	pwm3: pwm@3063000 {
		compatible = "cvitek,cvi-pwm";
		reg = <0x0 0x3063000 0x0 0x1000>;
		clocks = <&pclk>;
		#pwm-cells = <4>;
	};

	watchdog0: cv-wd@0x3010000 {
		compatible = "snps,dw-wdt";
		reg = <0x0 0x03010000 0x0 0x1000>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&rst RST_WDT>;
		clocks = <&pclk>;
	};

	timer {
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		always-on;
		clock-frequency = <25000000>;
		compatible = "arm,armv8-timer";
	};

	i2c_srcclk: clk25mhz {
		clock-output-names = "clk25mhz";
		clock-frequency = <25000000>;
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
	};

	audio_clock: audio_clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
#if 0
		clock-frequency = <12288000>;
#else
		clock-frequency = <24576000>;
#endif
		};

	i2c0: i2c@04000000 {
		compatible = "snps,designware-i2c";
		clocks = <&i2c_srcclk>;
		reg = <0x0 0x04000000 0x0 0x1000>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <100000>;

		#size-cells = <0x0>;
		#address-cells = <0x1>;
		resets = <&rst RST_I2C0>;
		reset-names = "i2c0";
		adau1372_1: adau1372@3c {
			compatible = "adi,adau1372";
			reg = <0x3c>;
			clocks = <&audio_clock>;
			clock-names = "mclk";
		};
	};

	i2c3: i2c@04030000 {
		compatible = "snps,designware-i2c";
		clocks = <&i2c_srcclk>;
		reg = <0x0 0x04030000 0x0 0x1000>;
		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <100000>;

		#size-cells = <0x0>;
		#address-cells = <0x1>;
		resets = <&rst RST_I2C3>;
		reset-names = "i2c3";
	};

	pclk: pclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <25000000>;
	};

	gpio0: gpio@03020000 {
		compatible = "snps,dw-apb-gpio";
		reg = <0x0 0x03020000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		porta: gpio-controller@0 {
			compatible = "snps,dw-apb-gpio-port";
			bank-name = "porta";
			gpio-controller;
			#gpio-cells = <2>;
			snps,nr-gpios = <32>;
			reg = <0>;
			interrupt-controller;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	gpio1: gpio@03021000 {
		compatible = "snps,dw-apb-gpio";
		reg = <0x0 0x03021000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		portb: gpio-controller@1 {
			compatible = "snps,dw-apb-gpio-port";
			bank-name = "portb";
			gpio-controller;
			#gpio-cells = <2>;
			snps,nr-gpios = <32>;
			reg = <0>;
			interrupt-controller;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	gpio2: gpio@03022000 {
		compatible = "snps,dw-apb-gpio";
		reg = <0x0 0x03022000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		portc: gpio-controller@2 {
			compatible = "snps,dw-apb-gpio-port";
			bank-name = "portc";
			gpio-controller;
			#gpio-cells = <2>;
			snps,nr-gpios = <32>;
			reg = <0>;
			interrupt-controller;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	gpio3: gpio@03023000 {
		compatible = "snps,dw-apb-gpio";
		reg = <0x0 0x03023000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		portd: gpio-controller@2 {
			compatible = "snps,dw-apb-gpio-port";
			bank-name = "portd";
			gpio-controller;
			#gpio-cells = <2>;
			snps,nr-gpios = <12>;
			reg = <0>;
			interrupt-controller;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	spi0:spi0@04180000 {
		compatible = "snps,dw-apb-ssi";
		reg = <0x0 0x04180000 0x0 0x10000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&pclk>;
		clock-frequency = <25000000>;
		#address-cells = <1>;
		#size-cells = <0>;
		num-cs = <1>;
		//switch-gpios = <&port0a 7 0>;
		spidev: spidev@0 {
			compatible = "rohm,dh2228fv";
			//memory-region = <&spi_lcd_reserved>;
			spi-max-frequency = <25000000>;
			reg = <0>;
		};
	};

	eth_csrclk: eth_csrclk {
		clock-output-names = "eth_csrclk";
		clock-frequency = <25000000>;
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
	};

	eth_ptpclk: eth_ptpclk {
		clock-output-names = "eth_ptpclk";
		clock-frequency = <50000000>;
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
	};


	uart0: serial@04140000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x0 0x04140000 0x0 0x1000>;
		clock-frequency = <25000000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
	};
#if 0
	uart1: serial@04150000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x0 0x04150000 0x0 0x1000>;
		clock-frequency = <25000000>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
	};

	uart2: serial@04160000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x0 0x04160000 0x0 0x1000>;
		clock-frequency = <25000000>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
	};

	uart3: serial@04170000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x0 0x04170000 0x0 0x1000>;
		clock-frequency = <25000000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
	};
#endif

	stmmac_axi_setup: stmmac-axi-config {
		snps,wr_osr_lmt = <1>;
		snps,rd_osr_lmt = <2>;
		snps,blen = <4 8 16 0 0 0 0>;
	};

	mtl_rx_setup: rx-queues-config {
		snps,rx-queues-to-use = <4>;
		queue0 {};
		queue1 {};
		queue2 {};
		queue3 {};
	};

	mtl_tx_setup: tx-queues-config {
		snps,tx-queues-to-use = <4>;
		queue0 {};
		queue1 {};
		queue2 {};
		queue3 {};
	};

#if 1
	ethernet0: ethernet@4510000 {
		compatible = "cvitek,ethernet";
		reg = <0x0 0x04510000 0x0 0x10000>;
		interrupt-names = "macirq";
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "stmmaceth", "ptp_ref";
		clocks = <&eth_csrclk>, <&eth_ptpclk>;
		phy-reset-gpios = <&porta 26 0>;

		/* no hash filter and perfect filter support */
		snps,multicast-filter-bins = <0>;
		snps,perfect-filter-entries = <1>;

		snps,txpbl = <16>;
		snps,rxpbl = <16>;
		snps,aal;

		snps,axi-config = <&stmmac_axi_setup>;
		snps,mtl-rx-config = <&mtl_rx_setup>;
		snps,mtl-tx-config = <&mtl_tx_setup>;
	};
#endif
#if 1
	ethernet1: ethernet@04520000 {
		compatible = "cvitek,ethernet";
		reg = <0x0 0x04520000 0x0 0x10000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq";
		clock-names = "stmmaceth", "ptp_ref";
		clocks = <&eth_csrclk>, <&eth_ptpclk>;
		phy-reset-gpios = <&porta 26 0>;

		/* no hash filter and perfect filter support */
		snps,multicast-filter-bins = <0>;
		snps,perfect-filter-entries = <1>;

		snps,txpbl = <16>;
		snps,rxpbl = <16>;
		snps,aal;

		snps,axi-config = <&stmmac_axi_setup>;
		snps,mtl-rx-config = <&mtl_rx_setup>;
		snps,mtl-tx-config = <&mtl_tx_setup>;

	};
#endif

	emmc:cv-emmc@4300000 {
		compatible = "cvitek,cv1835-fpga-emmc";
		reg = <0x0 0x4300000 0x0 0x1000>;
		reg-names = "core_mem";
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		bus-width = <4>;
		non-removable;
		max-frequency = <12000000>;
		no-sdio;
		no-sd;
	};

	sd:cv-sd@4310000 {
		compatible = "cvitek,cv1835-fpga-sd";
		reg = <0x0 0x4310000 0x0 0x1000>;
		reg-names = "core_mem";
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		bus-width = <4>;
		max-frequency = <12000000>;
		no-sdio;
		no-mmc;
	};

	i2s_subsys {
		compatible = "cvitek,i2s_tdm_subsys";
		reg = <0x0 0x04108000 0x0 0x100>;
		master_base = <0x04120000>; /* I2S2 is master, only useful while using multi I2S IPs work on same IO */
	};

	mipi_rx: cif {
		compatible = "cvitek,cif";
		reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0300b000 0x0 0x1000>;
		reg-names = "csi_mac0", "csi_wrap0";
		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "csi0";
		snsr-reset = <&portd 7 GPIO_ACTIVE_LOW>;
		resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
			<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
		reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
	};

	mipi_tx {
		compatible = "cvitek,mipi_tx";
		reg = <0x0 0x0a080000 0x0 0x10000>,<0x0 0x0300c000 0x0 0x100>;
		reg-names = "sc","dphy";
	};

	vip {
		compatible = "cvitek,vip";
		reg = <0x0 0x0a080000 0x0 0x10000>,<0x0 0x0a0a0000 0x0 0x2000>,
		      <0x0 0x0a0c8000 0x0 0x20>,<0x0 0x0a000000 0x0 0x80000>,
		      <0x0 0x0300c000 0x0 0x100>;
		reg-names = "sc","dwa","vip_sys","isp","dphy";
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sc","dwa","isp";
		cvitek,cif-modules = <&mipi_rx>;
		snsr-num = <1>;
	};

	vcodec {
		compatible = "cvitek,vcodec";
		memory-region = <&vcodec_reserved>;
		reg = <0x0 0xb020000 0x0 0x10000>;
		reg-names = "vcodec";
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vcodec";
	};

	jpu {
		compatible = "cvitek,jpeg";
		memory-region = <&jpu_reserved>;
		reg = <0x0 0x0B000000 0x0 0x300>;
		reg-names = "jpu";
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "jpu";
		resets = <&rst RST_JPEG>;
		reset-names = "jpeg";
	};

	i2s_mclk: i2s_mclk {
		clock-output-names = "i2s_mclk";
		clock-frequency = <24576000>; /* use internal audio PLL */
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
	};

#ifdef CV1835_AUDIO_CODEC_EN
	adc: adc@0300A000 {
		compatible = "cvitek,cv1835adc";
		reg = <0x0 0x0300A000 0x0 0x100>;
		clocks = <&i2s_mclk 0>;
		clock-names = "i2sclk";
	};

	dac: dac@0300A400 {
		compatible = "cvitek,cv1835dac";
		reg = <0x0 0x0300A400 0x0 0x100>;
		clocks = <&i2s_mclk 0>;
		clock-names = "i2sclk";
	};

	sound_adc {
		compatible = "cvitek,cv1835-adc";
		cvi,model = "CV1835";
		cvi,card_name = "cvi_adc";
	};

	sound_dac {
		compatible = "cvitek,cv1835-dac";
		cvi,model = "CV1835";
		cvi,card_name = "cvi_dac";
	};
#endif


	i2s0: i2s@04100000 {
		compatible = "cvitek,cv1835-i2s";
		reg = <0x0 0x04100000 0x0 0x2000>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2s_mclk 0>;
		clock-names = "i2sclk";
		dev-id = <0>;
		#sound-dai-cells = <0>;
		dmas = <&dmac 0 1 1 /* read channel */
			&dmac 1 1 1>; /* write channel */
		dma-names = "rx", "tx";
		capability = "rx"; /* I2S0 connect to internal ADC as RX */
	};

	i2s1: i2s@04110000 {
		compatible = "cvitek,cv1835-i2s";
		reg = <0x0 0x04110000 0x0 0x2000>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2s_mclk 0>;
		clock-names = "i2sclk";
		dev-id = <1>;
		#sound-dai-cells = <0>;
		dmas = <&dmac 2 1 1 /* read channel */
			&dmac 3 1 1>; /* write channel */
		dma-names = "rx", "tx";
#ifndef CV1835_CONCURRENT_I2S /* refer to /include/dt-bindings/sound/cv1835-audio.h */
		capability = "txrx";
#else
		capability = "tx";
#endif
	};

#ifdef CV1835_EXT_CARD_1_EN
	/* sound_ext1 use external codec */
	sound_ext1 {
		compatible = "cvitek,cv1835-adau1372";
		cvi,model = "CV1835";
		cvi,mode = "I2S";
		cvi,fmt = "IBNF";
		cvi,card_name = "cvi_sound_card_0";
		cvi,slot_no=<2>;
		dai@0 {
			cvi,dai_name = "cv1835-i2s-1";
			cvi,stream_name = "adau1372-aif";
			cvi,cpu_dai_name = "4110000.i2s";
			cvi,codec_dai_name = "adau1372-aif";
			cvi,platform_name = "4110000.i2s";
			cvi,codec_name = "adau1372.0-003c";
			cvi,role = "master";
		};
#ifdef CV1835_CONCURRENT_I2S
		dai@1 {
			cvi,dai_name = "cv1835-i2s-0";
			cvi,stream_name = "adau1372-aif";
			cvi,cpu_dai_name = "4100000.i2s";
			cvi,codec_dai_name = "adau1372-aif";
			cvi,platform_name = "4100000.i2s";
			cvi,codec_name = "adau1372.0-003c";
			cvi,role = "slave";
		};
#endif
	};
#endif

	pdm: pdm@0x041D0C00 {
		compatible = "cvitek,cv1835pdm";
		reg = <0x0 0x041D0C00 0x0 0x100>;
		clocks = <&i2s_mclk 0>;
		clock-names = "i2sclk";
	};

#ifdef CV1835_PDM_EN
	/* sound_PDM use PDM to transfer DMIC signal to I2S signal as audio input */
	sound_PDM {
		compatible = "cvitek,cv1835-pdm";
		cvi,model = "CV1835";
		cvi,card_name = "cv1835_internal_PDM";
	};
#endif

	i2s2: i2s@04120000 {
		compatible = "cvitek,cv1835-i2s";
		reg = <0x0 0x04120000 0x0 0x2000>;
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2s_mclk 0>;
		clock-names = "i2sclk";
		dev-id = <2>;
		#sound-dai-cells = <0>;
		dmas = <&dmac 4 1 1 /* read channel */
			&dmac 5 1 1>; /* write channel */
		dma-names = "rx", "tx";
#ifndef CV1835_CONCURRENT_I2S
		capability = "txrx";
#else
		capability = "rx";
#endif
	};

	i2s3: i2s@04130000 {
		compatible = "cvitek,cv1835-i2s";
		reg = <0x0 0x04130000 0x0 0x2000>;
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&i2s_mclk 0>;
		clock-names = "i2sclk";
		dev-id = <3>;
		#sound-dai-cells = <0>;
		dmas = <&dmac 6 1 1 /* read channel */
			&dmac 7 1 1>; /* write channel */
		dma-names = "rx", "tx";
		capability = "tx"; /* I2S3 connect to internal DAC as TX */
	};
#ifdef CV1835_EXT_CARD_2_EN
	/* sound_ext2 use external codec */
	sound_ext2 {
		compatible = "cvitek,cv1835-adau1372";
		cvi,model = "CV1835";
		cvi,mode = "I2S";
		cvi,fmt = "IBNF";
		cvi,card_name = "cv1835_external_card";
		cvi,slot_no=<2>;

		dai@0 {
			cvi,dai_name = "cv1835-i2s-2";
			cvi,stream_name = "adau1372-aif";
			cvi,cpu_dai_name = "4120000.i2s";
			cvi,codec_dai_name = "adau1372-aif";
			cvi,platform_name = "4120000.i2s";
			cvi,codec_name = "adau1372.0-003c";
			cvi,role = "master";
		};
#ifdef CV1835_CONCURRENT_I2S
		dai@1 {
			cvi,dai_name = "cv1835-i2s-3";
			cvi,stream_name = "adau1372-aif";
			cvi,cpu_dai_name = "4130000.i2s";
			cvi,codec_dai_name = "adau1372-aif";
			cvi,platform_name = "4130000.i2s";
			cvi,codec_name = "adau1372.0-003c";
			cvi,role = "slave";
		};
#endif
	};
#endif
	otg0:cvi-usb-otg@040C0000 {
		compatible = "cvitek,usb-otg";
		reg = <0x0 0x040C0000 0x0 0x10000>,
			<0x0 0x03000064 0x0 0x04>,//ddr_addr_mode
			<0x0 0x03000038 0x0 0x08>,//USB Control and Status Register 0
			<0x0 0x03000048 0x0 0x08>;//USB PHY Control and Status Register
		interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
		clock-frequency = <25000000>;
		//dr_mode		= "peripheral";
		dr_mode		= "otg";
		dis_ss = "true";
		resets = <&rst RST_USB>;
		reset-names = "usb";
		//vbus-gpio = <&port0a 4 0>;
		otg_bypass = "true";
		status = "disabled"; // fpga not support
	};

	host0:cvi-usb-host@040D0000 {
		compatible = "cvitek,xhci-platform";
		reg = <0x0 0x040D0000 0x0 0x10000>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
		otg-controller = <&otg0>;
		clock-frequency = <25000000>;
		status = "disabled"; // fpga not support
	};

	usb0:cvi-usb-dev@040E0000 {
		compatible = "cvitek,usb-dev";
		reg = <0x0 0x040E0000 0x0 0x1000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <25000000>;
		otg-controller = <&otg0>;
		dma_mode = "new";
		status = "disabled"; // fpga not support
	};

	memory {
		reg = <0x1 0x00000000 0x0 0x40000000>;
		device_type = "memory";
	};


	aliases {
		serial0 = &uart0;
		ethernet0 = &ethernet0;
		ethernet1 = &ethernet1;
	};

	chosen {
		stdout-path = "serial0"; // "serial0:115200n8", no arguments means no re-initialization
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A53_0>,
				     <&A53_1>;
	};

};