/* * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include #include #include /* ----------------------------------------------------------------------------- * Very simple stackless exception handlers used by BL2. * ----------------------------------------------------------------------------- */ .globl bl2_exceptions vector_base bl2_exceptions /* ----------------------------------------------------- * Current EL with SP0 : 0x0 - 0x200 * ----------------------------------------------------- */ vector_entry SynchronousExceptionSP0 mov x0, #SYNC_EXCEPTION_SP_EL0 bl cpu_report_exception no_ret panic_handler check_vector_size SynchronousExceptionSP0 vector_entry IrqSP0 mov x0, #IRQ_SP_EL0 bl cpu_report_exception no_ret panic_handler check_vector_size IrqSP0 vector_entry FiqSP0 mov x0, #FIQ_SP_EL0 bl cpu_report_exception no_ret panic_handler check_vector_size FiqSP0 vector_entry SErrorSP0 mov x0, #SERROR_SP_EL0 bl cpu_report_exception no_ret panic_handler check_vector_size SErrorSP0 /* ----------------------------------------------------- * Current EL with SPx: 0x200 - 0x400 * ----------------------------------------------------- */ vector_entry SynchronousExceptionSPx mov x0, #SYNC_EXCEPTION_SP_ELX bl cpu_report_exception no_ret panic_handler check_vector_size SynchronousExceptionSPx vector_entry IrqSPx mov x0, #IRQ_SP_ELX bl cpu_report_exception no_ret panic_handler check_vector_size IrqSPx vector_entry FiqSPx mov x0, #FIQ_SP_ELX bl cpu_report_exception no_ret panic_handler check_vector_size FiqSPx vector_entry SErrorSPx mov x0, #SERROR_SP_ELX bl cpu_report_exception no_ret panic_handler check_vector_size SErrorSPx /* ----------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 * ----------------------------------------------------- */ vector_entry SynchronousExceptionA64 /* Enable the SError interrupt */ msr daifclr, #DAIF_ABT_BIT /* Expect only SMC exceptions */ mrs x30, esr_el3 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH cmp x30, #EC_AARCH64_SMC b.ne unexpected_sync_exception b smc_handler64 check_vector_size SynchronousExceptionA64 vector_entry IrqA64 mov x0, #IRQ_AARCH64 bl cpu_report_exception no_ret panic_handler check_vector_size IrqA64 vector_entry FiqA64 mov x0, #FIQ_AARCH64 bl cpu_report_exception no_ret panic_handler check_vector_size FiqA64 vector_entry SErrorA64 mov x0, #SERROR_AARCH64 bl cpu_report_exception no_ret panic_handler check_vector_size SErrorA64 /* ----------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 * ----------------------------------------------------- */ vector_entry SynchronousExceptionA32 mov x0, #SYNC_EXCEPTION_AARCH32 bl cpu_report_exception no_ret panic_handler check_vector_size SynchronousExceptionA32 vector_entry IrqA32 mov x0, #IRQ_AARCH32 bl cpu_report_exception no_ret panic_handler check_vector_size IrqA32 vector_entry FiqA32 mov x0, #FIQ_AARCH32 bl cpu_report_exception no_ret panic_handler check_vector_size FiqA32 vector_entry SErrorA32 mov x0, #SERROR_AARCH32 bl cpu_report_exception no_ret panic_handler check_vector_size SErrorA32 unexpected_sync_exception: mov x0, #SYNC_EXCEPTION_AARCH64 bl cpu_report_exception no_ret panic_handler func smc_handler64 # Reset exception stack ldr x30, =__STACKS_END__ msr spsel, #0 mov sp, x30 bl bl2_smc_handler b . endfunc smc_handler64