5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
84 lines
1.3 KiB
Plaintext
84 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2014 Linaro Ltd.
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* Copyright (c) 2013-2014 Hisilicon Limited.
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*/
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/dts-v1/;
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#include "hisi-x5hd2.dtsi"
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/ {
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model = "Hisilicon HIX5HD2 Development Board";
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compatible = "hisilicon,hix5hd2";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "hisilicon,hix5hd2-smp";
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&l2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&l2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x80000000>;
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};
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};
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&timer0 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&gmac0 {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-handle = <&phy2>;
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phy-mode = "mii";
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/* Placeholder, overwritten by bootloader */
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mac-address = [00 00 00 00 00 00];
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status = "okay";
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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};
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&gmac1 {
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#address-cells = <1>;
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#size-cells = <0>;
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phy-handle = <&phy1>;
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phy-mode = "rgmii";
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/* Placeholder, overwritten by bootloader */
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mac-address = [00 00 00 00 00 00];
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&ahci {
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phys = <&sata_phy>;
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phy-names = "sata-phy";
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};
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