5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
40 lines
1.2 KiB
ArmAsm
40 lines
1.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
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* differently than every other instruction, so it is set to 0 (write)
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* even though the instructions are read instructions. This means that
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* during an abort the instructions will be treated as a write and the
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* handler will raise a signal from unwriteable locations if they
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* fault. We have to specifically check for these instructions
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* from the abort handlers to treat them properly.
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*
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*/
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.macro do_thumb_abort, fsr, pc, psr, tmp
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tst \psr, #PSR_T_BIT
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beq not_thumb
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ldrh \tmp, [\pc] @ Read aborted Thumb instruction
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uaccess_disable ip @ disable userspace access
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and \tmp, \tmp, # 0xfe00 @ Mask opcode field
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cmp \tmp, # 0x5600 @ Is it ldrsb?
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orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
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tst \tmp, #1 << 11 @ L = 0 -> write
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orreq \fsr, \fsr, #1 << 11 @ yes.
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b do_DataAbort
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not_thumb:
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.endm
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/*
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* We check for the following instruction encoding for LDRD.
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*
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* [27:25] == 000
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* [7:4] == 1101
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* [20] == 0
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*/
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.macro teq_ldrd, tmp, insn
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mov \tmp, #0x0e100000
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orr \tmp, #0x000000f0
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and \tmp, \insn, \tmp
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teq \tmp, #0x000000d0
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.endm
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