271 lines
6.4 KiB
Plaintext
271 lines
6.4 KiB
Plaintext
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/cv1835-resets.h>
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#include <dt-bindings/sound/cv1835-audio.h>
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/dts-v1/;
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/memreserve/ 0x80000000 0x0000000000080000; // ATF BL31 + BL32
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/ {
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compatible = "linux,dummy-virt";
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#size-cells = <0x2>;
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#address-cells = <0x2>;
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interrupt-parent = <&gic>;
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rst: reset-controller {
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#reset-cells = <1>;
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compatible = "cvitek,reset";
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reg = <0x0 0x03003000 0x0 0x10>;
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};
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gic: interrupt-controller {
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compatible = "arm,cortex-a15-gic";
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ranges;
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#size-cells = <0x2>;
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#address-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x0 0x01F01000 0x0 0x1000>,
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<0x0 0x01F02000 0x0 0x2000>;
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};
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psci {
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migrate = <0xc4000005>;
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cpu_on = <0xc4000003>;
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cpu_off = <0x84000002>;
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cpu_suspend = <0xc4000001>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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method = "smc";
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compatible = "arm,psci-0.2", "arm,psci";
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};
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cpus {
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#size-cells = <0x0>;
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#address-cells = <0x1>;
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A53_0: cpu@0 {
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reg = <0x0>;
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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};
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};
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tpu {
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compatible = "cvitek,tpu";
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reg-names = "tdma", "tiu";
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reg = <0x0 0x0C100000 0x0 0x1000>,
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<0x0 0x0C101000 0x0 0x1000>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
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};
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mon {
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compatible = "cvitek,mon";
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reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
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reg = <0x0 0x01040000 0x0 0x1000>,
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<0x0 0x08004000 0x0 0x1000>,
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<0x0 0x08006000 0x0 0x1000>,
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<0x0 0x08008000 0x0 0x1000>,
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<0x0 0x0800A000 0x0 0x1000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
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};
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cvitek-ion {
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compatible = "cvitek,cvitek-ion";
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heap_carveout@0 {
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compatible = "cvitek,carveout";
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memory-region = <&ion_reserved>;
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};
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};
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reserved-memory {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges;
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cma_reserved: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x1000000>; // 16MB
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alignment = <0x0 0x2000>; // 8KB
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linux,cma-default;
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};
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ion_reserved: ion {
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compatible = "ion-region";
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size = <0x0 0x06000000>; // 96MB
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};
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vip_reserved: vip {
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/* <start, length> pair
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* and restrict to 4G address range
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*/
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size = <0x0 0x02000000>; // 32MB
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no-map;
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};
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vcodec_reserved: vcodec {
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/* <start, length> pair
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* and restrict to 4G address range
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*/
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alloc-ranges = <0x0 0x80000000 0 0xC0000000>;
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size = <0x0 0x06000000>; // 96MB
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alignment = <0x0 0x1000>; // 4KB
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no-map;
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};
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jpu_reserved: jpu {
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/* <start, length> pair
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* and restrict to 4G address range
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*/
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alloc-ranges = <0x0 0x80000000 0 0xC0000000>;
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size = <0x0 0x01000000>; // 16MB
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alignment = <0x0 0x1000>; // 4KB
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no-map;
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};
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};
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timer {
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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always-on;
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clock-frequency = <1000000000>;
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compatible = "arm,armv8-timer";
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};
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watchdog0: cv-wd@0x3010000 {
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compatible = "snps,dw-wdt";
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reg = <0x0 0x03010000 0x0 0x1000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_WDT>;
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clocks = <&pclk>;
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};
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pclk: pclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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uart0: serial@04140000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x04140000 0x0 0x1000>;
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clock-frequency = <307200>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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memory {
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reg = <0x0 0x80000000 0x0 0x80000000>;
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device_type = "memory";
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};
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gpio0: gpio@03020000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x03020000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "porta";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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mipi_rx: cif {
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compatible = "cvitek,cif";
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reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
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<0x0 0x0a0c4000 0x0 0x2000>;
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reg-names = "csi_mac0", "csi_wrap0", "csi_mac1";
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "csi0", "csi1";
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snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>;
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resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
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<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
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reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
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};
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mipi_tx {
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compatible = "cvitek,mipi_tx";
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};
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base {
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compatible = "cvitek,base";
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};
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vip {
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compatible = "cvitek,vip";
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memory-region = <&vip_reserved>;
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reg = <0x0 0x0a080000 0x0 0x10000>,<0x0 0x0a0c0000 0x0 0x1000>,
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<0x0 0x0a0c8000 0x0 0x20>,<0x0 0x0a000000 0x0 0x80000>,
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<0x0 0x0a0d1000 0x0 0x100>;
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reg-names = "sc","dwa","vip_sys","isp","dphy";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sc","dwa","isp";
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cvitek,cif-modules = <&mipi_rx>;
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snsr-num = <1>;
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clock-freq-vip-sys1 = <300000000>;
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};
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vcodec {
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compatible = "cvitek,cv1822-fpga-vcodec";
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memory-region = <&vcodec_reserved>;
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reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>;
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reg-names = "h265", "h264","vc_ctrl";
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "h265","h264";
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};
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jpu {
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compatible = "cvitek,cv1822-fpga-jpeg";
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memory-region = <&jpu_reserved>;
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reg = <0x0 0x0B000000 0x0 0x300>;
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reg-names = "jpeg";
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "jpeg";
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reset = <&rst RST_JPEG>;
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reset-names = "jpeg";
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};
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0"; // "serial0:115200n8", no arguments means no re-initialization
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&A53_0>;
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};
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rtos_cmdqu {
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compatible = "cvitek,rtos_cmdqu";
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reg = <0x0 0x01900000 0x0 0x1000>;
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reg-names = "mailbox";
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mailbox";
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};
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};
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