1222 lines
57 KiB
C
1222 lines
57 KiB
C
// $Module: reg_vip_sys $
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// $RegisterBank Version: V 1.0.00 $
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// $Author: $
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// $Date: Tue, 28 Dec 2021 04:11:12 PM $
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//
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//GEN REG ADDR/OFFSET/MASK
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#define VIP_SYS_VIP_RESETS 0x0
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#define VIP_SYS_VIP_RESERVE 0x4
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#define VIP_SYS_VIP_INT 0x8
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#define VIP_SYS_VIP_AXI_SW 0x10
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#define VIP_SYS_VIP_CLK_LP 0x14
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#define VIP_SYS_VIP_CLK_CTRL0 0x18
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#define VIP_SYS_VIP_CLK_CTRL1 0x1c
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#define VIP_SYS_VIP_LP_CTRL_AXI_RT 0x20
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#define VIP_SYS_VIP_LP_CTRL_AXI_OFF 0x24
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#define VIP_SYS_VIP_LP_CTRL_X2P 0x28
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#define VIP_SYS_SC_LP_CTRL_AXI_FAB 0x2c
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#define VIP_SYS_VIP_CLK_RATIO0 0x30
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#define VIP_SYS_VIP_CLK_RATIO1 0x34
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#define VIP_SYS_VIP_CLK_RATIO_CSI_MAC0 0x38
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#define VIP_SYS_VIP_CLK_RATIO_ISP_TOP 0x3c
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#define VIP_SYS_VIP_CLK_RATIO_CSI_MAC1 0x40
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#define VIP_SYS_VIP_CLK_RATIO_CSI_BE 0x44
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#define VIP_SYS_VIP_CLK_RATIO_CSI_MAC2 0x48
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#define VIP_SYS_VIP_LP_CTRL_STATUS 0x50
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#define VIP_SYS_VIP_URGENT_SEL 0x5c
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#define VIP_SYS_VIP_QOS_OW 0x60
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#define VIP_SYS_VIP_QOS_VALUE 0x64
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#define VIP_SYS_VIP_QOS_OFFSET 0x68
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#define VIP_SYS_VIP_QOS_URGENT_HI_TH 0x6c
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#define VIP_SYS_VIP_AXI_RT_FAB_PRI_OW 0x70
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#define VIP_SYS_VIP_AXI_RT_FAB_PRI_VALUE 0x74
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#define VIP_SYS_VIP_QOS_URGENT_LOW_TH 0x7c
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#define VIP_SYS_VIP_DUMMY0 0x80
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#define VIP_SYS_VIP_DUMMY1 0x84
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#define VIP_SYS_VIP_DUMMY2 0x88
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#define VIP_SYS_VIP_DUMMY3 0x8c
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#define VIP_SYS_VIP_DBG0 0x90
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#define VIP_SYS_VIP_DBG1 0x94
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#define VIP_SYS_VIP_DBG2 0x98
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#define VIP_SYS_VIP_DBG3 0x9c
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#define VIP_SYS_VIP_RT_AXI_MON_M1 0xa0
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#define VIP_SYS_VIP_RT_AXI_MON_M2 0xa4
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#define VIP_SYS_VIP_RT_AXI_MON_M3 0xa8
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#define VIP_SYS_VIP_RT_AXI_MON_M4 0xac
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#define VIP_SYS_VIP_OFF_AXI_MON_M1 0xb0
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#define VIP_SYS_VIP_OFF_AXI_MON_M2 0xb4
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#define VIP_SYS_VIP_RESETS1 0xc0
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#define VIP_SYS_VIP_CLK_RATIO_RAW_TOP 0xc4
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#define VIP_SYS_VIP_CLK_RATIO_IVE_TOP 0xc8
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#define VIP_SYS_VIP_CLK_RATIO_CAM0 0xcc
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#define VIP_SYS_VIP_OFF_AXI_MON_M3 0xd0
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#define VIP_SYS_VIP_OFF_AXI_MON_M4 0xd4
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#define VIP_SYS_VIP_OFF_AXI_MON_M5 0xd8
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#define VIP_SYS_VIP_OFF_AXI_MON_M6 0xdc
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#define VIP_SYS_VIP_OFF_AXI_MON_M7 0xe0
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#define VIP_SYS_REG_QQQ 0x0
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#define VIP_SYS_REG_QQQ_OFFSET 0
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#define VIP_SYS_REG_QQQ_MASK 0x1
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#define VIP_SYS_REG_QQQ_BITS 0x1
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#define VIP_SYS_REG_RST_ISP_TOP 0x0
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#define VIP_SYS_REG_RST_ISP_TOP_OFFSET 1
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#define VIP_SYS_REG_RST_ISP_TOP_MASK 0x2
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#define VIP_SYS_REG_RST_ISP_TOP_BITS 0x1
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#define VIP_SYS_REG_RST_IMG_D 0x0
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#define VIP_SYS_REG_RST_IMG_D_OFFSET 2
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#define VIP_SYS_REG_RST_IMG_D_MASK 0x4
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#define VIP_SYS_REG_RST_IMG_D_BITS 0x1
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#define VIP_SYS_REG_RST_IMG_V 0x0
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#define VIP_SYS_REG_RST_IMG_V_OFFSET 3
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#define VIP_SYS_REG_RST_IMG_V_MASK 0x8
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#define VIP_SYS_REG_RST_IMG_V_BITS 0x1
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#define VIP_SYS_REG_RST_SC_TOP 0x0
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#define VIP_SYS_REG_RST_SC_TOP_OFFSET 4
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#define VIP_SYS_REG_RST_SC_TOP_MASK 0x10
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#define VIP_SYS_REG_RST_SC_TOP_BITS 0x1
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#define VIP_SYS_REG_RST_SC_D 0x0
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#define VIP_SYS_REG_RST_SC_D_OFFSET 5
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#define VIP_SYS_REG_RST_SC_D_MASK 0x20
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#define VIP_SYS_REG_RST_SC_D_BITS 0x1
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#define VIP_SYS_REG_RST_SC_V1 0x0
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#define VIP_SYS_REG_RST_SC_V1_OFFSET 6
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#define VIP_SYS_REG_RST_SC_V1_MASK 0x40
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#define VIP_SYS_REG_RST_SC_V1_BITS 0x1
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#define VIP_SYS_REG_RST_SC_V2 0x0
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#define VIP_SYS_REG_RST_SC_V2_OFFSET 7
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#define VIP_SYS_REG_RST_SC_V2_MASK 0x80
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#define VIP_SYS_REG_RST_SC_V2_BITS 0x1
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#define VIP_SYS_REG_RST_SC_V3 0x0
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#define VIP_SYS_REG_RST_SC_V3_OFFSET 8
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#define VIP_SYS_REG_RST_SC_V3_MASK 0x100
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#define VIP_SYS_REG_RST_SC_V3_BITS 0x1
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#define VIP_SYS_REG_RST_DISP 0x0
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#define VIP_SYS_REG_RST_DISP_OFFSET 9
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#define VIP_SYS_REG_RST_DISP_MASK 0x200
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#define VIP_SYS_REG_RST_DISP_BITS 0x1
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#define VIP_SYS_REG_RST_BT 0x0
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#define VIP_SYS_REG_RST_BT_OFFSET 10
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#define VIP_SYS_REG_RST_BT_MASK 0x400
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#define VIP_SYS_REG_RST_BT_BITS 0x1
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#define VIP_SYS_REG_RST_DSI_MAC 0x0
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#define VIP_SYS_REG_RST_DSI_MAC_OFFSET 11
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#define VIP_SYS_REG_RST_DSI_MAC_MASK 0x800
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#define VIP_SYS_REG_RST_DSI_MAC_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_MAC0 0x0
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#define VIP_SYS_REG_RST_CSI_MAC0_OFFSET 12
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#define VIP_SYS_REG_RST_CSI_MAC0_MASK 0x1000
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#define VIP_SYS_REG_RST_CSI_MAC0_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_MAC1 0x0
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#define VIP_SYS_REG_RST_CSI_MAC1_OFFSET 13
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#define VIP_SYS_REG_RST_CSI_MAC1_MASK 0x2000
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#define VIP_SYS_REG_RST_CSI_MAC1_BITS 0x1
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#define VIP_SYS_REG_RST_LDC_TOP 0x0
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#define VIP_SYS_REG_RST_LDC_TOP_OFFSET 14
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#define VIP_SYS_REG_RST_LDC_TOP_MASK 0x4000
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#define VIP_SYS_REG_RST_LDC_TOP_BITS 0x1
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#define VIP_SYS_REG_RST_CLK_BT_DIV 0x0
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#define VIP_SYS_REG_RST_CLK_BT_DIV_OFFSET 15
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#define VIP_SYS_REG_RST_CLK_BT_DIV_MASK 0x8000
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#define VIP_SYS_REG_RST_CLK_BT_DIV_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_MAC2 0x0
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#define VIP_SYS_REG_RST_CSI_MAC2_OFFSET 16
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#define VIP_SYS_REG_RST_CSI_MAC2_MASK 0x10000
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#define VIP_SYS_REG_RST_CSI_MAC2_BITS 0x1
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#define VIP_SYS_REG_RST_ISP_TOP_APB 0x0
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#define VIP_SYS_REG_RST_ISP_TOP_APB_OFFSET 17
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#define VIP_SYS_REG_RST_ISP_TOP_APB_MASK 0x20000
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#define VIP_SYS_REG_RST_ISP_TOP_APB_BITS 0x1
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#define VIP_SYS_REG_RST_SC_TOP_APB 0x0
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#define VIP_SYS_REG_RST_SC_TOP_APB_OFFSET 18
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#define VIP_SYS_REG_RST_SC_TOP_APB_MASK 0x40000
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#define VIP_SYS_REG_RST_SC_TOP_APB_BITS 0x1
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#define VIP_SYS_REG_RST_LDC_TOP_APB 0x0
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#define VIP_SYS_REG_RST_LDC_TOP_APB_OFFSET 19
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#define VIP_SYS_REG_RST_LDC_TOP_APB_MASK 0x80000
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#define VIP_SYS_REG_RST_LDC_TOP_APB_BITS 0x1
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#define VIP_SYS_REG_RST_DSI_MAC_APB 0x0
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#define VIP_SYS_REG_RST_DSI_MAC_APB_OFFSET 20
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#define VIP_SYS_REG_RST_DSI_MAC_APB_MASK 0x100000
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#define VIP_SYS_REG_RST_DSI_MAC_APB_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_MAC0_APB 0x0
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#define VIP_SYS_REG_RST_CSI_MAC0_APB_OFFSET 21
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#define VIP_SYS_REG_RST_CSI_MAC0_APB_MASK 0x200000
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#define VIP_SYS_REG_RST_CSI_MAC0_APB_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_MAC1_APB 0x0
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#define VIP_SYS_REG_RST_CSI_MAC1_APB_OFFSET 22
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#define VIP_SYS_REG_RST_CSI_MAC1_APB_MASK 0x400000
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#define VIP_SYS_REG_RST_CSI_MAC1_APB_BITS 0x1
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#define VIP_SYS_REG_RST_DSI_PHY_APB 0x0
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#define VIP_SYS_REG_RST_DSI_PHY_APB_OFFSET 23
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#define VIP_SYS_REG_RST_DSI_PHY_APB_MASK 0x800000
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#define VIP_SYS_REG_RST_DSI_PHY_APB_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_PHY0_APB 0x0
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#define VIP_SYS_REG_RST_CSI_PHY0_APB_OFFSET 24
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#define VIP_SYS_REG_RST_CSI_PHY0_APB_MASK 0x1000000
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#define VIP_SYS_REG_RST_CSI_PHY0_APB_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_PHY1_APB 0x0
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#define VIP_SYS_REG_RST_CSI_PHY1_APB_OFFSET 25
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#define VIP_SYS_REG_RST_CSI_PHY1_APB_MASK 0x2000000
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#define VIP_SYS_REG_RST_CSI_PHY1_APB_BITS 0x1
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#define VIP_SYS_REG_RST_DSI_PHY 0x0
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#define VIP_SYS_REG_RST_DSI_PHY_OFFSET 26
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#define VIP_SYS_REG_RST_DSI_PHY_MASK 0x4000000
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#define VIP_SYS_REG_RST_DSI_PHY_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_PHY0 0x0
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#define VIP_SYS_REG_RST_CSI_PHY0_OFFSET 27
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#define VIP_SYS_REG_RST_CSI_PHY0_MASK 0x8000000
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#define VIP_SYS_REG_RST_CSI_PHY0_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_PHY1 0x0
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#define VIP_SYS_REG_RST_CSI_PHY1_OFFSET 28
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#define VIP_SYS_REG_RST_CSI_PHY1_MASK 0x10000000
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#define VIP_SYS_REG_RST_CSI_PHY1_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_BE 0x0
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#define VIP_SYS_REG_RST_CSI_BE_OFFSET 29
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#define VIP_SYS_REG_RST_CSI_BE_MASK 0x20000000
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#define VIP_SYS_REG_RST_CSI_BE_BITS 0x1
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#define VIP_SYS_REG_RST_CSI_MAC2_APB 0x0
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#define VIP_SYS_REG_RST_CSI_MAC2_APB_OFFSET 30
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#define VIP_SYS_REG_RST_CSI_MAC2_APB_MASK 0x40000000
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#define VIP_SYS_REG_RST_CSI_MAC2_APB_BITS 0x1
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#define VIP_SYS_REG_RST_REV 0x0
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#define VIP_SYS_REG_RST_REV_OFFSET 31
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#define VIP_SYS_REG_RST_REV_MASK 0x80000000
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#define VIP_SYS_REG_RST_REV_BITS 0x1
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#define VIP_SYS_REG_CLK_AXI_ISP_TOP_EN 0x4
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#define VIP_SYS_REG_CLK_AXI_ISP_TOP_EN_OFFSET 0
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#define VIP_SYS_REG_CLK_AXI_ISP_TOP_EN_MASK 0x1
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#define VIP_SYS_REG_CLK_AXI_ISP_TOP_EN_BITS 0x1
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#define VIP_SYS_REG_EN_REV0 0x4
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#define VIP_SYS_REG_EN_REV0_OFFSET 1
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#define VIP_SYS_REG_EN_REV0_MASK 0xfffe
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#define VIP_SYS_REG_EN_REV0_BITS 0xf
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#define VIP_SYS_REG_EN_REV1 0x4
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#define VIP_SYS_REG_EN_REV1_OFFSET 16
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#define VIP_SYS_REG_EN_REV1_MASK 0xffff0000
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#define VIP_SYS_REG_EN_REV1_BITS 0x10
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#define VIP_SYS_INT_SC_TOP 0x8
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#define VIP_SYS_INT_SC_TOP_OFFSET 0
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#define VIP_SYS_INT_SC_TOP_MASK 0x1
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#define VIP_SYS_INT_SC_TOP_BITS 0x1
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#define VIP_SYS_INT_ISP_TOP 0x8
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#define VIP_SYS_INT_ISP_TOP_OFFSET 16
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#define VIP_SYS_INT_ISP_TOP_MASK 0x10000
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#define VIP_SYS_INT_ISP_TOP_BITS 0x1
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#define VIP_SYS_INT_LDC_TOP 0x8
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#define VIP_SYS_INT_LDC_TOP_OFFSET 24
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#define VIP_SYS_INT_LDC_TOP_MASK 0x1000000
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#define VIP_SYS_INT_LDC_TOP_BITS 0x1
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#define VIP_SYS_INT_IVE_TOP 0x8
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#define VIP_SYS_INT_IVE_TOP_OFFSET 25
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#define VIP_SYS_INT_IVE_TOP_MASK 0x2000000
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#define VIP_SYS_INT_IVE_TOP_BITS 0x1
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#define VIP_SYS_INT_CSI_MAC0 0x8
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#define VIP_SYS_INT_CSI_MAC0_OFFSET 28
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#define VIP_SYS_INT_CSI_MAC0_MASK 0x10000000
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#define VIP_SYS_INT_CSI_MAC0_BITS 0x1
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#define VIP_SYS_INT_CSI_MAC1 0x8
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#define VIP_SYS_INT_CSI_MAC1_OFFSET 29
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#define VIP_SYS_INT_CSI_MAC1_MASK 0x20000000
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#define VIP_SYS_INT_CSI_MAC1_BITS 0x1
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#define VIP_SYS_REG_PORT_SEL_SC_OFF 0x10
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#define VIP_SYS_REG_PORT_SEL_SC_OFF_OFFSET 0
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#define VIP_SYS_REG_PORT_SEL_SC_OFF_MASK 0x1
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#define VIP_SYS_REG_PORT_SEL_SC_OFF_BITS 0x1
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#define VIP_SYS_REG_PORT_SEL_ISP_OFF0 0x10
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#define VIP_SYS_REG_PORT_SEL_ISP_OFF0_OFFSET 1
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#define VIP_SYS_REG_PORT_SEL_ISP_OFF0_MASK 0x2
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#define VIP_SYS_REG_PORT_SEL_ISP_OFF0_BITS 0x1
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#define VIP_SYS_REG_PORT_SEL_ISP_OFF1 0x10
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#define VIP_SYS_REG_PORT_SEL_ISP_OFF1_OFFSET 2
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#define VIP_SYS_REG_PORT_SEL_ISP_OFF1_MASK 0x4
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#define VIP_SYS_REG_PORT_SEL_ISP_OFF1_BITS 0x1
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#define VIP_SYS_REG_PORT_SEL_LDC_OFF 0x10
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#define VIP_SYS_REG_PORT_SEL_LDC_OFF_OFFSET 3
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#define VIP_SYS_REG_PORT_SEL_LDC_OFF_MASK 0x8
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#define VIP_SYS_REG_PORT_SEL_LDC_OFF_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_SC_TOP 0x14
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#define VIP_SYS_APB_CLK_EN_SC_TOP_OFFSET 0
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#define VIP_SYS_APB_CLK_EN_SC_TOP_MASK 0x1
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#define VIP_SYS_APB_CLK_EN_SC_TOP_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_ISP_TOP 0x14
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#define VIP_SYS_APB_CLK_EN_ISP_TOP_OFFSET 1
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#define VIP_SYS_APB_CLK_EN_ISP_TOP_MASK 0x2
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#define VIP_SYS_APB_CLK_EN_ISP_TOP_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_LDC_TOP 0x14
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#define VIP_SYS_APB_CLK_EN_LDC_TOP_OFFSET 2
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#define VIP_SYS_APB_CLK_EN_LDC_TOP_MASK 0x4
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#define VIP_SYS_APB_CLK_EN_LDC_TOP_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_IVE_TOP 0x14
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#define VIP_SYS_APB_CLK_EN_IVE_TOP_OFFSET 3
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#define VIP_SYS_APB_CLK_EN_IVE_TOP_MASK 0x8
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#define VIP_SYS_APB_CLK_EN_IVE_TOP_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_VIP_SYS 0x14
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#define VIP_SYS_APB_CLK_EN_VIP_SYS_OFFSET 4
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#define VIP_SYS_APB_CLK_EN_VIP_SYS_MASK 0x10
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#define VIP_SYS_APB_CLK_EN_VIP_SYS_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_CSI_PHY0 0x14
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#define VIP_SYS_APB_CLK_EN_CSI_PHY0_OFFSET 5
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#define VIP_SYS_APB_CLK_EN_CSI_PHY0_MASK 0x20
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#define VIP_SYS_APB_CLK_EN_CSI_PHY0_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_DSI_PHY 0x14
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#define VIP_SYS_APB_CLK_EN_DSI_PHY_OFFSET 6
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#define VIP_SYS_APB_CLK_EN_DSI_PHY_MASK 0x40
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#define VIP_SYS_APB_CLK_EN_DSI_PHY_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_CSI_MAC0 0x14
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#define VIP_SYS_APB_CLK_EN_CSI_MAC0_OFFSET 8
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#define VIP_SYS_APB_CLK_EN_CSI_MAC0_MASK 0x100
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#define VIP_SYS_APB_CLK_EN_CSI_MAC0_BITS 0x1
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#define VIP_SYS_APB_CLK_EN_CSI_MAC1 0x14
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#define VIP_SYS_APB_CLK_EN_CSI_MAC1_OFFSET 9
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#define VIP_SYS_APB_CLK_EN_CSI_MAC1_MASK 0x200
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#define VIP_SYS_APB_CLK_EN_CSI_MAC1_BITS 0x1
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#define VIP_SYS_SC_X2P_BUSY_EN 0x14
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#define VIP_SYS_SC_X2P_BUSY_EN_OFFSET 12
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#define VIP_SYS_SC_X2P_BUSY_EN_MASK 0x1000
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#define VIP_SYS_SC_X2P_BUSY_EN_BITS 0x1
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#define VIP_SYS_ISP_X2P_BUSY_EN 0x14
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#define VIP_SYS_ISP_X2P_BUSY_EN_OFFSET 13
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#define VIP_SYS_ISP_X2P_BUSY_EN_MASK 0x2000
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#define VIP_SYS_ISP_X2P_BUSY_EN_BITS 0x1
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#define VIP_SYS_LDC_X2P_BUSY_EN 0x14
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#define VIP_SYS_LDC_X2P_BUSY_EN_OFFSET 14
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#define VIP_SYS_LDC_X2P_BUSY_EN_MASK 0x4000
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#define VIP_SYS_LDC_X2P_BUSY_EN_BITS 0x1
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#define VIP_SYS_IVE_X2P_BUSY_EN 0x14
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#define VIP_SYS_IVE_X2P_BUSY_EN_OFFSET 15
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#define VIP_SYS_IVE_X2P_BUSY_EN_MASK 0x8000
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#define VIP_SYS_IVE_X2P_BUSY_EN_BITS 0x1
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#define VIP_SYS_APB_AUTO_GATING_EN_SC_TOP 0x14
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#define VIP_SYS_APB_AUTO_GATING_EN_SC_TOP_OFFSET 16
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#define VIP_SYS_APB_AUTO_GATING_EN_SC_TOP_MASK 0x10000
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#define VIP_SYS_APB_AUTO_GATING_EN_SC_TOP_BITS 0x1
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#define VIP_SYS_APB_AUTO_GATING_EN_ISP_TOP 0x14
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#define VIP_SYS_APB_AUTO_GATING_EN_ISP_TOP_OFFSET 17
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#define VIP_SYS_APB_AUTO_GATING_EN_ISP_TOP_MASK 0x20000
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#define VIP_SYS_APB_AUTO_GATING_EN_ISP_TOP_BITS 0x1
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#define VIP_SYS_APB_AUTO_GATING_EN_LDC_TOP 0x14
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#define VIP_SYS_APB_AUTO_GATING_EN_LDC_TOP_OFFSET 18
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#define VIP_SYS_APB_AUTO_GATING_EN_LDC_TOP_MASK 0x40000
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#define VIP_SYS_APB_AUTO_GATING_EN_LDC_TOP_BITS 0x1
|
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#define VIP_SYS_APB_AUTO_GATING_EN_IVE_TOP 0x14
|
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#define VIP_SYS_APB_AUTO_GATING_EN_IVE_TOP_OFFSET 19
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_IVE_TOP_MASK 0x80000
|
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#define VIP_SYS_APB_AUTO_GATING_EN_IVE_TOP_BITS 0x1
|
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#define VIP_SYS_APB_AUTO_GATING_EN_VIP_SYS 0x14
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_VIP_SYS_OFFSET 20
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_VIP_SYS_MASK 0x100000
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_VIP_SYS_BITS 0x1
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_PHY0 0x14
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_PHY0_OFFSET 21
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_PHY0_MASK 0x200000
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_PHY0_BITS 0x1
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_DSI_PHY 0x14
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_DSI_PHY_OFFSET 22
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_DSI_PHY_MASK 0x400000
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_DSI_PHY_BITS 0x1
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC0 0x14
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC0_OFFSET 24
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC0_MASK 0x1000000
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC0_BITS 0x1
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC1 0x14
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC1_OFFSET 25
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC1_MASK 0x2000000
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC1_BITS 0x1
|
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#define VIP_SYS_APB_CLK_EN_CSI_MAC2 0x14
|
|
#define VIP_SYS_APB_CLK_EN_CSI_MAC2_OFFSET 26
|
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#define VIP_SYS_APB_CLK_EN_CSI_MAC2_MASK 0x4000000
|
|
#define VIP_SYS_APB_CLK_EN_CSI_MAC2_BITS 0x1
|
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#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC2 0x14
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC2_OFFSET 27
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC2_MASK 0x8000000
|
|
#define VIP_SYS_APB_AUTO_GATING_EN_CSI_MAC2_BITS 0x1
|
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#define VIP_SYS_CLK_BT_SRC_SEL 0x18
|
|
#define VIP_SYS_CLK_BT_SRC_SEL_OFFSET 0
|
|
#define VIP_SYS_CLK_BT_SRC_SEL_MASK 0x3
|
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#define VIP_SYS_CLK_BT_SRC_SEL_BITS 0x2
|
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#define VIP_SYS_CLK_LVDS0_SRC_SEL 0x18
|
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#define VIP_SYS_CLK_LVDS0_SRC_SEL_OFFSET 2
|
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#define VIP_SYS_CLK_LVDS0_SRC_SEL_MASK 0x4
|
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#define VIP_SYS_CLK_LVDS0_SRC_SEL_BITS 0x1
|
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#define VIP_SYS_CLK_LVDS1_SRC_SEL 0x18
|
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#define VIP_SYS_CLK_LVDS1_SRC_SEL_OFFSET 3
|
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#define VIP_SYS_CLK_LVDS1_SRC_SEL_MASK 0x8
|
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#define VIP_SYS_CLK_LVDS1_SRC_SEL_BITS 0x1
|
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#define VIP_SYS_CLK_DISP_SEL_BT_DIV1 0x18
|
|
#define VIP_SYS_CLK_DISP_SEL_BT_DIV1_OFFSET 4
|
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#define VIP_SYS_CLK_DISP_SEL_BT_DIV1_MASK 0x10
|
|
#define VIP_SYS_CLK_DISP_SEL_BT_DIV1_BITS 0x1
|
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#define VIP_SYS_CLK_DISP_DIV_CNT 0x18
|
|
#define VIP_SYS_CLK_DISP_DIV_CNT_OFFSET 5
|
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#define VIP_SYS_CLK_DISP_DIV_CNT_MASK 0xe0
|
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#define VIP_SYS_CLK_DISP_DIV_CNT_BITS 0x3
|
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#define VIP_SYS_CLK_DSI_MAC_SRC_SEL 0x18
|
|
#define VIP_SYS_CLK_DSI_MAC_SRC_SEL_OFFSET 8
|
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#define VIP_SYS_CLK_DSI_MAC_SRC_SEL_MASK 0x100
|
|
#define VIP_SYS_CLK_DSI_MAC_SRC_SEL_BITS 0x1
|
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#define VIP_SYS_CLK_CSI0_RX_SRC_SEL 0x18
|
|
#define VIP_SYS_CLK_CSI0_RX_SRC_SEL_OFFSET 10
|
|
#define VIP_SYS_CLK_CSI0_RX_SRC_SEL_MASK 0x400
|
|
#define VIP_SYS_CLK_CSI0_RX_SRC_SEL_BITS 0x1
|
|
#define VIP_SYS_CLK_CSI1_RX_SRC_SEL 0x18
|
|
#define VIP_SYS_CLK_CSI1_RX_SRC_SEL_OFFSET 11
|
|
#define VIP_SYS_CLK_CSI1_RX_SRC_SEL_MASK 0x800
|
|
#define VIP_SYS_CLK_CSI1_RX_SRC_SEL_BITS 0x1
|
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#define VIP_SYS_PAD_VI0_CLK_SRC_SEL 0x18
|
|
#define VIP_SYS_PAD_VI0_CLK_SRC_SEL_OFFSET 12
|
|
#define VIP_SYS_PAD_VI0_CLK_SRC_SEL_MASK 0x1000
|
|
#define VIP_SYS_PAD_VI0_CLK_SRC_SEL_BITS 0x1
|
|
#define VIP_SYS_PAD_VI1_CLK_SRC_SEL 0x18
|
|
#define VIP_SYS_PAD_VI1_CLK_SRC_SEL_OFFSET 13
|
|
#define VIP_SYS_PAD_VI1_CLK_SRC_SEL_MASK 0x2000
|
|
#define VIP_SYS_PAD_VI1_CLK_SRC_SEL_BITS 0x1
|
|
#define VIP_SYS_PAD_VI2_CLK_SRC_SEL 0x18
|
|
#define VIP_SYS_PAD_VI2_CLK_SRC_SEL_OFFSET 14
|
|
#define VIP_SYS_PAD_VI2_CLK_SRC_SEL_MASK 0x4000
|
|
#define VIP_SYS_PAD_VI2_CLK_SRC_SEL_BITS 0x1
|
|
#define VIP_SYS_CLK_DISP_DIV_UP_W1T 0x18
|
|
#define VIP_SYS_CLK_DISP_DIV_UP_W1T_OFFSET 16
|
|
#define VIP_SYS_CLK_DISP_DIV_UP_W1T_MASK 0x10000
|
|
#define VIP_SYS_CLK_DISP_DIV_UP_W1T_BITS 0x1
|
|
#define VIP_SYS_CLK_VIP_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_VIP_SRC_SEL_OFFSET 0
|
|
#define VIP_SYS_CLK_VIP_SRC_SEL_MASK 0x1
|
|
#define VIP_SYS_CLK_VIP_SRC_SEL_BITS 0x1
|
|
#define VIP_SYS_CLK_CSI_MAC0_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_CSI_MAC0_SRC_SEL_OFFSET 4
|
|
#define VIP_SYS_CLK_CSI_MAC0_SRC_SEL_MASK 0x30
|
|
#define VIP_SYS_CLK_CSI_MAC0_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_CLK_CSI_MAC1_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_CSI_MAC1_SRC_SEL_OFFSET 8
|
|
#define VIP_SYS_CLK_CSI_MAC1_SRC_SEL_MASK 0x300
|
|
#define VIP_SYS_CLK_CSI_MAC1_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_CLK_CSI_BE_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_CSI_BE_SRC_SEL_OFFSET 12
|
|
#define VIP_SYS_CLK_CSI_BE_SRC_SEL_MASK 0x3000
|
|
#define VIP_SYS_CLK_CSI_BE_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_CLK_ISP_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_ISP_SRC_SEL_OFFSET 16
|
|
#define VIP_SYS_CLK_ISP_SRC_SEL_MASK 0x30000
|
|
#define VIP_SYS_CLK_ISP_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_CLK_LDC_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_LDC_SRC_SEL_OFFSET 20
|
|
#define VIP_SYS_CLK_LDC_SRC_SEL_MASK 0x100000
|
|
#define VIP_SYS_CLK_LDC_SRC_SEL_BITS 0x1
|
|
#define VIP_SYS_CLK_IVE_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_IVE_SRC_SEL_OFFSET 21
|
|
#define VIP_SYS_CLK_IVE_SRC_SEL_MASK 0x600000
|
|
#define VIP_SYS_CLK_IVE_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_ISP_CLK_CSI1_SRC_SEL 0x1c
|
|
#define VIP_SYS_ISP_CLK_CSI1_SRC_SEL_OFFSET 24
|
|
#define VIP_SYS_ISP_CLK_CSI1_SRC_SEL_MASK 0x3000000
|
|
#define VIP_SYS_ISP_CLK_CSI1_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_CLK_RAW_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_RAW_SRC_SEL_OFFSET 26
|
|
#define VIP_SYS_CLK_RAW_SRC_SEL_MASK 0xc000000
|
|
#define VIP_SYS_CLK_RAW_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_CLK_OSDC_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_OSDC_SRC_SEL_OFFSET 28
|
|
#define VIP_SYS_CLK_OSDC_SRC_SEL_MASK 0x30000000
|
|
#define VIP_SYS_CLK_OSDC_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_CLK_CSI_MAC2_SRC_SEL 0x1c
|
|
#define VIP_SYS_CLK_CSI_MAC2_SRC_SEL_OFFSET 30
|
|
#define VIP_SYS_CLK_CSI_MAC2_SRC_SEL_MASK 0xc0000000
|
|
#define VIP_SYS_CLK_CSI_MAC2_SRC_SEL_BITS 0x2
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_AXI_RT 0x20
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_AXI_RT_OFFSET 0
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_AXI_RT_MASK 0x1
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_AXI_RT_BITS 0x1
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_AXI_RT 0x20
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_AXI_RT_OFFSET 1
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_AXI_RT_MASK 0x2
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_AXI_RT_BITS 0x1
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_AXI_RT 0x20
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_AXI_RT_OFFSET 8
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_AXI_RT_MASK 0x3f00
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_AXI_RT_BITS 0x6
|
|
#define VIP_SYS_REG_DIS_FAB_LP_OPT_AXI_RT 0x20
|
|
#define VIP_SYS_REG_DIS_FAB_LP_OPT_AXI_RT_OFFSET 16
|
|
#define VIP_SYS_REG_DIS_FAB_LP_OPT_AXI_RT_MASK 0xff0000
|
|
#define VIP_SYS_REG_DIS_FAB_LP_OPT_AXI_RT_BITS 0x8
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_AXI_OFF 0x24
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_AXI_OFF_OFFSET 0
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_AXI_OFF_MASK 0x1
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_AXI_OFF_BITS 0x1
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_AXI_OFF 0x24
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_AXI_OFF_OFFSET 1
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_AXI_OFF_MASK 0x2
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_AXI_OFF_BITS 0x1
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_AXI_OFF 0x24
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_AXI_OFF_OFFSET 8
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_AXI_OFF_MASK 0x3f00
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_AXI_OFF_BITS 0x6
|
|
#define VIP_SYS_REG_DIS_FAB_LP_OPT_AXI_OFF 0x24
|
|
#define VIP_SYS_REG_DIS_FAB_LP_OPT_AXI_OFF_OFFSET 16
|
|
#define VIP_SYS_REG_DIS_FAB_LP_OPT_AXI_OFF_MASK 0xff0000
|
|
#define VIP_SYS_REG_DIS_FAB_LP_OPT_AXI_OFF_BITS 0x8
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_X2P 0x28
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_X2P_OFFSET 0
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_X2P_MASK 0x1
|
|
#define VIP_SYS_REG_LP_DISABLE_VIP_X2P_BITS 0x1
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_X2P 0x28
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_X2P_OFFSET 1
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_X2P_MASK 0x2
|
|
#define VIP_SYS_REG_LP_LOCK_VIP_X2P_BITS 0x1
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_X2P 0x28
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_X2P_OFFSET 8
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_X2P_MASK 0x3f00
|
|
#define VIP_SYS_REG_LP_CTRL_VIP_X2P_BITS 0x6
|
|
#define VIP_SYS_REG_LP_DISABLE_SC_AXI_FAB_M0 0x2c
|
|
#define VIP_SYS_REG_LP_DISABLE_SC_AXI_FAB_M0_OFFSET 0
|
|
#define VIP_SYS_REG_LP_DISABLE_SC_AXI_FAB_M0_MASK 0x1
|
|
#define VIP_SYS_REG_LP_DISABLE_SC_AXI_FAB_M0_BITS 0x1
|
|
#define VIP_SYS_REG_LP_LOCK_SC_AXI_FAB_M0 0x2c
|
|
#define VIP_SYS_REG_LP_LOCK_SC_AXI_FAB_M0_OFFSET 1
|
|
#define VIP_SYS_REG_LP_LOCK_SC_AXI_FAB_M0_MASK 0x2
|
|
#define VIP_SYS_REG_LP_LOCK_SC_AXI_FAB_M0_BITS 0x1
|
|
#define VIP_SYS_REG_LP_CTRL_SC_AXI_FAB_M0 0x2c
|
|
#define VIP_SYS_REG_LP_CTRL_SC_AXI_FAB_M0_OFFSET 8
|
|
#define VIP_SYS_REG_LP_CTRL_SC_AXI_FAB_M0_MASK 0x3f00
|
|
#define VIP_SYS_REG_LP_CTRL_SC_AXI_FAB_M0_BITS 0x6
|
|
#define VIP_SYS_REG_LP_DISABLE_SC_AXI_FAB_M1 0x2c
|
|
#define VIP_SYS_REG_LP_DISABLE_SC_AXI_FAB_M1_OFFSET 16
|
|
#define VIP_SYS_REG_LP_DISABLE_SC_AXI_FAB_M1_MASK 0x10000
|
|
#define VIP_SYS_REG_LP_DISABLE_SC_AXI_FAB_M1_BITS 0x1
|
|
#define VIP_SYS_REG_LP_LOCK_SC_AXI_FAB_M1 0x2c
|
|
#define VIP_SYS_REG_LP_LOCK_SC_AXI_FAB_M1_OFFSET 17
|
|
#define VIP_SYS_REG_LP_LOCK_SC_AXI_FAB_M1_MASK 0x20000
|
|
#define VIP_SYS_REG_LP_LOCK_SC_AXI_FAB_M1_BITS 0x1
|
|
#define VIP_SYS_REG_LP_CTRL_SC_AXI_FAB_M1 0x2c
|
|
#define VIP_SYS_REG_LP_CTRL_SC_AXI_FAB_M1_OFFSET 24
|
|
#define VIP_SYS_REG_LP_CTRL_SC_AXI_FAB_M1_MASK 0x3f000000
|
|
#define VIP_SYS_REG_LP_CTRL_SC_AXI_FAB_M1_BITS 0x6
|
|
#define VIP_SYS_REG_CK_COEF_ISP_TOP 0x30
|
|
#define VIP_SYS_REG_CK_COEF_ISP_TOP_OFFSET 0
|
|
#define VIP_SYS_REG_CK_COEF_ISP_TOP_MASK 0x1f
|
|
#define VIP_SYS_REG_CK_COEF_ISP_TOP_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_LDC 0x30
|
|
#define VIP_SYS_REG_CK_COEF_LDC_OFFSET 5
|
|
#define VIP_SYS_REG_CK_COEF_LDC_MASK 0x3e0
|
|
#define VIP_SYS_REG_CK_COEF_LDC_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_IMG_D 0x30
|
|
#define VIP_SYS_REG_CK_COEF_IMG_D_OFFSET 10
|
|
#define VIP_SYS_REG_CK_COEF_IMG_D_MASK 0x7c00
|
|
#define VIP_SYS_REG_CK_COEF_IMG_D_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_IMG_V 0x30
|
|
#define VIP_SYS_REG_CK_COEF_IMG_V_OFFSET 15
|
|
#define VIP_SYS_REG_CK_COEF_IMG_V_MASK 0xf8000
|
|
#define VIP_SYS_REG_CK_COEF_IMG_V_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_SC_D 0x30
|
|
#define VIP_SYS_REG_CK_COEF_SC_D_OFFSET 20
|
|
#define VIP_SYS_REG_CK_COEF_SC_D_MASK 0x1f00000
|
|
#define VIP_SYS_REG_CK_COEF_SC_D_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_SC_V1 0x30
|
|
#define VIP_SYS_REG_CK_COEF_SC_V1_OFFSET 25
|
|
#define VIP_SYS_REG_CK_COEF_SC_V1_MASK 0x3e000000
|
|
#define VIP_SYS_REG_CK_COEF_SC_V1_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_SC_V2 0x34
|
|
#define VIP_SYS_REG_CK_COEF_SC_V2_OFFSET 0
|
|
#define VIP_SYS_REG_CK_COEF_SC_V2_MASK 0x1f
|
|
#define VIP_SYS_REG_CK_COEF_SC_V2_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_SC_V3 0x34
|
|
#define VIP_SYS_REG_CK_COEF_SC_V3_OFFSET 5
|
|
#define VIP_SYS_REG_CK_COEF_SC_V3_MASK 0x3e0
|
|
#define VIP_SYS_REG_CK_COEF_SC_V3_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_CSI_MAC0 0x34
|
|
#define VIP_SYS_REG_CK_COEF_CSI_MAC0_OFFSET 10
|
|
#define VIP_SYS_REG_CK_COEF_CSI_MAC0_MASK 0x7c00
|
|
#define VIP_SYS_REG_CK_COEF_CSI_MAC0_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_CSI_MAC1 0x34
|
|
#define VIP_SYS_REG_CK_COEF_CSI_MAC1_OFFSET 15
|
|
#define VIP_SYS_REG_CK_COEF_CSI_MAC1_MASK 0xf8000
|
|
#define VIP_SYS_REG_CK_COEF_CSI_MAC1_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_OSDC 0x34
|
|
#define VIP_SYS_REG_CK_COEF_OSDC_OFFSET 20
|
|
#define VIP_SYS_REG_CK_COEF_OSDC_MASK 0x1f00000
|
|
#define VIP_SYS_REG_CK_COEF_OSDC_BITS 0x5
|
|
#define VIP_SYS_REG_CK_COEF_REV 0x34
|
|
#define VIP_SYS_REG_CK_COEF_REV_OFFSET 25
|
|
#define VIP_SYS_REG_CK_COEF_REV_MASK 0x3e000000
|
|
#define VIP_SYS_REG_CK_COEF_REV_BITS 0x5
|
|
#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC0 0x38
|
|
#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC0_OFFSET 0
|
|
#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC0_MASK 0x1
|
|
#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC0_BITS 0x1
|
|
#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC0 0x38
|
|
#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC0_OFFSET 1
|
|
#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC0_MASK 0x2
|
|
#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC0_BITS 0x1
|
|
#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC0 0x38
|
|
#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC0_OFFSET 2
|
|
#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC0_MASK 0x4
|
|
#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC0_BITS 0x1
|
|
#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC0 0x38
|
|
#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC0_OFFSET 8
|
|
#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC0_MASK 0x700
|
|
#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC0_BITS 0x3
|
|
#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC0 0x38
|
|
#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC0_OFFSET 12
|
|
#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC0_MASK 0x7000
|
|
#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC0_BITS 0x3
|
|
#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC0 0x38
|
|
#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC0_OFFSET 16
|
|
#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC0_MASK 0x1f0000
|
|
#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC0_BITS 0x5
|
|
#define VIP_SYS_REG_NORM_DIV_EN_ISP_TOP 0x3c
|
|
#define VIP_SYS_REG_NORM_DIV_EN_ISP_TOP_OFFSET 0
|
|
#define VIP_SYS_REG_NORM_DIV_EN_ISP_TOP_MASK 0x1
|
|
#define VIP_SYS_REG_NORM_DIV_EN_ISP_TOP_BITS 0x1
|
|
#define VIP_SYS_REG_IDLE_DIV_EN_ISP_TOP 0x3c
|
|
#define VIP_SYS_REG_IDLE_DIV_EN_ISP_TOP_OFFSET 1
|
|
#define VIP_SYS_REG_IDLE_DIV_EN_ISP_TOP_MASK 0x2
|
|
#define VIP_SYS_REG_IDLE_DIV_EN_ISP_TOP_BITS 0x1
|
|
#define VIP_SYS_REG_UPDATE_SEL_ISP_TOP 0x3c
|
|
#define VIP_SYS_REG_UPDATE_SEL_ISP_TOP_OFFSET 2
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#define VIP_SYS_REG_UPDATE_SEL_ISP_TOP_MASK 0x4
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#define VIP_SYS_REG_UPDATE_SEL_ISP_TOP_BITS 0x1
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#define VIP_SYS_REG_IDLE_SLOW_SEL_ISP_TOP 0x3c
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#define VIP_SYS_REG_IDLE_SLOW_SEL_ISP_TOP_OFFSET 8
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#define VIP_SYS_REG_IDLE_SLOW_SEL_ISP_TOP_MASK 0x700
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#define VIP_SYS_REG_IDLE_SLOW_SEL_ISP_TOP_BITS 0x3
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#define VIP_SYS_REG_IDLE_WAIT_SEL_ISP_TOP 0x3c
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#define VIP_SYS_REG_IDLE_WAIT_SEL_ISP_TOP_OFFSET 12
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#define VIP_SYS_REG_IDLE_WAIT_SEL_ISP_TOP_MASK 0x7000
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#define VIP_SYS_REG_IDLE_WAIT_SEL_ISP_TOP_BITS 0x3
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#define VIP_SYS_REG_NORM_DIV_VAL_ISP_TOP 0x3c
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#define VIP_SYS_REG_NORM_DIV_VAL_ISP_TOP_OFFSET 16
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#define VIP_SYS_REG_NORM_DIV_VAL_ISP_TOP_MASK 0x1f0000
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#define VIP_SYS_REG_NORM_DIV_VAL_ISP_TOP_BITS 0x5
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC1 0x40
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC1_OFFSET 0
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC1_MASK 0x1
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC1_BITS 0x1
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC1 0x40
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC1_OFFSET 1
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC1_MASK 0x2
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC1_BITS 0x1
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#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC1 0x40
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#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC1_OFFSET 2
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#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC1_MASK 0x4
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#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC1_BITS 0x1
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC1 0x40
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC1_OFFSET 8
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC1_MASK 0x700
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC1_BITS 0x3
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC1 0x40
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC1_OFFSET 12
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC1_MASK 0x7000
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC1_BITS 0x3
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#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC1 0x40
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#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC1_OFFSET 16
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#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC1_MASK 0x1f0000
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#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC1_BITS 0x5
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_BE 0x44
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_BE_OFFSET 0
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_BE_MASK 0x1
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_BE_BITS 0x1
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_BE 0x44
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_BE_OFFSET 1
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_BE_MASK 0x2
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_BE_BITS 0x1
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#define VIP_SYS_REG_UPDATE_SEL_CSI_BE 0x44
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#define VIP_SYS_REG_UPDATE_SEL_CSI_BE_OFFSET 2
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#define VIP_SYS_REG_UPDATE_SEL_CSI_BE_MASK 0x4
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#define VIP_SYS_REG_UPDATE_SEL_CSI_BE_BITS 0x1
|
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_BE 0x44
|
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_BE_OFFSET 8
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_BE_MASK 0x700
|
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_BE_BITS 0x3
|
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_BE 0x44
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_BE_OFFSET 12
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_BE_MASK 0x7000
|
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_BE_BITS 0x3
|
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#define VIP_SYS_REG_NORM_DIV_VAL_CSI_BE 0x44
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#define VIP_SYS_REG_NORM_DIV_VAL_CSI_BE_OFFSET 16
|
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#define VIP_SYS_REG_NORM_DIV_VAL_CSI_BE_MASK 0x1f0000
|
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#define VIP_SYS_REG_NORM_DIV_VAL_CSI_BE_BITS 0x5
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC2 0x48
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC2_OFFSET 0
|
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC2_MASK 0x1
|
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#define VIP_SYS_REG_NORM_DIV_EN_CSI_MAC2_BITS 0x1
|
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC2 0x48
|
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC2_OFFSET 1
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC2_MASK 0x2
|
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#define VIP_SYS_REG_IDLE_DIV_EN_CSI_MAC2_BITS 0x1
|
|
#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC2 0x48
|
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#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC2_OFFSET 2
|
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#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC2_MASK 0x4
|
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#define VIP_SYS_REG_UPDATE_SEL_CSI_MAC2_BITS 0x1
|
|
#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC2 0x48
|
|
#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC2_OFFSET 8
|
|
#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC2_MASK 0x700
|
|
#define VIP_SYS_REG_IDLE_SLOW_SEL_CSI_MAC2_BITS 0x3
|
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC2 0x48
|
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC2_OFFSET 12
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC2_MASK 0x7000
|
|
#define VIP_SYS_REG_IDLE_WAIT_SEL_CSI_MAC2_BITS 0x3
|
|
#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC2 0x48
|
|
#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC2_OFFSET 16
|
|
#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC2_MASK 0x1f0000
|
|
#define VIP_SYS_REG_NORM_DIV_VAL_CSI_MAC2_BITS 0x5
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|
#define VIP_SYS_CACTIVE_AXI_RT_FAB 0x50
|
|
#define VIP_SYS_CACTIVE_AXI_RT_FAB_OFFSET 0
|
|
#define VIP_SYS_CACTIVE_AXI_RT_FAB_MASK 0x1
|
|
#define VIP_SYS_CACTIVE_AXI_RT_FAB_BITS 0x1
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|
#define VIP_SYS_CSYSREQ_AXI_RT_FAB 0x50
|
|
#define VIP_SYS_CSYSREQ_AXI_RT_FAB_OFFSET 1
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#define VIP_SYS_CSYSREQ_AXI_RT_FAB_MASK 0x2
|
|
#define VIP_SYS_CSYSREQ_AXI_RT_FAB_BITS 0x1
|
|
#define VIP_SYS_CSYSACK_AXI_RT_FAB 0x50
|
|
#define VIP_SYS_CSYSACK_AXI_RT_FAB_OFFSET 2
|
|
#define VIP_SYS_CSYSACK_AXI_RT_FAB_MASK 0x4
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|
#define VIP_SYS_CSYSACK_AXI_RT_FAB_BITS 0x1
|
|
#define VIP_SYS_LPC_RT_FAB_LP_LOCK_O 0x50
|
|
#define VIP_SYS_LPC_RT_FAB_LP_LOCK_O_OFFSET 3
|
|
#define VIP_SYS_LPC_RT_FAB_LP_LOCK_O_MASK 0x8
|
|
#define VIP_SYS_LPC_RT_FAB_LP_LOCK_O_BITS 0x1
|
|
#define VIP_SYS_LPC_RT_FAB_LP_BUSY_O 0x50
|
|
#define VIP_SYS_LPC_RT_FAB_LP_BUSY_O_OFFSET 4
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#define VIP_SYS_LPC_RT_FAB_LP_BUSY_O_MASK 0x10
|
|
#define VIP_SYS_LPC_RT_FAB_LP_BUSY_O_BITS 0x1
|
|
#define VIP_SYS_CACTIVE_AXI_OFF_FAB 0x50
|
|
#define VIP_SYS_CACTIVE_AXI_OFF_FAB_OFFSET 5
|
|
#define VIP_SYS_CACTIVE_AXI_OFF_FAB_MASK 0x20
|
|
#define VIP_SYS_CACTIVE_AXI_OFF_FAB_BITS 0x1
|
|
#define VIP_SYS_CSYSREQ_AXI_OFF_FAB 0x50
|
|
#define VIP_SYS_CSYSREQ_AXI_OFF_FAB_OFFSET 6
|
|
#define VIP_SYS_CSYSREQ_AXI_OFF_FAB_MASK 0x40
|
|
#define VIP_SYS_CSYSREQ_AXI_OFF_FAB_BITS 0x1
|
|
#define VIP_SYS_CSYSACK_AXI_OFF_FAB 0x50
|
|
#define VIP_SYS_CSYSACK_AXI_OFF_FAB_OFFSET 7
|
|
#define VIP_SYS_CSYSACK_AXI_OFF_FAB_MASK 0x80
|
|
#define VIP_SYS_CSYSACK_AXI_OFF_FAB_BITS 0x1
|
|
#define VIP_SYS_LPC_OFF_FAB_LP_LOCK_O 0x50
|
|
#define VIP_SYS_LPC_OFF_FAB_LP_LOCK_O_OFFSET 8
|
|
#define VIP_SYS_LPC_OFF_FAB_LP_LOCK_O_MASK 0x100
|
|
#define VIP_SYS_LPC_OFF_FAB_LP_LOCK_O_BITS 0x1
|
|
#define VIP_SYS_LPC_OFF_FAB_LP_BUSY_O 0x50
|
|
#define VIP_SYS_LPC_OFF_FAB_LP_BUSY_O_OFFSET 9
|
|
#define VIP_SYS_LPC_OFF_FAB_LP_BUSY_O_MASK 0x200
|
|
#define VIP_SYS_LPC_OFF_FAB_LP_BUSY_O_BITS 0x1
|
|
#define VIP_SYS_CACTIVE_X2P 0x50
|
|
#define VIP_SYS_CACTIVE_X2P_OFFSET 10
|
|
#define VIP_SYS_CACTIVE_X2P_MASK 0x400
|
|
#define VIP_SYS_CACTIVE_X2P_BITS 0x1
|
|
#define VIP_SYS_CSYSREQ_X2P 0x50
|
|
#define VIP_SYS_CSYSREQ_X2P_OFFSET 11
|
|
#define VIP_SYS_CSYSREQ_X2P_MASK 0x800
|
|
#define VIP_SYS_CSYSREQ_X2P_BITS 0x1
|
|
#define VIP_SYS_CSYSACK_X2P 0x50
|
|
#define VIP_SYS_CSYSACK_X2P_OFFSET 12
|
|
#define VIP_SYS_CSYSACK_X2P_MASK 0x1000
|
|
#define VIP_SYS_CSYSACK_X2P_BITS 0x1
|
|
#define VIP_SYS_LPC_X2P_FAB_LP_LOCK_O 0x50
|
|
#define VIP_SYS_LPC_X2P_FAB_LP_LOCK_O_OFFSET 13
|
|
#define VIP_SYS_LPC_X2P_FAB_LP_LOCK_O_MASK 0x2000
|
|
#define VIP_SYS_LPC_X2P_FAB_LP_LOCK_O_BITS 0x1
|
|
#define VIP_SYS_LPC_X2P_FAB_LP_BUSY_O 0x50
|
|
#define VIP_SYS_LPC_X2P_FAB_LP_BUSY_O_OFFSET 14
|
|
#define VIP_SYS_LPC_X2P_FAB_LP_BUSY_O_MASK 0x4000
|
|
#define VIP_SYS_LPC_X2P_FAB_LP_BUSY_O_BITS 0x1
|
|
#define VIP_SYS_CACTIVE_SC_AXI_FAB_M0 0x50
|
|
#define VIP_SYS_CACTIVE_SC_AXI_FAB_M0_OFFSET 16
|
|
#define VIP_SYS_CACTIVE_SC_AXI_FAB_M0_MASK 0x10000
|
|
#define VIP_SYS_CACTIVE_SC_AXI_FAB_M0_BITS 0x1
|
|
#define VIP_SYS_CSYSREQ_SC_AXI_FAB_M0 0x50
|
|
#define VIP_SYS_CSYSREQ_SC_AXI_FAB_M0_OFFSET 17
|
|
#define VIP_SYS_CSYSREQ_SC_AXI_FAB_M0_MASK 0x20000
|
|
#define VIP_SYS_CSYSREQ_SC_AXI_FAB_M0_BITS 0x1
|
|
#define VIP_SYS_CSYSACK_SC_AXI_FAB_M0 0x50
|
|
#define VIP_SYS_CSYSACK_SC_AXI_FAB_M0_OFFSET 18
|
|
#define VIP_SYS_CSYSACK_SC_AXI_FAB_M0_MASK 0x40000
|
|
#define VIP_SYS_CSYSACK_SC_AXI_FAB_M0_BITS 0x1
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M0_LP_LOCK_O 0x50
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M0_LP_LOCK_O_OFFSET 19
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M0_LP_LOCK_O_MASK 0x80000
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M0_LP_LOCK_O_BITS 0x1
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M0_LP_BUSY_O 0x50
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M0_LP_BUSY_O_OFFSET 20
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M0_LP_BUSY_O_MASK 0x100000
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M0_LP_BUSY_O_BITS 0x1
|
|
#define VIP_SYS_CACTIVE_SC_AXI_FAB_M1 0x50
|
|
#define VIP_SYS_CACTIVE_SC_AXI_FAB_M1_OFFSET 21
|
|
#define VIP_SYS_CACTIVE_SC_AXI_FAB_M1_MASK 0x200000
|
|
#define VIP_SYS_CACTIVE_SC_AXI_FAB_M1_BITS 0x1
|
|
#define VIP_SYS_CSYSREQ_SC_AXI_FAB_M1 0x50
|
|
#define VIP_SYS_CSYSREQ_SC_AXI_FAB_M1_OFFSET 22
|
|
#define VIP_SYS_CSYSREQ_SC_AXI_FAB_M1_MASK 0x400000
|
|
#define VIP_SYS_CSYSREQ_SC_AXI_FAB_M1_BITS 0x1
|
|
#define VIP_SYS_CSYSACK_SC_AXI_FAB_M1 0x50
|
|
#define VIP_SYS_CSYSACK_SC_AXI_FAB_M1_OFFSET 23
|
|
#define VIP_SYS_CSYSACK_SC_AXI_FAB_M1_MASK 0x800000
|
|
#define VIP_SYS_CSYSACK_SC_AXI_FAB_M1_BITS 0x1
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M1_LP_LOCK_O 0x50
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M1_LP_LOCK_O_OFFSET 24
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M1_LP_LOCK_O_MASK 0x1000000
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M1_LP_LOCK_O_BITS 0x1
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M1_LP_BUSY_O 0x50
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M1_LP_BUSY_O_OFFSET 25
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M1_LP_BUSY_O_MASK 0x2000000
|
|
#define VIP_SYS_LPC_SC_AXI_FAB_M1_LP_BUSY_O_BITS 0x1
|
|
#define VIP_SYS_REG_SC_AXI_URGENT_AW_EN 0x5c
|
|
#define VIP_SYS_REG_SC_AXI_URGENT_AW_EN_OFFSET 0
|
|
#define VIP_SYS_REG_SC_AXI_URGENT_AW_EN_MASK 0x1
|
|
#define VIP_SYS_REG_SC_AXI_URGENT_AW_EN_BITS 0x1
|
|
#define VIP_SYS_REG_SC_AXI_URGENT_AR_EN 0x5c
|
|
#define VIP_SYS_REG_SC_AXI_URGENT_AR_EN_OFFSET 1
|
|
#define VIP_SYS_REG_SC_AXI_URGENT_AR_EN_MASK 0x2
|
|
#define VIP_SYS_REG_SC_AXI_URGENT_AR_EN_BITS 0x1
|
|
#define VIP_SYS_REG_AWURGENT_THRD_LOW_EN 0x5c
|
|
#define VIP_SYS_REG_AWURGENT_THRD_LOW_EN_OFFSET 8
|
|
#define VIP_SYS_REG_AWURGENT_THRD_LOW_EN_MASK 0x100
|
|
#define VIP_SYS_REG_AWURGENT_THRD_LOW_EN_BITS 0x1
|
|
#define VIP_SYS_REG_ARURGENT_THRD_LOW_EN 0x5c
|
|
#define VIP_SYS_REG_ARURGENT_THRD_LOW_EN_OFFSET 9
|
|
#define VIP_SYS_REG_ARURGENT_THRD_LOW_EN_MASK 0x200
|
|
#define VIP_SYS_REG_ARURGENT_THRD_LOW_EN_BITS 0x1
|
|
#define VIP_SYS_REG_AWURGENT_IDLE_CLR 0x5c
|
|
#define VIP_SYS_REG_AWURGENT_IDLE_CLR_OFFSET 16
|
|
#define VIP_SYS_REG_AWURGENT_IDLE_CLR_MASK 0x10000
|
|
#define VIP_SYS_REG_AWURGENT_IDLE_CLR_BITS 0x1
|
|
#define VIP_SYS_REG_ARURGENT_IDLE_CLR 0x5c
|
|
#define VIP_SYS_REG_ARURGENT_IDLE_CLR_OFFSET 17
|
|
#define VIP_SYS_REG_ARURGENT_IDLE_CLR_MASK 0x20000
|
|
#define VIP_SYS_REG_ARURGENT_IDLE_CLR_BITS 0x1
|
|
#define VIP_SYS_REG_AWQOS_OW_ISP 0x60
|
|
#define VIP_SYS_REG_AWQOS_OW_ISP_OFFSET 0
|
|
#define VIP_SYS_REG_AWQOS_OW_ISP_MASK 0x1
|
|
#define VIP_SYS_REG_AWQOS_OW_ISP_BITS 0x1
|
|
#define VIP_SYS_REG_ARQOS_OW_ISP 0x60
|
|
#define VIP_SYS_REG_ARQOS_OW_ISP_OFFSET 1
|
|
#define VIP_SYS_REG_ARQOS_OW_ISP_MASK 0x2
|
|
#define VIP_SYS_REG_ARQOS_OW_ISP_BITS 0x1
|
|
#define VIP_SYS_REG_AWQOS_OW_SC 0x60
|
|
#define VIP_SYS_REG_AWQOS_OW_SC_OFFSET 2
|
|
#define VIP_SYS_REG_AWQOS_OW_SC_MASK 0x4
|
|
#define VIP_SYS_REG_AWQOS_OW_SC_BITS 0x1
|
|
#define VIP_SYS_REG_ARQOS_OW_SC 0x60
|
|
#define VIP_SYS_REG_ARQOS_OW_SC_OFFSET 3
|
|
#define VIP_SYS_REG_ARQOS_OW_SC_MASK 0x8
|
|
#define VIP_SYS_REG_ARQOS_OW_SC_BITS 0x1
|
|
#define VIP_SYS_REG_AWQOS_OW_SC_M1 0x60
|
|
#define VIP_SYS_REG_AWQOS_OW_SC_M1_OFFSET 4
|
|
#define VIP_SYS_REG_AWQOS_OW_SC_M1_MASK 0x10
|
|
#define VIP_SYS_REG_AWQOS_OW_SC_M1_BITS 0x1
|
|
#define VIP_SYS_REG_ARQOS_OW_SC_M1 0x60
|
|
#define VIP_SYS_REG_ARQOS_OW_SC_M1_OFFSET 5
|
|
#define VIP_SYS_REG_ARQOS_OW_SC_M1_MASK 0x20
|
|
#define VIP_SYS_REG_ARQOS_OW_SC_M1_BITS 0x1
|
|
#define VIP_SYS_REG_AWQOS_OW_ISP_M1 0x60
|
|
#define VIP_SYS_REG_AWQOS_OW_ISP_M1_OFFSET 6
|
|
#define VIP_SYS_REG_AWQOS_OW_ISP_M1_MASK 0x40
|
|
#define VIP_SYS_REG_AWQOS_OW_ISP_M1_BITS 0x1
|
|
#define VIP_SYS_REG_ARQOS_OW_ISP_M1 0x60
|
|
#define VIP_SYS_REG_ARQOS_OW_ISP_M1_OFFSET 7
|
|
#define VIP_SYS_REG_ARQOS_OW_ISP_M1_MASK 0x80
|
|
#define VIP_SYS_REG_ARQOS_OW_ISP_M1_BITS 0x1
|
|
#define VIP_SYS_REG_AWQOS_ISP 0x64
|
|
#define VIP_SYS_REG_AWQOS_ISP_OFFSET 0
|
|
#define VIP_SYS_REG_AWQOS_ISP_MASK 0xf
|
|
#define VIP_SYS_REG_AWQOS_ISP_BITS 0x4
|
|
#define VIP_SYS_REG_ARQOS_ISP 0x64
|
|
#define VIP_SYS_REG_ARQOS_ISP_OFFSET 4
|
|
#define VIP_SYS_REG_ARQOS_ISP_MASK 0xf0
|
|
#define VIP_SYS_REG_ARQOS_ISP_BITS 0x4
|
|
#define VIP_SYS_REG_AWQOS_SC 0x64
|
|
#define VIP_SYS_REG_AWQOS_SC_OFFSET 8
|
|
#define VIP_SYS_REG_AWQOS_SC_MASK 0xf00
|
|
#define VIP_SYS_REG_AWQOS_SC_BITS 0x4
|
|
#define VIP_SYS_REG_ARQOS_SC 0x64
|
|
#define VIP_SYS_REG_ARQOS_SC_OFFSET 12
|
|
#define VIP_SYS_REG_ARQOS_SC_MASK 0xf000
|
|
#define VIP_SYS_REG_ARQOS_SC_BITS 0x4
|
|
#define VIP_SYS_REG_AWQOS_SC_M1 0x64
|
|
#define VIP_SYS_REG_AWQOS_SC_M1_OFFSET 16
|
|
#define VIP_SYS_REG_AWQOS_SC_M1_MASK 0xf0000
|
|
#define VIP_SYS_REG_AWQOS_SC_M1_BITS 0x4
|
|
#define VIP_SYS_REG_ARQOS_SC_M1 0x64
|
|
#define VIP_SYS_REG_ARQOS_SC_M1_OFFSET 20
|
|
#define VIP_SYS_REG_ARQOS_SC_M1_MASK 0xf00000
|
|
#define VIP_SYS_REG_ARQOS_SC_M1_BITS 0x4
|
|
#define VIP_SYS_REG_AWQOS_ISP_M1 0x64
|
|
#define VIP_SYS_REG_AWQOS_ISP_M1_OFFSET 24
|
|
#define VIP_SYS_REG_AWQOS_ISP_M1_MASK 0xf000000
|
|
#define VIP_SYS_REG_AWQOS_ISP_M1_BITS 0x4
|
|
#define VIP_SYS_REG_ARQOS_ISP_M1 0x64
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#define VIP_SYS_REG_ARQOS_ISP_M1_OFFSET 28
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#define VIP_SYS_REG_ARQOS_ISP_M1_MASK 0xf0000000
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#define VIP_SYS_REG_ARQOS_ISP_M1_BITS 0x4
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#define VIP_SYS_REG_AWQOS_OFFSET_ISP 0x68
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#define VIP_SYS_REG_AWQOS_OFFSET_ISP_OFFSET 0
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#define VIP_SYS_REG_AWQOS_OFFSET_ISP_MASK 0xf
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#define VIP_SYS_REG_AWQOS_OFFSET_ISP_BITS 0x4
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#define VIP_SYS_REG_ARQOS_OFFSET_ISP 0x68
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#define VIP_SYS_REG_ARQOS_OFFSET_ISP_OFFSET 4
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#define VIP_SYS_REG_ARQOS_OFFSET_ISP_MASK 0xf0
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#define VIP_SYS_REG_ARQOS_OFFSET_ISP_BITS 0x4
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#define VIP_SYS_REG_AWQOS_OFFSET_SC 0x68
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#define VIP_SYS_REG_AWQOS_OFFSET_SC_OFFSET 8
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#define VIP_SYS_REG_AWQOS_OFFSET_SC_MASK 0xf00
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#define VIP_SYS_REG_AWQOS_OFFSET_SC_BITS 0x4
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#define VIP_SYS_REG_ARQOS_OFFSET_SC 0x68
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#define VIP_SYS_REG_ARQOS_OFFSET_SC_OFFSET 12
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#define VIP_SYS_REG_ARQOS_OFFSET_SC_MASK 0xf000
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#define VIP_SYS_REG_ARQOS_OFFSET_SC_BITS 0x4
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#define VIP_SYS_REG_AWQOS_OFFSET_SC_M1 0x68
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#define VIP_SYS_REG_AWQOS_OFFSET_SC_M1_OFFSET 16
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#define VIP_SYS_REG_AWQOS_OFFSET_SC_M1_MASK 0xf0000
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#define VIP_SYS_REG_AWQOS_OFFSET_SC_M1_BITS 0x4
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#define VIP_SYS_REG_ARQOS_OFFSET_SC_M1 0x68
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#define VIP_SYS_REG_ARQOS_OFFSET_SC_M1_OFFSET 20
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#define VIP_SYS_REG_ARQOS_OFFSET_SC_M1_MASK 0xf00000
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#define VIP_SYS_REG_ARQOS_OFFSET_SC_M1_BITS 0x4
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#define VIP_SYS_REG_AWQOS_OFFSET_ISP_M1 0x68
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#define VIP_SYS_REG_AWQOS_OFFSET_ISP_M1_OFFSET 24
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#define VIP_SYS_REG_AWQOS_OFFSET_ISP_M1_MASK 0xf000000
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#define VIP_SYS_REG_AWQOS_OFFSET_ISP_M1_BITS 0x4
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#define VIP_SYS_REG_ARQOS_OFFSET_ISP_M1 0x68
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#define VIP_SYS_REG_ARQOS_OFFSET_ISP_M1_OFFSET 28
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#define VIP_SYS_REG_ARQOS_OFFSET_ISP_M1_MASK 0xf0000000
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#define VIP_SYS_REG_ARQOS_OFFSET_ISP_M1_BITS 0x4
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#define VIP_SYS_REG_AWQOS_THRD_ISP 0x6c
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#define VIP_SYS_REG_AWQOS_THRD_ISP_OFFSET 0
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#define VIP_SYS_REG_AWQOS_THRD_ISP_MASK 0xf
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#define VIP_SYS_REG_AWQOS_THRD_ISP_BITS 0x4
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#define VIP_SYS_REG_ARQOS_THRD_ISP 0x6c
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#define VIP_SYS_REG_ARQOS_THRD_ISP_OFFSET 4
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#define VIP_SYS_REG_ARQOS_THRD_ISP_MASK 0xf0
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#define VIP_SYS_REG_ARQOS_THRD_ISP_BITS 0x4
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#define VIP_SYS_REG_AWQOS_THRD_SC 0x6c
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#define VIP_SYS_REG_AWQOS_THRD_SC_OFFSET 8
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#define VIP_SYS_REG_AWQOS_THRD_SC_MASK 0xf00
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#define VIP_SYS_REG_AWQOS_THRD_SC_BITS 0x4
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#define VIP_SYS_REG_ARQOS_THRD_SC 0x6c
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#define VIP_SYS_REG_ARQOS_THRD_SC_OFFSET 12
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#define VIP_SYS_REG_ARQOS_THRD_SC_MASK 0xf000
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#define VIP_SYS_REG_ARQOS_THRD_SC_BITS 0x4
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#define VIP_SYS_REG_AWQOS_THRD_SC_M1 0x6c
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#define VIP_SYS_REG_AWQOS_THRD_SC_M1_OFFSET 16
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#define VIP_SYS_REG_AWQOS_THRD_SC_M1_MASK 0xf0000
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#define VIP_SYS_REG_AWQOS_THRD_SC_M1_BITS 0x4
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#define VIP_SYS_REG_ARQOS_THRD_SC_M1 0x6c
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#define VIP_SYS_REG_ARQOS_THRD_SC_M1_OFFSET 20
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#define VIP_SYS_REG_ARQOS_THRD_SC_M1_MASK 0xf00000
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#define VIP_SYS_REG_ARQOS_THRD_SC_M1_BITS 0x4
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#define VIP_SYS_REG_AWQOS_THRD_ISP_M1 0x6c
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#define VIP_SYS_REG_AWQOS_THRD_ISP_M1_OFFSET 24
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#define VIP_SYS_REG_AWQOS_THRD_ISP_M1_MASK 0xf000000
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#define VIP_SYS_REG_AWQOS_THRD_ISP_M1_BITS 0x4
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#define VIP_SYS_REG_ARQOS_THRD_ISP_M1 0x6c
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#define VIP_SYS_REG_ARQOS_THRD_ISP_M1_OFFSET 28
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#define VIP_SYS_REG_ARQOS_THRD_ISP_M1_MASK 0xf0000000
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#define VIP_SYS_REG_ARQOS_THRD_ISP_M1_BITS 0x4
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#define VIP_SYS_REG_PRIORITY_OW_RT_M1 0x70
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#define VIP_SYS_REG_PRIORITY_OW_RT_M1_OFFSET 0
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#define VIP_SYS_REG_PRIORITY_OW_RT_M1_MASK 0x1
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#define VIP_SYS_REG_PRIORITY_OW_RT_M1_BITS 0x1
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#define VIP_SYS_REG_PRIORITY_OW_RT_M2 0x70
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#define VIP_SYS_REG_PRIORITY_OW_RT_M2_OFFSET 1
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#define VIP_SYS_REG_PRIORITY_OW_RT_M2_MASK 0x2
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#define VIP_SYS_REG_PRIORITY_OW_RT_M2_BITS 0x1
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#define VIP_SYS_REG_PRIORITY_OW_RT_M3 0x70
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#define VIP_SYS_REG_PRIORITY_OW_RT_M3_OFFSET 2
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#define VIP_SYS_REG_PRIORITY_OW_RT_M3_MASK 0x4
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#define VIP_SYS_REG_PRIORITY_OW_RT_M3_BITS 0x1
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#define VIP_SYS_REG_PRIORITY_OW_RT_M4 0x70
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#define VIP_SYS_REG_PRIORITY_OW_RT_M4_OFFSET 3
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#define VIP_SYS_REG_PRIORITY_OW_RT_M4_MASK 0x8
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#define VIP_SYS_REG_PRIORITY_OW_RT_M4_BITS 0x1
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M1 0x70
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M1_OFFSET 8
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M1_MASK 0x300
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M1_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M2 0x70
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M2_OFFSET 10
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M2_MASK 0xc00
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M2_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M3 0x70
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M3_OFFSET 12
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M3_MASK 0x3000
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M3_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M4 0x70
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M4_OFFSET 14
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M4_MASK 0xc000
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#define VIP_SYS_REG_PRIORITY_MODE_RT_M4_BITS 0x2
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M1 0x70
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M1_OFFSET 16
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M1_MASK 0x30000
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M1_BITS 0x2
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M2 0x70
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M2_OFFSET 20
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M2_MASK 0x300000
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M2_BITS 0x2
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M3 0x70
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M3_OFFSET 24
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M3_MASK 0x3000000
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M3_BITS 0x2
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M4 0x70
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M4_OFFSET 28
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M4_MASK 0x30000000
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#define VIP_SYS_REG_FIX_PRIORITY_RT_M4_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_0 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_0_OFFSET 0
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_0_MASK 0x3
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_0_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_1 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_1_OFFSET 2
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_1_MASK 0xc
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_1_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_2 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_2_OFFSET 4
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_2_MASK 0x30
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_2_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_3 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_3_OFFSET 6
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_3_MASK 0xc0
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#define VIP_SYS_REG_PRIORITY_RT_M1_SEL_3_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_0 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_0_OFFSET 8
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_0_MASK 0x300
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_0_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_1 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_1_OFFSET 10
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_1_MASK 0xc00
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_1_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_2 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_2_OFFSET 12
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_2_MASK 0x3000
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_2_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_3 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_3_OFFSET 14
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_3_MASK 0xc000
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#define VIP_SYS_REG_PRIORITY_RT_M2_SEL_3_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_0 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_0_OFFSET 16
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_0_MASK 0x30000
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_0_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_1 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_1_OFFSET 18
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_1_MASK 0xc0000
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_1_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_2 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_2_OFFSET 20
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_2_MASK 0x300000
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_2_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_3 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_3_OFFSET 22
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_3_MASK 0xc00000
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#define VIP_SYS_REG_PRIORITY_RT_M3_SEL_3_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_0 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_0_OFFSET 24
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_0_MASK 0x3000000
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_0_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_1 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_1_OFFSET 26
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_1_MASK 0xc000000
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_1_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_2 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_2_OFFSET 28
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_2_MASK 0x30000000
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_2_BITS 0x2
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_3 0x74
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_3_OFFSET 30
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_3_MASK 0xc0000000
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#define VIP_SYS_REG_PRIORITY_RT_M4_SEL_3_BITS 0x2
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#define VIP_SYS_REG_AWQOS_LOW_THRD_ISP 0x7c
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#define VIP_SYS_REG_AWQOS_LOW_THRD_ISP_OFFSET 0
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#define VIP_SYS_REG_AWQOS_LOW_THRD_ISP_MASK 0xf
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#define VIP_SYS_REG_AWQOS_LOW_THRD_ISP_BITS 0x4
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#define VIP_SYS_REG_ARQOS_LOW_THRD_ISP 0x7c
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#define VIP_SYS_REG_ARQOS_LOW_THRD_ISP_OFFSET 4
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#define VIP_SYS_REG_ARQOS_LOW_THRD_ISP_MASK 0xf0
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#define VIP_SYS_REG_ARQOS_LOW_THRD_ISP_BITS 0x4
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#define VIP_SYS_REG_AWQOS_LOW_THRD_SC 0x7c
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#define VIP_SYS_REG_AWQOS_LOW_THRD_SC_OFFSET 8
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#define VIP_SYS_REG_AWQOS_LOW_THRD_SC_MASK 0xf00
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#define VIP_SYS_REG_AWQOS_LOW_THRD_SC_BITS 0x4
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#define VIP_SYS_REG_ARQOS_LOW_THRD_SC 0x7c
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#define VIP_SYS_REG_ARQOS_LOW_THRD_SC_OFFSET 12
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#define VIP_SYS_REG_ARQOS_LOW_THRD_SC_MASK 0xf000
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#define VIP_SYS_REG_ARQOS_LOW_THRD_SC_BITS 0x4
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#define VIP_SYS_REG_AWQOS_LOW_THRD_SC_M1 0x7c
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#define VIP_SYS_REG_AWQOS_LOW_THRD_SC_M1_OFFSET 16
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#define VIP_SYS_REG_AWQOS_LOW_THRD_SC_M1_MASK 0xf0000
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#define VIP_SYS_REG_AWQOS_LOW_THRD_SC_M1_BITS 0x4
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#define VIP_SYS_REG_ARQOS_LOW_THRD_SC_M1 0x7c
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#define VIP_SYS_REG_ARQOS_LOW_THRD_SC_M1_OFFSET 20
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#define VIP_SYS_REG_ARQOS_LOW_THRD_SC_M1_MASK 0xf00000
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#define VIP_SYS_REG_ARQOS_LOW_THRD_SC_M1_BITS 0x4
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#define VIP_SYS_REG_AWQOS_LOW_THRD_ISP_M1 0x7c
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#define VIP_SYS_REG_AWQOS_LOW_THRD_ISP_M1_OFFSET 24
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#define VIP_SYS_REG_AWQOS_LOW_THRD_ISP_M1_MASK 0xf000000
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#define VIP_SYS_REG_AWQOS_LOW_THRD_ISP_M1_BITS 0x4
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#define VIP_SYS_REG_ARQOS_LOW_THRD_ISP_M1 0x7c
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#define VIP_SYS_REG_ARQOS_LOW_THRD_ISP_M1_OFFSET 28
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#define VIP_SYS_REG_ARQOS_LOW_THRD_ISP_M1_MASK 0xf0000000
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#define VIP_SYS_REG_ARQOS_LOW_THRD_ISP_M1_BITS 0x4
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#define VIP_SYS_REG_DUMMY0 0x80
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#define VIP_SYS_REG_DUMMY0_OFFSET 0
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#define VIP_SYS_REG_DUMMY0_MASK 0xffffffff
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#define VIP_SYS_REG_DUMMY0_BITS 0x20
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#define VIP_SYS_REG_DUMMY1 0x84
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#define VIP_SYS_REG_DUMMY1_OFFSET 0
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#define VIP_SYS_REG_DUMMY1_MASK 0xffffffff
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#define VIP_SYS_REG_DUMMY1_BITS 0x20
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#define VIP_SYS_REG_DUMMY2 0x88
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#define VIP_SYS_REG_DUMMY2_OFFSET 0
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#define VIP_SYS_REG_DUMMY2_MASK 0xffffffff
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#define VIP_SYS_REG_DUMMY2_BITS 0x20
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#define VIP_SYS_REG_DUMMY3 0x8c
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#define VIP_SYS_REG_DUMMY3_OFFSET 0
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#define VIP_SYS_REG_DUMMY3_MASK 0xffffffff
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#define VIP_SYS_REG_DUMMY3_BITS 0x20
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#define VIP_SYS_REG_DBG_BUS0 0x90
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#define VIP_SYS_REG_DBG_BUS0_OFFSET 0
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#define VIP_SYS_REG_DBG_BUS0_MASK 0xffffffff
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#define VIP_SYS_REG_DBG_BUS0_BITS 0x20
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#define VIP_SYS_REG_DBG_BUS1 0x94
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#define VIP_SYS_REG_DBG_BUS1_OFFSET 0
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#define VIP_SYS_REG_DBG_BUS1_MASK 0xffffffff
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#define VIP_SYS_REG_DBG_BUS1_BITS 0x20
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#define VIP_SYS_REG_DBG_BUS2 0x98
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#define VIP_SYS_REG_DBG_BUS2_OFFSET 0
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#define VIP_SYS_REG_DBG_BUS2_MASK 0xffffffff
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#define VIP_SYS_REG_DBG_BUS2_BITS 0x20
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#define VIP_SYS_REG_DBG_BUS3 0x9c
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#define VIP_SYS_REG_DBG_BUS3_OFFSET 0
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#define VIP_SYS_REG_DBG_BUS3_MASK 0xffffffff
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#define VIP_SYS_REG_DBG_BUS3_BITS 0x20
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#define VIP_SYS_RT_AXI_MON_M1_OUT 0xa0
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#define VIP_SYS_RT_AXI_MON_M1_OUT_OFFSET 0
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#define VIP_SYS_RT_AXI_MON_M1_OUT_MASK 0xffffffff
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#define VIP_SYS_RT_AXI_MON_M1_OUT_BITS 0x20
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#define VIP_SYS_RT_AXI_MON_M2_OUT 0xa4
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#define VIP_SYS_RT_AXI_MON_M2_OUT_OFFSET 0
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#define VIP_SYS_RT_AXI_MON_M2_OUT_MASK 0xffffffff
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#define VIP_SYS_RT_AXI_MON_M2_OUT_BITS 0x20
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#define VIP_SYS_RT_AXI_MON_M3_OUT 0xa8
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#define VIP_SYS_RT_AXI_MON_M3_OUT_OFFSET 0
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#define VIP_SYS_RT_AXI_MON_M3_OUT_MASK 0xffffffff
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#define VIP_SYS_RT_AXI_MON_M3_OUT_BITS 0x20
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#define VIP_SYS_RT_AXI_MON_M4_OUT 0xac
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#define VIP_SYS_RT_AXI_MON_M4_OUT_OFFSET 0
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#define VIP_SYS_RT_AXI_MON_M4_OUT_MASK 0xffffffff
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#define VIP_SYS_RT_AXI_MON_M4_OUT_BITS 0x20
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#define VIP_SYS_OFF_AXI_MON_M1_OUT 0xb0
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#define VIP_SYS_OFF_AXI_MON_M1_OUT_OFFSET 0
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#define VIP_SYS_OFF_AXI_MON_M1_OUT_MASK 0xffffffff
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#define VIP_SYS_OFF_AXI_MON_M1_OUT_BITS 0x20
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#define VIP_SYS_OFF_AXI_MON_M2_OUT 0xb4
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#define VIP_SYS_OFF_AXI_MON_M2_OUT_OFFSET 0
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#define VIP_SYS_OFF_AXI_MON_M2_OUT_MASK 0xffffffff
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#define VIP_SYS_OFF_AXI_MON_M2_OUT_BITS 0x20
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#define VIP_SYS_REG_RST_IVE_TOP 0xc0
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#define VIP_SYS_REG_RST_IVE_TOP_OFFSET 0
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#define VIP_SYS_REG_RST_IVE_TOP_MASK 0x1
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#define VIP_SYS_REG_RST_IVE_TOP_BITS 0x1
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#define VIP_SYS_REG_RST_ISP_RAW 0xc0
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#define VIP_SYS_REG_RST_ISP_RAW_OFFSET 1
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#define VIP_SYS_REG_RST_ISP_RAW_MASK 0x2
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#define VIP_SYS_REG_RST_ISP_RAW_BITS 0x1
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#define VIP_SYS_REG_RST_OSDC 0xc0
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#define VIP_SYS_REG_RST_OSDC_OFFSET 2
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#define VIP_SYS_REG_RST_OSDC_MASK 0x4
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#define VIP_SYS_REG_RST_OSDC_BITS 0x1
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#define VIP_SYS_REG_RST_IVE_TOP_APB 0xc0
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#define VIP_SYS_REG_RST_IVE_TOP_APB_OFFSET 8
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#define VIP_SYS_REG_RST_IVE_TOP_APB_MASK 0x100
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#define VIP_SYS_REG_RST_IVE_TOP_APB_BITS 0x1
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#define VIP_SYS_REG_NORM_DIV_EN_RAW_TOP 0xc4
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#define VIP_SYS_REG_NORM_DIV_EN_RAW_TOP_OFFSET 0
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#define VIP_SYS_REG_NORM_DIV_EN_RAW_TOP_MASK 0x1
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#define VIP_SYS_REG_NORM_DIV_EN_RAW_TOP_BITS 0x1
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#define VIP_SYS_REG_IDLE_DIV_EN_RAW_TOP 0xc4
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#define VIP_SYS_REG_IDLE_DIV_EN_RAW_TOP_OFFSET 1
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#define VIP_SYS_REG_IDLE_DIV_EN_RAW_TOP_MASK 0x2
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#define VIP_SYS_REG_IDLE_DIV_EN_RAW_TOP_BITS 0x1
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#define VIP_SYS_REG_UPDATE_SEL_RAW_TOP 0xc4
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#define VIP_SYS_REG_UPDATE_SEL_RAW_TOP_OFFSET 2
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#define VIP_SYS_REG_UPDATE_SEL_RAW_TOP_MASK 0x4
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#define VIP_SYS_REG_UPDATE_SEL_RAW_TOP_BITS 0x1
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#define VIP_SYS_REG_IDLE_SLOW_SEL_RAW_TOP 0xc4
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#define VIP_SYS_REG_IDLE_SLOW_SEL_RAW_TOP_OFFSET 8
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#define VIP_SYS_REG_IDLE_SLOW_SEL_RAW_TOP_MASK 0x700
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#define VIP_SYS_REG_IDLE_SLOW_SEL_RAW_TOP_BITS 0x3
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#define VIP_SYS_REG_IDLE_WAIT_SEL_RAW_TOP 0xc4
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#define VIP_SYS_REG_IDLE_WAIT_SEL_RAW_TOP_OFFSET 12
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#define VIP_SYS_REG_IDLE_WAIT_SEL_RAW_TOP_MASK 0x7000
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#define VIP_SYS_REG_IDLE_WAIT_SEL_RAW_TOP_BITS 0x3
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#define VIP_SYS_REG_NORM_DIV_VAL_RAW_TOP 0xc4
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#define VIP_SYS_REG_NORM_DIV_VAL_RAW_TOP_OFFSET 16
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#define VIP_SYS_REG_NORM_DIV_VAL_RAW_TOP_MASK 0x1f0000
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#define VIP_SYS_REG_NORM_DIV_VAL_RAW_TOP_BITS 0x5
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#define VIP_SYS_REG_NORM_DIV_EN_IVE_TOP 0xc8
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#define VIP_SYS_REG_NORM_DIV_EN_IVE_TOP_OFFSET 0
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#define VIP_SYS_REG_NORM_DIV_EN_IVE_TOP_MASK 0x1
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#define VIP_SYS_REG_NORM_DIV_EN_IVE_TOP_BITS 0x1
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#define VIP_SYS_REG_IDLE_DIV_EN_IVE_TOP 0xc8
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#define VIP_SYS_REG_IDLE_DIV_EN_IVE_TOP_OFFSET 1
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#define VIP_SYS_REG_IDLE_DIV_EN_IVE_TOP_MASK 0x2
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#define VIP_SYS_REG_IDLE_DIV_EN_IVE_TOP_BITS 0x1
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#define VIP_SYS_REG_UPDATE_SEL_IVE_TOP 0xc8
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#define VIP_SYS_REG_UPDATE_SEL_IVE_TOP_OFFSET 2
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#define VIP_SYS_REG_UPDATE_SEL_IVE_TOP_MASK 0x4
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#define VIP_SYS_REG_UPDATE_SEL_IVE_TOP_BITS 0x1
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#define VIP_SYS_REG_IDLE_SLOW_SEL_IVE_TOP 0xc8
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#define VIP_SYS_REG_IDLE_SLOW_SEL_IVE_TOP_OFFSET 8
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#define VIP_SYS_REG_IDLE_SLOW_SEL_IVE_TOP_MASK 0x700
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#define VIP_SYS_REG_IDLE_SLOW_SEL_IVE_TOP_BITS 0x3
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#define VIP_SYS_REG_IDLE_WAIT_SEL_IVE_TOP 0xc8
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#define VIP_SYS_REG_IDLE_WAIT_SEL_IVE_TOP_OFFSET 12
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#define VIP_SYS_REG_IDLE_WAIT_SEL_IVE_TOP_MASK 0x7000
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#define VIP_SYS_REG_IDLE_WAIT_SEL_IVE_TOP_BITS 0x3
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#define VIP_SYS_REG_NORM_DIV_VAL_IVE_TOP 0xc8
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#define VIP_SYS_REG_NORM_DIV_VAL_IVE_TOP_OFFSET 16
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#define VIP_SYS_REG_NORM_DIV_VAL_IVE_TOP_MASK 0x1f0000
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#define VIP_SYS_REG_NORM_DIV_VAL_IVE_TOP_BITS 0x5
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#define VIP_SYS_REG_NORM_DIV_EN_CAM0 0xcc
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#define VIP_SYS_REG_NORM_DIV_EN_CAM0_OFFSET 0
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#define VIP_SYS_REG_NORM_DIV_EN_CAM0_MASK 0x1
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#define VIP_SYS_REG_NORM_DIV_EN_CAM0_BITS 0x1
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#define VIP_SYS_REG_IDLE_DIV_EN_CAM0 0xcc
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#define VIP_SYS_REG_IDLE_DIV_EN_CAM0_OFFSET 1
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#define VIP_SYS_REG_IDLE_DIV_EN_CAM0_MASK 0x2
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#define VIP_SYS_REG_IDLE_DIV_EN_CAM0_BITS 0x1
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#define VIP_SYS_REG_UPDATE_SEL_CAM0 0xcc
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#define VIP_SYS_REG_UPDATE_SEL_CAM0_OFFSET 2
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#define VIP_SYS_REG_UPDATE_SEL_CAM0_MASK 0x4
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#define VIP_SYS_REG_UPDATE_SEL_CAM0_BITS 0x1
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CAM0 0xcc
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CAM0_OFFSET 8
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CAM0_MASK 0x700
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#define VIP_SYS_REG_IDLE_SLOW_SEL_CAM0_BITS 0x3
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CAM0 0xcc
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CAM0_OFFSET 12
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CAM0_MASK 0x7000
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#define VIP_SYS_REG_IDLE_WAIT_SEL_CAM0_BITS 0x3
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#define VIP_SYS_REG_NORM_DIV_VAL_CAM0 0xcc
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#define VIP_SYS_REG_NORM_DIV_VAL_CAM0_OFFSET 16
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#define VIP_SYS_REG_NORM_DIV_VAL_CAM0_MASK 0x1f0000
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#define VIP_SYS_REG_NORM_DIV_VAL_CAM0_BITS 0x5
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#define VIP_SYS_OFF_AXI_MON_M3_OUT 0xd0
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#define VIP_SYS_OFF_AXI_MON_M3_OUT_OFFSET 0
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#define VIP_SYS_OFF_AXI_MON_M3_OUT_MASK 0xffffffff
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#define VIP_SYS_OFF_AXI_MON_M3_OUT_BITS 0x20
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#define VIP_SYS_OFF_AXI_MON_M4_OUT 0xd4
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#define VIP_SYS_OFF_AXI_MON_M4_OUT_OFFSET 0
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#define VIP_SYS_OFF_AXI_MON_M4_OUT_MASK 0xffffffff
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#define VIP_SYS_OFF_AXI_MON_M4_OUT_BITS 0x20
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#define VIP_SYS_OFF_AXI_MON_M5_OUT 0xd8
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#define VIP_SYS_OFF_AXI_MON_M5_OUT_OFFSET 0
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#define VIP_SYS_OFF_AXI_MON_M5_OUT_MASK 0xffffffff
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#define VIP_SYS_OFF_AXI_MON_M5_OUT_BITS 0x20
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#define VIP_SYS_OFF_AXI_MON_M6_OUT 0xdc
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#define VIP_SYS_OFF_AXI_MON_M6_OUT_OFFSET 0
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#define VIP_SYS_OFF_AXI_MON_M6_OUT_MASK 0xffffffff
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#define VIP_SYS_OFF_AXI_MON_M6_OUT_BITS 0x20
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#define VIP_SYS_OFF_AXI_MON_M7_OUT 0xe0
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#define VIP_SYS_OFF_AXI_MON_M7_OUT_OFFSET 0
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#define VIP_SYS_OFF_AXI_MON_M7_OUT_MASK 0xffffffff
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#define VIP_SYS_OFF_AXI_MON_M7_OUT_BITS 0x20
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