5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
85 lines
1.2 KiB
Plaintext
85 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for MediaTek X20 Development Board
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*
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* Copyright (C) 2018, Linaro Ltd.
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*
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*/
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/dts-v1/;
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#include "mt6797.dtsi"
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/ {
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model = "Mediatek X20 Development Board";
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compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
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aliases {
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serial0 = &uart1;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x80000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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/* HDMI */
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins_a>;
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status = "okay";
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};
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/* HS - I2C2 */
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins_a>;
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status = "okay";
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};
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/* HS - I2C3 */
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins_a>;
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status = "okay";
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};
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/* LS - I2C0 */
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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status = "okay";
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};
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/* LS - I2C1 */
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&i2c5 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins_a>;
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status = "okay";
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};
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/* POWER_VPROC */
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&i2c6 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_pins_a>;
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status = "okay";
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};
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/* FAN53555 */
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&i2c7 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7_pins_a>;
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status = "okay";
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins_a>;
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};
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