3a4bcfca2f
1. add cvitek folders to u-boot-2021.10 2. add cv183x/cv182x part 3. add cv181x/cv180x part Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
94 lines
1.7 KiB
C
94 lines
1.7 KiB
C
/*
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* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
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*
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*/
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#ifndef _CVI_I80_H_
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#define _CVI_I80_H_
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#include "cvi_mipi.h"
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#define COMMAND 0
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#define DATA 1
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enum _PIXEL_FORMAT_E {
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PIXEL_FORMAT_RGB_888 = 0,
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PIXEL_FORMAT_BGR_888,
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PIXEL_FORMAT_RGB_888_PLANAR,
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};
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enum _VO_I80_FORMAT {
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VO_I80_FORMAT_RGB444 = 0,
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VO_I80_FORMAT_RGB565,
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VO_I80_FORMAT_RGB666,
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VO_I80_FORMAT_MAX
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};
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enum i80_op_type {
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I80_OP_GO = 0,
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I80_OP_TIMER,
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I80_OP_DONE,
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I80_OP_MAX,
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};
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enum i80_ctrl_type {
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I80_CTRL_CMD = 0,
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I80_CTRL_DATA,
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I80_CTRL_EOL = I80_CTRL_DATA,
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I80_CTRL_EOF,
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I80_CTRL_END = I80_CTRL_EOF,
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I80_CTRL_MAX
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};
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/* Define I80's lane (0~3)
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*
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* CS: Chip Select
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* RS(DCX): Data/Command
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* WR: MCU Write to bus
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* RD: MCU Read from bus
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*/
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struct _VO_I80_LANE_S {
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unsigned char CS;
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unsigned char RS;
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unsigned char WR;
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unsigned char RD;
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};
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/* Define I80's config
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*
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* lane_s: lane mapping
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* fmt: format of data
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* cycle_time: cycle time of WR/RD, unit ns, max 250
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*/
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struct _VO_I80_CFG_S {
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struct _VO_I80_LANE_S lane_s;
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enum _VO_I80_FORMAT fmt;
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unsigned short cycle_time;
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struct sync_info_s sync_info;
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};
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/* Define I80's cmd
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*
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* delay: ms to delay after instr
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* data_type: Data(1)/Command(0)
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* data: data to send
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*/
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struct _VO_I80_INSTR_S {
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unsigned char delay;
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unsigned char data_type;
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unsigned char data;
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};
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extern unsigned char i80_ctrl[I80_CTRL_MAX];
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void i80_package_frame(unsigned char *in, unsigned char *out, unsigned int stride, unsigned char byte_cnt,
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unsigned short w, unsigned short h);
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int i80_set_combo_dev_cfg(const struct _VO_I80_CFG_S *i80_cfg);
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void i80_set_sw_mode(unsigned long mode_flags);
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int i80_set_cmd(unsigned int cmd);
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int i80_set_run(void);
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void i80_sclr_intr_clr(void);
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#endif // _CVI_I80_H_
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