3a4bcfca2f
1. add cvitek folders to u-boot-2021.10 2. add cv183x/cv182x part 3. add cv181x/cv180x part Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
26 lines
748 B
C
26 lines
748 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2017 Andes Technology Corporation
|
|
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
|
*/
|
|
|
|
#ifndef _ASM_RISCV_CACHE_H
|
|
#define _ASM_RISCV_CACHE_H
|
|
|
|
/* cache */
|
|
void cache_flush(void);
|
|
void invalidate_dcache_range(unsigned long start, unsigned long end);
|
|
void flush_dcache_range(unsigned long start, unsigned long end);
|
|
/*
|
|
* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
|
|
* We use that value for aligning DMA buffers unless the board config has
|
|
* specified an alternate cache line size.
|
|
*/
|
|
#ifdef CONFIG_SYS_CACHELINE_SIZE
|
|
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
|
#else
|
|
#define ARCH_DMA_MINALIGN 32
|
|
#endif
|
|
|
|
#endif /* _ASM_RISCV_CACHE_H */
|