5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
23 lines
740 B
Plaintext
23 lines
740 B
Plaintext
ZTE ZX PWM controller
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Required properties:
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- compatible: Should be "zte,zx296718-pwm".
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- reg: Physical base address and length of the controller's registers.
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- clocks : The phandle and specifier referencing the controller's clocks.
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- clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The
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PCLK is for register access, while WCLK is the reference clock for
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calculating period and duty cycles.
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- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
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the cells format.
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Example:
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pwm: pwm@1439000 {
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compatible = "zte,zx296718-pwm";
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reg = <0x1439000 0x1000>;
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clocks = <&lsp1crm LSP1_PWM_PCLK>,
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<&lsp1crm LSP1_PWM_WCLK>;
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clock-names = "pclk", "wclk";
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#pwm-cells = <3>;
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};
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