4f810186ab
1. update cv182x/cv183x configuration file 2. update cv181x/cv180x configuration file 3. update clk driver for cvitek 4. update dma driver for cvitek 5. update soc driver for cvitek 6. porting cvitek ion driver from kernel-4.19 7. compatible with riscv Change-Id: Icff9fafe0ebe7d6bab824bbadb952e08bdc66c19
78 lines
1.9 KiB
C
78 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef _CV1835_I2S_SUBSYS_H_
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#define _CV1835_I2S_SUBSYS_H_
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#define SUBSYS_I2S0 (0x1 << 0)
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#define SUBSYS_I2S1 (0x1 << 1)
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#define SUBSYS_I2S2 (0x1 << 2)
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#define SUBSYS_I2S3 (0x1 << 3)
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#define SCLK_IN_SEL 0x00
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#define FS_IN_SEL 0x04
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#define SDI_IN_SEL 0x08
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#define SDO_OUT_SEL 0x0C
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#define MULTI_SYNC 0x20
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#define BCLK_OEN_SEL 0x30
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#define BCLK_OUT_CTRL 0x34
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#define AUDIO_PDM_CTRL 0x40
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#define AUDIO_PHY_BYPASS1 0x50
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#define AUDIO_PHY_BYPASS2 0x54
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#define SYS_CLK_CTRL 0x70
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#define I2S0_MASTER_CLK_CTRL0 0x80
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#define I2S0_MASTER_CLK_CTRL1 0x84
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#define I2S1_MASTER_CLK_CTRL0 0x90
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#define I2S1_MASTER_CLK_CTRL1 0x94
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#define I2S2_MASTER_CLK_CTRL0 0xA0
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#define I2S2_MASTER_CLK_CTRL1 0xA4
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#define I2S3_MASTER_CLK_CTRL0 0xB0
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#define I2S3_MASTER_CLK_CTRL1 0xB4
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#define SYS_LRCK_CTRL 0xC0
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#define I2S_FRAME_SETTING_REG 0x04
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#define I2S_ENABLE_REG 0x18
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#define I2S_LCRK_MASTER_REG 0x2C
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#define I2S_CLK_CTRL0_REG 0x60
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#define I2S_CLK_CTRL1_REG 0x64
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#define I2S_RESET_REG 0x1C
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#define I2S_TX_STATUS_REG 0x48
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#ifdef CONFIG_PM_SLEEP
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struct subsys_reg_context {
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u32 sclk_in_sel;
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u32 fs_in_sel;
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u32 sdi_in_sel;
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u32 sdo_out_sel;
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u32 multi_sync;
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u32 bclk_oen_sel;
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u32 pdm_ctrl;
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};
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#endif
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struct cvi_i2s_subsys_dev {
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void __iomem *subsys_base;
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struct device *dev;
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u32 master_id;
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u32 master_base;
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#ifdef CONFIG_PM_SLEEP
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struct subsys_reg_context *reg_ctx;
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#endif
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};
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#define CVI_16384_MHZ 16384000 /* 16.384 Mhz */
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#define CVI_22579_MHZ 22579200 /* 22.5792 Mhz */
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#define CVI_24576_MHZ 24576000 /* 24.576 Mhz */
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u32 i2s_subsys_query_master(void);
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void i2s_master_clk_switch_on(bool on);
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void i2s_set_master_clk(u32 clk_ctrl1);
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void i2s_set_master_frame_setting(u32 frame_format);
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void cv1835_set_mclk(u32 freq);
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void cv182x_reset_dac(void);
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void cv182x_reset_adc(void);
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void cv182xa_reset_dac(void);
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void cv182xa_reset_adc(void);
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#endif
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