4f810186ab
1. update cv182x/cv183x configuration file 2. update cv181x/cv180x configuration file 3. update clk driver for cvitek 4. update dma driver for cvitek 5. update soc driver for cvitek 6. porting cvitek ion driver from kernel-4.19 7. compatible with riscv Change-Id: Icff9fafe0ebe7d6bab824bbadb952e08bdc66c19
189 lines
5.1 KiB
C
189 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/* Driver for CVITEK PHYs */
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#include <linux/bitops.h>
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#define CVI_ETH_PHY_ADC_CTRL 16
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#define CVI_ETH_PHY_INT_STS 16
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#define CVI_ETH_AUTO_CALIBRATE 16
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#define CVI_ETH_PHY_INT_MASK 17
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#define CVI_ETH_PHY_APS 18
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#define CVI_ETH_PHY_UAPS 19
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#define CVI_ETH_PHY_LB_CTL 18
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#define CVI_ETH_PHY_AFE_TX 20
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#define CVI_ETH_PHY_AFE_DRV2 21
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#define CVI_ETH_PHY_CP 23
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#define CVI_ETH_PHY_ADC_OP_BIAS 24
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#define CVI_ETH_PHY_STATUS 25
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#define CVI_ETH_PHY_RX_SIGNAL 25
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#define CVI_ETH_PHY_2_MISC 28
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#define CVI_ETH_PHY_TXDATA_CTRL 24
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#define CVI_ETH_PHY_PAGE_SEL 31
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#define CVI_ETH_PHY_PAGE_0 0x0000
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#define CVI_ETH_PHY_PAGE_1 0x0100
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#define CVI_ETH_PHY_PAGE_2 0x0200
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#define CVI_ETH_PHY_PAGE_3 0x0300
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#define CVI_ETH_PHY_PAGE_6 0x0600
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#define CVI_ETH_PHY_PAGE_8 0x0800
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#define CVI_ETH_PHY_PAGE_9 0x0900
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#define CVI_ETH_PHY_LOOPBACK
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#define LOOPBACK_XMII2MAC 0x8000
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#define LOOPBACK_PCS2MAC 0x2000
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#define LOOPBACK_PMA2MAC 0x1000
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#define LOOPBACK_RMII2PHY 0x0080
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#define CVI_LNK_STS_CHG_INT_MSK BIT(15)
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#define CVI_MGC_PKT_DET_INT_MSK BIT(14)
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#define CVI_TX_LPI_RCV_INT_MSK BIT(13)
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#define CVI_RX_LPI_RCV_INT_MSK BIT(12)
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#define CVI_UAPS_ENABLE BIT(15)
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#define CVI_CKSELIN BIT(13)
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#define CVI_INT_EVENTS \
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(CVI_LNK_STS_CHG_INT_MSK | CVI_MGC_PKT_DET_INT_MSK)
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static int cvi_phy_config_intr(struct phy_device *phydev)
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{
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int rc = phy_write(phydev, CVI_ETH_PHY_INT_MASK,
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((phydev->interrupts == PHY_INTERRUPT_ENABLED)
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? CVI_INT_EVENTS
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: 0));
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return rc < 0 ? rc : 0;
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}
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static int cvi_phy_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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pr_debug("%s, clear interrupts\n", __func__);
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err = phy_write(phydev, CVI_ETH_PHY_INT_STS, 0xf000);
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return err < 0 ? err : 0;
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}
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static int cvi_read_status(struct phy_device *phydev)
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{
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int err = genphy_read_status(phydev);
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pr_debug("%s, speed=%d, duplex=%d, ", __func__, phydev->speed, phydev->duplex);
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pr_debug("pasue=%d, asym_pause=%d, autoneg=%d ", phydev->pause, phydev->asym_pause, phydev->autoneg);
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pr_debug("cvi_Status=0x%04x\n", phy_read(phydev, CVI_ETH_PHY_STATUS));
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return err;
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}
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#if defined(CONFIG_CVITEK_PHY_UAPS)
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/* Ultra Auto Power Saving mode */
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static int cvi_phy_aps_enable(struct phy_device *phydev)
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{
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int val;
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pr_info("Enable CVITEK ethernet phy ultra auto power saving mode\n");
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phy_write(phydev, CVI_ETH_PHY_PAGE_SEL, CVI_ETH_PHY_PAGE_1);
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val = phy_read(phydev, CVI_ETH_PHY_UAPS);
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phy_write(phydev, CVI_ETH_PHY_UAPS, CVI_UAPS_ENABLE | val);
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phy_write(phydev, CVI_ETH_PHY_PAGE_SEL, CVI_ETH_PHY_PAGE_0);
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return 0;
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}
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#endif
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static int cvi_phy_config_aneg(struct phy_device *phydev)
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{
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int ret;
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/* switch to page 1 */
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phy_write(phydev, CVI_ETH_PHY_PAGE_SEL, CVI_ETH_PHY_PAGE_1);
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/* Disable APS */
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phy_write(phydev, CVI_ETH_PHY_APS, 0x4824);
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/* switch to page 2 */
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phy_write(phydev, CVI_ETH_PHY_PAGE_SEL, CVI_ETH_PHY_PAGE_2);
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/* PHYAFE TRX optimization */
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phy_write(phydev, CVI_ETH_PHY_TXDATA_CTRL, 0x0000);
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/* switch to page 6 */
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phy_write(phydev, CVI_ETH_PHY_PAGE_SEL, CVI_ETH_PHY_PAGE_6);
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/* PHYAFE ADC optimization */
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phy_write(phydev, CVI_ETH_PHY_ADC_CTRL, 0x555b);
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/* PHYAFE TX optimization */
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phy_write(phydev, CVI_ETH_PHY_AFE_TX, 0x508f);
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/* enable a_CLKSELIN to avoid CRC error and increase 10M/100M amplitude*/
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phy_write(phydev, CVI_ETH_PHY_AFE_DRV2, 0x3030);
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/* PHYAFE CP current optimization */
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phy_write(phydev, CVI_ETH_PHY_CP, 0x0575);
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/* PHYAFE ADC OP BIAS optimization */
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phy_write(phydev, CVI_ETH_PHY_ADC_OP_BIAS, 0x0000);
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/* PHYAFE RX signal detector level optimization */
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phy_write(phydev, CVI_ETH_PHY_RX_SIGNAL, 0x0408);
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/* Enable PD control optimization */
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phy_write(phydev, CVI_ETH_PHY_2_MISC, 0x8880);
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/* switch to page 8 */
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phy_write(phydev, CVI_ETH_PHY_PAGE_SEL, CVI_ETH_PHY_PAGE_8);
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/* Stop auto-calibrate */
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phy_write(phydev, CVI_ETH_AUTO_CALIBRATE, 0x0844);
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#if defined(CONFIG_CVITEK_PHY_UAPS)
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cvi_phy_aps_enable(phydev); /* if phy not work, disable this function for try */
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#endif
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/* switch back to page 0 */
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phy_write(phydev, CVI_ETH_PHY_PAGE_SEL, CVI_ETH_PHY_PAGE_0);
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ret = genphy_config_aneg(phydev);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int cvi_phy_config_init(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_read_abilities(phydev);
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if (ret < 0)
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return ret;
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return 0;
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}
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static struct phy_driver cvitek_phy_driver[] = {
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{
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.phy_id = 0x00441400,
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.phy_id_mask = 0xfffffff0,
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.name = "CVITEK CVI18XX",
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.get_features = genphy_read_abilities,
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.read_status = cvi_read_status,
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/* IRQ related */
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.ack_interrupt = cvi_phy_ack_interrupt,
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.config_intr = cvi_phy_config_intr,
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.aneg_done = genphy_aneg_done,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.set_loopback = genphy_loopback,
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} };
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module_phy_driver(cvitek_phy_driver);
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MODULE_DESCRIPTION("CVITEK PHY driver");
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MODULE_AUTHOR("Ethan Chen");
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MODULE_LICENSE("GPL");
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static struct mdio_device_id __maybe_unused cvitek_tbl[] = {
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{ 0x00441400, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, cvitek_tbl);
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