5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
49 lines
1.7 KiB
C
49 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_BARRIER_H
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#define __ASM_CSKY_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() asm volatile ("nop\n":::"memory")
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/*
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* sync: completion barrier, all sync.xx instructions
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* guarantee the last response recieved by bus transaction
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* made by ld/st instructions before sync.s
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* sync.s: inherit from sync, but also shareable to other cores
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* sync.i: inherit from sync, but also flush cpu pipeline
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* sync.is: the same with sync.i + sync.s
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*
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* bar.brwarw: ordering barrier for all load/store instructions before it
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* bar.brwarws: ordering barrier for all load/store instructions before it
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* and shareable to other cores
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* bar.brar: ordering barrier for all load instructions before it
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* bar.brars: ordering barrier for all load instructions before it
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* and shareable to other cores
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* bar.bwaw: ordering barrier for all store instructions before it
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* bar.bwaws: ordering barrier for all store instructions before it
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* and shareable to other cores
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*/
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#ifdef CONFIG_CPU_HAS_CACHEV2
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#define mb() asm volatile ("sync.s\n":::"memory")
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#ifdef CONFIG_SMP
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#define __smp_mb() asm volatile ("bar.brwarws\n":::"memory")
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#define __smp_rmb() asm volatile ("bar.brars\n":::"memory")
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#define __smp_wmb() asm volatile ("bar.bwaws\n":::"memory")
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#endif /* CONFIG_SMP */
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#define sync_is() asm volatile ("sync.is\n":::"memory")
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#else /* !CONFIG_CPU_HAS_CACHEV2 */
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#define mb() asm volatile ("sync\n":::"memory")
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#endif
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#include <asm-generic/barrier.h>
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_CSKY_BARRIER_H */
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