5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
33 lines
1.0 KiB
C
33 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARM_SWITCH_TO_H
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#define __ASM_ARM_SWITCH_TO_H
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#include <linux/thread_info.h>
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/*
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* For v7 SMP cores running a preemptible kernel we may be pre-empted
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* during a TLB maintenance operation, so execute an inner-shareable dsb
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* to ensure that the maintenance completes in case we migrate to another
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* CPU.
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*/
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#if defined(CONFIG_PREEMPTION) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
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#define __complete_pending_tlbi() dsb(ish)
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#else
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#define __complete_pending_tlbi()
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#endif
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'. schedule() itself
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* contains the memory barrier to tell GCC not to cache `current'.
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*/
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extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
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#define switch_to(prev,next,last) \
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do { \
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__complete_pending_tlbi(); \
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last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
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} while (0)
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#endif /* __ASM_ARM_SWITCH_TO_H */
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