4f810186ab
1. update cv182x/cv183x configuration file 2. update cv181x/cv180x configuration file 3. update clk driver for cvitek 4. update dma driver for cvitek 5. update soc driver for cvitek 6. porting cvitek ion driver from kernel-4.19 7. compatible with riscv Change-Id: Icff9fafe0ebe7d6bab824bbadb952e08bdc66c19
101 lines
2.2 KiB
ArmAsm
101 lines
2.2 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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* Copyright (C) 2019 T-HEAD
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/csr.h>
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#include <asm/asm-offsets.h>
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#if (defined(CONFIG_VECTOR_1_0) && defined(__THEAD_VERSION__))
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#define V_ST vse8.v
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#define V_LD vle8.v
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#else
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#define V_ST vsb.v
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#define V_LD vlb.v
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#endif
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ENTRY(__vstate_save)
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li a2, TASK_THREAD_V0
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add a0, a0, a2
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li t1, (SR_VS | SR_FS)
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csrs sstatus, t1
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csrr t0, CSR_VSTART
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sd t0, TASK_THREAD_VSTART_V0(a0)
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csrr t0, CSR_VXSAT
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sd t0, TASK_THREAD_VXSAT_V0(a0)
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csrr t0, CSR_VXRM
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sd t0, TASK_THREAD_VXRM_V0(a0)
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csrr t0, CSR_VL
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sd t0, TASK_THREAD_VL_V0(a0)
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csrr t0, CSR_VTYPE
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sd t0, TASK_THREAD_VTYPE_V0(a0)
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vsetvli t0, x0, e8,m8
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V_ST v0, (a0)
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addi a0, a0, RISCV_VECTOR_VLENB*8
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V_ST v8, (a0)
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addi a0, a0, RISCV_VECTOR_VLENB*8
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V_ST v16, (a0)
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addi a0, a0, RISCV_VECTOR_VLENB*8
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V_ST v24, (a0)
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csrc sstatus, t1
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ret
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ENDPROC(__vstate_save)
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ENTRY(__vstate_restore)
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li a2, TASK_THREAD_V0
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add a0, a0, a2
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mv t2, a0
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li t1, (SR_VS | SR_FS)
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csrs sstatus, t1
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vsetvli t0, x0, e8,m8
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V_LD v0, (a0)
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addi a0, a0, RISCV_VECTOR_VLENB*8
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V_LD v8, (a0)
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addi a0, a0, RISCV_VECTOR_VLENB*8
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V_LD v16, (a0)
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addi a0, a0, RISCV_VECTOR_VLENB*8
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V_LD v24, (a0)
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mv a0, t2
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ld t0, TASK_THREAD_VSTART_V0(a0)
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csrw CSR_VSTART, t0
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ld t0, TASK_THREAD_VXSAT_V0(a0)
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csrw CSR_VXSAT, t0
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ld t0, TASK_THREAD_VXRM_V0(a0)
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csrw CSR_VXRM, t0
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ld t0, TASK_THREAD_VL_V0(a0)
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ld t2, TASK_THREAD_VTYPE_V0(a0)
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#ifdef CONFIG_VECTOR_EMU
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srli t3, t2, 63
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bne t3,zero,1f
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#endif
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vsetvl t3, t0, t2
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#ifdef CONFIG_VECTOR_EMU
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j 2f
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1: vsetvli zero,zero,e64,m2,d1
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2:
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#endif
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csrc sstatus, t1
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ret
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ENDPROC(__vstate_restore)
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