f8fc109960
repo: https://github.com/u-boot/u-boot commit: d80bb749fab53da72c4a0e09b8c2d2aaa3103c91 Change-Id: Ie6434426e1ec15bc08bb1832798e371f3fd5fb29
29 lines
871 B
C
29 lines
871 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2015-2016, NVIDIA CORPORATION.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
|
|
#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
|
|
|
|
#define TEGRA186_POWER_DOMAIN_AUD 0
|
|
#define TEGRA186_POWER_DOMAIN_DFD 1
|
|
#define TEGRA186_POWER_DOMAIN_DISP 2
|
|
#define TEGRA186_POWER_DOMAIN_DISPB 3
|
|
#define TEGRA186_POWER_DOMAIN_DISPC 4
|
|
#define TEGRA186_POWER_DOMAIN_ISPA 5
|
|
#define TEGRA186_POWER_DOMAIN_NVDEC 6
|
|
#define TEGRA186_POWER_DOMAIN_NVJPG 7
|
|
#define TEGRA186_POWER_DOMAIN_MPE 8
|
|
#define TEGRA186_POWER_DOMAIN_PCX 9
|
|
#define TEGRA186_POWER_DOMAIN_SAX 10
|
|
#define TEGRA186_POWER_DOMAIN_VE 11
|
|
#define TEGRA186_POWER_DOMAIN_VIC 12
|
|
#define TEGRA186_POWER_DOMAIN_XUSBA 13
|
|
#define TEGRA186_POWER_DOMAIN_XUSBB 14
|
|
#define TEGRA186_POWER_DOMAIN_XUSBC 15
|
|
#define TEGRA186_POWER_DOMAIN_GPU 43
|
|
#define TEGRA186_POWER_DOMAIN_MAX 44
|
|
|
|
#endif
|