130 lines
3.7 KiB
ArmAsm
130 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cpu.h>
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#include <aarch64/el3_common_macros.S>
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#include <debug.h>
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#include <platform.h>
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.globl bl1_entrypoint
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.globl bl1_entrypoint_end
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.globl bl1_entrypoint_rel
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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.pushsection .entry, "ax"
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bl1_entrypoint:
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# Relocate from 0x04400000 to mirrored ROM address 0x40000000
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ldr x0, =bl1_entrypoint_rel
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br x0
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bl1_entrypoint_end:
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.popsection
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func bl1_entrypoint_rel
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atf_state_set w14, x15, ATF_STATE_BL1_ENTRY_POINT
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atf_err_set w14, x15, ATF_ERR_NONE
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/*
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* Initialise the register file as a safeguard against
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* spurious X propagation in EDA verfication platform.
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*/
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mov x0, xzr
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mov x1, xzr
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mov x2, xzr
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mov x3, xzr
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mov x4, xzr
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mov x5, xzr
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mov x6, xzr
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mov x7, xzr
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mov x8, xzr
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mov x9, xzr
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mov x10, xzr
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mov x11, xzr
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mov x12, xzr
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mov x13, xzr
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mov x14, xzr
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mov x15, xzr
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mov x16, xzr
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mov x17, xzr
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mov x18, xzr
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mov x19, xzr
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mov x20, xzr
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mov x21, xzr
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mov x22, xzr
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mov x23, xzr
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mov x24, xzr
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mov x25, xzr
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mov x26, xzr
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mov x27, xzr
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mov x28, xzr
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mov x29, xzr
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mov x30, xzr
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/* ---------------------------------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------------------------------
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*/
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msr spsel, #0
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ldr x0, =__STACKS_END__
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mov sp, x0
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/* -------------------------------------------------------------
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* This is the initialisation of SCTLR_EL3 and so must ensure
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* that all fields are explicitly set rather than relying on hw.
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* Some fields reset to an IMPLEMENTATION DEFINED value and
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* others are architecturally UNKNOWN on reset.
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*
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* SCTLR.EE: Set the CPU endianness before doing anything that
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* might involve memory reads or writes. Set to zero to select
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* Little Endian.
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*
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* SCTLR_EL3.WXN: For the EL3 translation regime, this field can
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* force all memory regions that are writeable to be treated as
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* XN (Execute-never). Set to zero so that this control has no
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* effect on memory access permissions.
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*
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* SCTLR_EL3.SA: Set to zero to disable Stack Aligment check.
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*
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* SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
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* -------------------------------------------------------------
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*/
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mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
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| SCTLR_SA_BIT | SCTLR_A_BIT))
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msr sctlr_el3, x0
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isb
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/* ---------------------------------------------------------------------
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* It is a cold boot.
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* ---------------------------------------------------------------------
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*/
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el3_arch_init_common bl1_exceptions
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/* NO C runtime environment. stack only. no .bss and .data */
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bl bl1_early_platform_setup
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/* --------------------------------------------------
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* Initialize platform and jump to our c-entry point
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* for this type of reset.
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* --------------------------------------------------
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*/
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bl bl1_main
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/* --------------------------------------------------
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* Do the transition to next boot image.
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* --------------------------------------------------
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*/
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1:
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atf_err_set w14, x15, ATF_ERR_BL1_RETURN
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b 1b
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endfunc bl1_entrypoint_rel
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