151 lines
3.5 KiB
ArmAsm
151 lines
3.5 KiB
ArmAsm
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cpu.h>
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#include <aarch64/asm_macros.S>
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#include <bl_common.h>
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/* -----------------------------------------------------------------------------
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* Very simple stackless exception handlers used by BL2.
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* -----------------------------------------------------------------------------
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*/
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.globl bl2_exceptions
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vector_base bl2_exceptions
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSP0
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mov x0, #SYNC_EXCEPTION_SP_EL0
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size SynchronousExceptionSP0
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vector_entry IrqSP0
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mov x0, #IRQ_SP_EL0
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size IrqSP0
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vector_entry FiqSP0
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mov x0, #FIQ_SP_EL0
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size FiqSP0
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vector_entry SErrorSP0
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mov x0, #SERROR_SP_EL0
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionSPx
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mov x0, #SYNC_EXCEPTION_SP_ELX
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size SynchronousExceptionSPx
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vector_entry IrqSPx
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mov x0, #IRQ_SP_ELX
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size IrqSPx
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vector_entry FiqSPx
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mov x0, #FIQ_SP_ELX
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size FiqSPx
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vector_entry SErrorSPx
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mov x0, #SERROR_SP_ELX
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA64
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/* Expect only SMC exceptions */
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x30, #EC_AARCH64_SMC
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b.ne unexpected_sync_exception
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b smc_handler64
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check_vector_size SynchronousExceptionA64
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vector_entry IrqA64
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mov x0, #IRQ_AARCH64
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size IrqA64
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vector_entry FiqA64
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mov x0, #FIQ_AARCH64
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size FiqA64
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vector_entry SErrorA64
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mov x0, #SERROR_AARCH64
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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vector_entry SynchronousExceptionA32
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mov x0, #SYNC_EXCEPTION_AARCH32
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size SynchronousExceptionA32
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vector_entry IrqA32
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mov x0, #IRQ_AARCH32
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size IrqA32
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vector_entry FiqA32
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mov x0, #FIQ_AARCH32
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size FiqA32
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vector_entry SErrorA32
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mov x0, #SERROR_AARCH32
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bl cpu_report_exception
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no_ret panic_handler
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check_vector_size SErrorA32
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unexpected_sync_exception:
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl cpu_report_exception
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no_ret panic_handler
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func smc_handler64
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# Reset exception stack
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ldr x30, =__STACKS_END__
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msr spsel, #0
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mov sp, x30
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bl bl2_smc_handler
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b .
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endfunc smc_handler64
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