111 lines
1.8 KiB
ArmAsm
111 lines
1.8 KiB
ArmAsm
#include "bits.h"
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#include "csr.h"
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#include <platform.h>
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#include <riscv/asm_macros.S>
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.globl bl1_entrypoint
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.globl bl1_entrypoint_end
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.globl bl1_entrypoint_rel
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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.pushsection .entry, "ax"
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bl1_entrypoint:
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la x1, bl1_entrypoint_rel
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jr x1
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bl1_entrypoint_end:
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.popsection
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.option norvc
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.section .text.init,"ax",@progbits
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.globl bl1_entrypoint_rel
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bl1_entrypoint_rel:
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atf_state_set x28, x29, ATF_STATE_BL1_ENTRY_POINT
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atf_err_set x28, x29, ATF_ERR_NONE
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10, 0
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li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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csrw mscratch, x0
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# write mtvec and make sure it sticks
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la t0, trap_vector
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csrw mtvec, t0
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# set mxstatus to init value
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li x3, 0xc0638000
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csrw mxstatus, x3
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# set plic_ctrl = 1 for linux plic
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li x3, 0x701FFFFC # plic_base + 0x1FFFFC
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li x4, 1
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sw x4 , 0(x3)
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// invalidate all memory for BTB,BHT,DCACHE,ICACHE
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li x3, 0x30013
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csrs mcor, x3
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// enable ICACHE,DCACHE,BHT,BTB,RAS,WA
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li x3, 0x7f
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csrs mhcr, x3
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// enable data_cache_prefetch, amr
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li x3, 0x610c
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csrs mhint, x3 #mhint
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# enable fp
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li x3, 0x1 << 13
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csrs mstatus, x3
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la sp, __STACKS_END__
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call bl1_early_platform_setup
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call bl1_main
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j die
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.balign 4
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trap_vector:
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die:
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j panic_handler
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j die
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.bss
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.align RISCV_PGSHIFT
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stacks:
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.skip RISCV_PGSIZE
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.section .rodata
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