5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
33 lines
1.1 KiB
Plaintext
33 lines
1.1 KiB
Plaintext
Xilinx LogiCORE Partial Reconfig Decoupler Softcore
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The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
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decouplers / fpga bridges.
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The controller can decouple/disable the bridges which prevents signal
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changes from passing through the bridge. The controller can also
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couple / enable the bridges which allows traffic to pass through the
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bridge normally.
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The Driver supports only MMIO handling. A PR region can have multiple
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PR Decouplers which can be handled independently or chained via decouple/
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decouple_status signals.
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Required properties:
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- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
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"xlnx,pr-decoupler"
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- regs : base address and size for decoupler module
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- clocks : input clock to IP
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- clock-names : should contain "aclk"
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See Documentation/devicetree/bindings/fpga/fpga-region.txt and
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Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
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Example:
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fpga-bridge@100000450 {
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compatible = "xlnx,pr-decoupler-1.00",
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"xlnx-pr-decoupler";
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regs = <0x10000045 0x10>;
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clocks = <&clkc 15>;
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clock-names = "aclk";
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bridge-enable = <0>;
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};
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