5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
52 lines
1.6 KiB
Plaintext
52 lines
1.6 KiB
Plaintext
Xilinx Slave Serial SPI FPGA Manager
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Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
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bitstream over what is referred to as "slave serial" interface.
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The slave serial link is not technically SPI, and might require extra
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circuits in order to play nicely with other SPI slaves on the same bus.
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See:
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- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
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- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
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- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
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Required properties:
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- compatible: should contain "xlnx,fpga-slave-serial"
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- reg: spi chip select of the FPGA
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- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
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- done-gpios: config status pin (referred to as DONE in the manual)
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Optional properties:
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- init-b-gpios: initialization status and configuration error pin
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(referred to as INIT_B in the manual)
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Example for full FPGA configuration:
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fpga-region0 {
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compatible = "fpga-region";
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fpga-mgr = <&fpga_mgr_spi>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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};
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spi1: spi@10680 {
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compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <92>;
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clocks = <&coreclk 0>;
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fpga_mgr_spi: fpga-mgr@0 {
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compatible = "xlnx,fpga-slave-serial";
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spi-max-frequency = <60000000>;
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spi-cpha;
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reg = <0>;
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prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
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init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
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done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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};
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};
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