5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
34 lines
763 B
Plaintext
34 lines
763 B
Plaintext
Cavium, Inc. OCTEON SOC SPI master controller.
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Required properties:
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- compatible : "cavium,octeon-3010-spi"
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- reg : The register base for the controller.
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- interrupts : One interrupt, used by the controller.
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- #address-cells : <1>, as required by generic SPI binding.
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- #size-cells : <0>, also as required by generic SPI binding.
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Child nodes as per the generic SPI binding.
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Example:
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spi@1070000001000 {
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compatible = "cavium,octeon-3010-spi";
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reg = <0x10700 0x00001000 0x0 0x100>;
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interrupts = <0 58>;
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#address-cells = <1>;
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#size-cells = <0>;
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eeprom@0 {
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compatible = "st,m95256", "atmel,at25";
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reg = <0>;
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spi-max-frequency = <5000000>;
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spi-cpha;
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spi-cpol;
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pagesize = <64>;
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size = <32768>;
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address-width = <16>;
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};
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};
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