5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
33 lines
909 B
Plaintext
33 lines
909 B
Plaintext
Xilinx SuperSpeed DWC3 USB SoC controller
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Required properties:
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- compatible: Should contain "xlnx,zynqmp-dwc3"
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- clocks: A list of phandles for the clocks listed in clock-names
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- clock-names: Should contain the following:
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"bus_clk" Master/Core clock, have to be >= 125 MHz for SS
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operation and >= 60MHz for HS operation
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"ref_clk" Clock source to core during PHY power down
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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Example device node:
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usb@0 {
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#address-cells = <0x2>;
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#size-cells = <0x1>;
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compatible = "xlnx,zynqmp-dwc3";
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clock-names = "bus_clk" "ref_clk";
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clocks = <&clk125>, <&clk125>;
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ranges;
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dwc3@fe200000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe200000 0x40000>;
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interrupts = <0x0 0x41 0x4>;
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dr_mode = "host";
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};
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};
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