5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
50 lines
1.2 KiB
ArmAsm
50 lines
1.2 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/fiqasm.S
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*
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* Derived from code originally in linux/arch/arm/kernel/fiq.c:
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*
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* Copyright (C) 1998 Russell King
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* Copyright (C) 1998, 1999 Phil Blundell
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* Copyright (C) 2011, Linaro Limited
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*
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* FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
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*
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* FIQ support re-written by Russell King to be more generic
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*
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* v7/Thumb-2 compatibility modifications by Linaro Limited, 2011.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* Taking an interrupt in FIQ mode is death, so both these functions
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* disable irqs for the duration.
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*/
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ENTRY(__set_fiq_regs)
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mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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mrs r1, cpsr
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msr cpsr_c, r2 @ select FIQ mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ldmia r0!, {r8 - r12}
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ldr sp, [r0], #4
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ldr lr, [r0]
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msr cpsr_c, r1 @ return to SVC mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ret lr
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ENDPROC(__set_fiq_regs)
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ENTRY(__get_fiq_regs)
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mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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mrs r1, cpsr
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msr cpsr_c, r2 @ select FIQ mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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stmia r0!, {r8 - r12}
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str sp, [r0], #4
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str lr, [r0]
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msr cpsr_c, r1 @ return to SVC mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ret lr
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ENDPROC(__get_fiq_regs)
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