5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
33 lines
881 B
C
33 lines
881 B
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
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*/
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#include <linux/io.h>
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#include <asm/smp_scu.h>
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#include <asm/smp.h>
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#include "addr-map.h"
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#define SW_BRANCH_VIRT_ADDR CIU_REG(0x24)
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static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/*
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* Apparently, the boot ROM on the second core spins on this
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* register becoming non-zero and then jumps to the address written
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* there. No IPIs involved.
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*/
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__raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
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return 0;
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}
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static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(SCU_VIRT_BASE);
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}
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static const struct smp_operations mmp3_smp_ops __initconst = {
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.smp_prepare_cpus = mmp3_smp_prepare_cpus,
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.smp_boot_secondary = mmp3_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);
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