4f810186ab
1. update cv182x/cv183x configuration file 2. update cv181x/cv180x configuration file 3. update clk driver for cvitek 4. update dma driver for cvitek 5. update soc driver for cvitek 6. porting cvitek ion driver from kernel-4.19 7. compatible with riscv Change-Id: Icff9fafe0ebe7d6bab824bbadb952e08bdc66c19
103 lines
1.6 KiB
C
103 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_CKMMUV1_H
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#define __ASM_CSKY_CKMMUV1_H
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#include <abi/reg_ops.h>
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static inline int read_mmu_index(void)
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{
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return cprcr("cpcr0");
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}
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static inline void write_mmu_index(int value)
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{
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cpwcr("cpcr0", value);
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}
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static inline int read_mmu_entrylo0(void)
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{
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return cprcr("cpcr2") << 6;
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}
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static inline int read_mmu_entrylo1(void)
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{
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return cprcr("cpcr3") << 6;
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}
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static inline void write_mmu_pagemask(int value)
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{
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cpwcr("cpcr6", value);
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}
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static inline int read_mmu_entryhi(void)
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{
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return cprcr("cpcr4");
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}
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static inline void write_mmu_entryhi(int value)
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{
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cpwcr("cpcr4", value);
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}
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static inline unsigned long read_mmu_msa0(void)
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{
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return cprcr("cpcr30");
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}
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static inline void write_mmu_msa0(unsigned long value)
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{
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cpwcr("cpcr30", value);
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}
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static inline unsigned long read_mmu_msa1(void)
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{
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return cprcr("cpcr31");
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}
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static inline void write_mmu_msa1(unsigned long value)
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{
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cpwcr("cpcr31", value);
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}
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/*
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* TLB operations.
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*/
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static inline void tlb_probe(void)
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{
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cpwcr("cpcr8", 0x80000000);
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}
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static inline void tlb_read(void)
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{
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cpwcr("cpcr8", 0x40000000);
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}
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static inline void tlb_invalid_all(void)
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{
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cpwcr("cpcr8", 0x04000000);
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}
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static inline void local_tlb_invalid_all(void)
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{
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tlb_invalid_all();
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}
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static inline void tlb_invalid_indexed(void)
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{
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cpwcr("cpcr8", 0x02000000);
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}
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static inline void setup_pgd(pgd_t *pgd, int asid)
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{
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cpwcr("cpcr29", __pa(pgd) | BIT(0));
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write_mmu_entryhi(asid);
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}
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static inline pgd_t *get_pgd(void)
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{
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return __va(cprcr("cpcr29") & ~BIT(0));
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}
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#endif /* __ASM_CSKY_CKMMUV1_H */
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