5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
34 lines
1.1 KiB
C
34 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* include/asm-sh/cpu-sh4/sq.h
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*
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* Copyright (C) 2001, 2002, 2003 Paul Mundt
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* Copyright (C) 2001, 2002 M. R. Brown
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*/
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#ifndef __ASM_CPU_SH4_SQ_H
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#define __ASM_CPU_SH4_SQ_H
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#include <asm/addrspace.h>
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#include <asm/page.h>
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/*
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* Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
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* mapped to any physical address space. Since data is written (and aligned)
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* to 32-byte boundaries, we need to be sure that all allocations are aligned.
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*/
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#define SQ_SIZE 32
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#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
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#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
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#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
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#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
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#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
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/* arch/sh/kernel/cpu/sh4/sq.c */
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unsigned long sq_remap(unsigned long phys, unsigned int size,
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const char *name, pgprot_t prot);
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void sq_unmap(unsigned long vaddr);
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void sq_flush_range(unsigned long start, unsigned int len);
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#endif /* __ASM_CPU_SH4_SQ_H */
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