edd73bf069
[ion] support get ion total size [fb_ili9341]fb_ili9341 bring up Change-Id: I41cf49172640923ebc64947cbc9a23cad3d05a46
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/*
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* drivers/mmc/host/sdhci-cvi.c - CVITEK SDHCI Platform driver
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*
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* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SDHCI_CV_H
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#define __SDHCI_CV_H
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/delay.h>
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#include <linux/mmc/mmc.h>
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#include <linux/slab.h>
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#define MAX_TUNING_CMD_RETRY_COUNT 50
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#define TUNE_MAX_PHCODE 128
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#define TAP_WINDOW_THLD 20
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#define DISPPLL_MHZ 1188
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#define FPLL_MHZ 1500
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#define TOP_BASE 0x03000000
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#define OFFSET_SD_PWRSW_CTRL 0x1F4
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#define PINMUX_BASE 0x03001000
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#define CLKGEN_BASE 0x03002000
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#define CVI_CV180X_SDHCI_VENDOR_OFFSET 0x200
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#define CVI_CV180X_SDHCI_VENDOR_MSHC_CTRL_R (CVI_CV180X_SDHCI_VENDOR_OFFSET + 0x0)
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#define CVI_CV180X_SDHCI_PHY_TX_RX_DLY (CVI_CV180X_SDHCI_VENDOR_OFFSET + 0x40)
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#define CVI_CV180X_SDHCI_PHY_DS_DLY (CVI_CV180X_SDHCI_VENDOR_OFFSET + 0x44)
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#define CVI_CV180X_SDHCI_PHY_DLY_STS (CVI_CV180X_SDHCI_VENDOR_OFFSET + 0x48)
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#define CVI_CV180X_SDHCI_PHY_CONFIG (CVI_CV180X_SDHCI_VENDOR_OFFSET + 0x4C)
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#define SDHCI_GPIO_CD_DEBOUNCE_TIME 10
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#define SDHCI_GPIO_CD_DEBOUNCE_DELAY_TIME 200
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#ifdef CONFIG_PM_SLEEP
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#ifdef CONFIG_ARCH_CV180X_ASIC
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#define RTC_CTRL_BASE 0x5025000
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#define RTCSYS_CLKMUX 0x1C
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#define RTCSYS_CLKBYP 0x30
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#define RTCSYS_MCU51_ICTRL1 0x7C
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#define RTCSYS_CTRL 0x248
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struct cvi_rtc_sdhci_reg_context {
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u32 rtcsys_clkmux;
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u32 rtcsys_clkbyp;
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u32 rtcsys_mcu51_ictrl1;
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u32 rtcsys_ctrl;
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};
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#else
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struct cvi_rtc_sdhci_reg_context {};
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#endif
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#endif
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struct sdhci_cvi_host {
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struct sdhci_host *host;
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struct platform_device *pdev;
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void __iomem *core_mem; /* mmio address */
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struct clk *clk; /* main SD/MMC bus clock */
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struct clk *clk100k;
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struct clk *clkaxi;
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struct mmc_host *mmc;
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struct reset_control *reset;
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struct reset_control *clk_rst_axi_emmc_ctrl;
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struct reset_control *clk_rst_emmc_ctrl;
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struct reset_control *clk_rst_100k_emmc_ctrl;
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void __iomem *topbase;
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void __iomem *pinmuxbase;
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void __iomem *clkgenbase;
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u32 reg_ctrl2;
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u32 reg_clk_ctrl;
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u32 reg_host_ctrl;
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u8 final_tap;
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u8 sdio0_voltage_1_8_v;
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int sd_save_count;
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struct mmc_gpio *cvi_gpio;
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struct delayed_work cd_debounce_work;
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spinlock_t cd_debounce_lock;
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int pre_gpio_cd;
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bool is_debounce_work_running;
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#ifdef CONFIG_PM_SLEEP
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struct cvi_rtc_sdhci_reg_context *rtc_reg_ctx;
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#endif
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};
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#endif
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