4f810186ab
1. update cv182x/cv183x configuration file 2. update cv181x/cv180x configuration file 3. update clk driver for cvitek 4. update dma driver for cvitek 5. update soc driver for cvitek 6. porting cvitek ion driver from kernel-4.19 7. compatible with riscv Change-Id: Icff9fafe0ebe7d6bab824bbadb952e08bdc66c19
100 lines
2.7 KiB
C
100 lines
2.7 KiB
C
/*
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* drivers/mmc/host/sdhci-cvi.c - CVITEK SDHCI Platform driver
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*
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* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SDHCI_CV_H
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#define __SDHCI_CV_H
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/delay.h>
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#include <linux/mmc/mmc.h>
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#include <linux/slab.h>
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#define MAX_TUNING_CMD_RETRY_COUNT 50
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#define TUNE_MAX_PHCODE 128
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#define TAP_WINDOW_THLD 20
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#define DISPPLL_MHZ 1188
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#define FPLL_MHZ 1500
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#define TOP_BASE 0x3000000
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#define OFFSET_SD_PWRSW_CTRL 0x1F4
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#define PINMUX_BASE 0x03001000
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#define CLKGEN_BASE 0x03002000
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#define CVI_183X_SDHCI_VENDOR_OFFSET 0x500
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#define CVI_183X_SDHCI_VENDOR_MSHC_CTRL_R (CVI_183X_SDHCI_VENDOR_OFFSET + 0x08)
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#define CVI_183X_SDHCI_VENDOR_A_CTRL_R (CVI_183X_SDHCI_VENDOR_OFFSET + 0x40)
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#define CVI_183X_SDHCI_VENDOR_A_STAT_R (CVI_183X_SDHCI_VENDOR_OFFSET + 0x44)
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/* PHY register */
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#define SDHCI_PHY_R_OFFSET 0x300
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#define SDHCI_P_PHY_CNFG (SDHCI_PHY_R_OFFSET + 0x00)
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#define SDHCI_RX_DELAY_LINE (SDHCI_PHY_R_OFFSET + 0x0C)
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#define SDHCI_TX_DELAY_LINE (SDHCI_PHY_R_OFFSET + 0x1C)
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#define SDHCI_P_SDCLKDL_DC (SDHCI_PHY_R_OFFSET + 0x1E)
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#define SDHCI_LEAD_LAG_FLAG (SDHCI_PHY_R_OFFSET + 0x12)
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#define PHY_CNFG_PHY_RSTN 0
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#define PHY_CNFG_PHY_PWRGOOD 1
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#define PHY_CNFG_PAD_SP 16
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#define PHY_CNFG_PAD_SP_MSK 0xf
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#define PHY_CNFG_PAD_SN 20
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#define PHY_CNFG_PAD_SN_MSK 0xf
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#define SDHCI_GPIO_CD_DEBOUNCE_TIME 15
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#define SDHCI_GPIO_CD_DEBOUNCE_DELAY_TIME 200
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#ifdef CONFIG_PM_SLEEP
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struct cvi_rtc_sdhci_reg_context {};
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#endif
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struct sdhci_cvi_host {
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struct sdhci_host *host;
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struct platform_device *pdev;
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void __iomem *core_mem; /* mmio address */
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struct clk *clk; /* main SD/MMC bus clock */
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struct clk *clk100k;
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struct clk *clkaxi;
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struct mmc_host *mmc;
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struct reset_control *reset;
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struct reset_control *clk_rst_axi_emmc_ctrl;
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struct reset_control *clk_rst_emmc_ctrl;
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struct reset_control *clk_rst_100k_emmc_ctrl;
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int gpio_card_cd;
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int gpio_card_cd_active;
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void __iomem *topbase;
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void __iomem *pinmuxbase;
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void __iomem *clkgenbase;
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u32 reg_ctrl2;
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u32 reg_clk_ctrl;
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u32 reg_host_ctrl;
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u8 final_tap;
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u8 sdio0_voltage_1_8_v;
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int sd_save_count;
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struct mmc_gpio *cvi_gpio;
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#ifdef CONFIG_PM_SLEEP
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struct cvi_rtc_sdhci_reg_context *rtc_reg_ctx;
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#endif
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};
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#endif
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