4f810186ab
1. update cv182x/cv183x configuration file 2. update cv181x/cv180x configuration file 3. update clk driver for cvitek 4. update dma driver for cvitek 5. update soc driver for cvitek 6. porting cvitek ion driver from kernel-4.19 7. compatible with riscv Change-Id: Icff9fafe0ebe7d6bab824bbadb952e08bdc66c19
126 lines
3.1 KiB
C
126 lines
3.1 KiB
C
/*
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* Bitmain SoCs Reset Controller driver
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*
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* Copyright (c) 2018 Bitmain Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define BITS_PER_REG 32
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struct bm_reset_data {
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spinlock_t lock;
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void __iomem *membase;
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struct reset_controller_dev rcdev;
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};
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static int bm_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct bm_reset_data *data = container_of(rcdev,
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struct bm_reset_data,
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rcdev);
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int bank = id / BITS_PER_REG;
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int offset = id % BITS_PER_REG;
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(data->membase + (bank * 4));
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writel(reg & ~BIT(offset), data->membase + (bank * 4));
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int bm_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct bm_reset_data *data = container_of(rcdev,
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struct bm_reset_data,
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rcdev);
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int bank = id / BITS_PER_REG;
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int offset = id % BITS_PER_REG;
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(data->membase + (bank * 4));
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writel(reg | BIT(offset), data->membase + (bank * 4));
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static const struct reset_control_ops bm_reset_ops = {
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.assert = bm_reset_assert,
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.deassert = bm_reset_deassert,
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};
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static const struct of_device_id bm_reset_dt_ids[] = {
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{ .compatible = "cvitek,clk-reset", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, bm_reset_dt_ids);
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static int bm_reset_probe(struct platform_device *pdev)
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{
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struct bm_reset_data *data;
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struct resource *res;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->membase))
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return PTR_ERR(data->membase);
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spin_lock_init(&data->lock);
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = (resource_size(res)>>2) * 32;
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pr_info("clk reset: nr_reset=%d resource_size=%lld\n", data->rcdev.nr_resets, resource_size(res));
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data->rcdev.ops = &bm_reset_ops;
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data->rcdev.of_node = pdev->dev.of_node;
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return devm_reset_controller_register(&pdev->dev, &data->rcdev);
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}
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static struct platform_driver bm_reset_driver = {
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.probe = bm_reset_probe,
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.driver = {
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.name = "bm-clock-reset",
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.of_match_table = bm_reset_dt_ids,
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},
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};
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static int __init bm_clk_reset_init(void)
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{
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return platform_driver_register(&bm_reset_driver);
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}
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postcore_initcall(bm_clk_reset_init);
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MODULE_AUTHOR("Wei Huang<wei.huang01@bitmain.com>");
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MODULE_DESCRIPTION("Cvitek SoC Clock Reset Controoler Driver");
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MODULE_LICENSE("GPL");
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