396 lines
8.8 KiB
C
396 lines
8.8 KiB
C
#ifndef _U_CIF_UAPI_H_
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#define _U_CIF_UAPI_H_
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#define MIPI_LANE_NUM 4
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#define WDR_VC_NUM 2
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#define SYNC_CODE_NUM 4
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#define BT_DEMUX_NUM 4
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#define MIPI_DEMUX_NUM 4
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struct img_size_s {
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unsigned int width;
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unsigned int height;
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};
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enum rx_mac_clk_e {
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RX_MAC_CLK_200M = 0,
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RX_MAC_CLK_300M,
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RX_MAC_CLK_400M,
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RX_MAC_CLK_500M,
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RX_MAC_CLK_600M,
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RX_MAC_CLK_BUTT,
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};
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enum cam_pll_freq_e {
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CAMPLL_FREQ_NONE = 0,
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CAMPLL_FREQ_37P125M,
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CAMPLL_FREQ_25M,
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CAMPLL_FREQ_27M,
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CAMPLL_FREQ_24M,
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CAMPLL_FREQ_26M,
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CAMPLL_FREQ_NUM
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};
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struct mclk_pll_s {
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unsigned int cam;
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enum cam_pll_freq_e freq;
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};
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struct dphy_s {
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unsigned char enable;
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unsigned char hs_settle;
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};
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enum lane_divide_mode_e {
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LANE_DIVIDE_MODE_0 = 0,
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LANE_DIVIDE_MODE_1,
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LANE_DIVIDE_MODE_2,
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LANE_DIVIDE_MODE_3,
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LANE_DIVIDE_MODE_4,
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LANE_DIVIDE_MODE_5,
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LANE_DIVIDE_MODE_6,
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LANE_DIVIDE_MODE_7,
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LANE_DIVIDE_MODE_BUTT
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};
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enum input_mode_e {
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INPUT_MODE_MIPI = 0,
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INPUT_MODE_SUBLVDS,
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INPUT_MODE_HISPI,
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INPUT_MODE_CMOS,
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INPUT_MODE_BT1120,
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INPUT_MODE_BT601,
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INPUT_MODE_BT656_9B,
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INPUT_MODE_CUSTOM_0,
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INPUT_MODE_BT_DEMUX,
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INPUT_MODE_BUTT
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};
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enum raw_data_type_e {
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RAW_DATA_8BIT = 0,
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RAW_DATA_10BIT,
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RAW_DATA_12BIT,
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YUV422_8BIT, /* MIPI-CSI only */
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YUV422_10BIT, /* MIPI-CSI only*/
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RAW_DATA_BUTT
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};
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enum mipi_wdr_mode_e {
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CVI_MIPI_WDR_MODE_NONE = 0,
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CVI_MIPI_WDR_MODE_VC,
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CVI_MIPI_WDR_MODE_DT,
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CVI_MIPI_WDR_MODE_DOL,
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CVI_MIPI_WDR_MODE_MANUAL, /* SOI case */
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CVI_MIPI_WDR_MODE_BUTT
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};
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enum wdr_mode_e {
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CVI_WDR_MODE_NONE = 0,
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CVI_WDR_MODE_2F,
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CVI_WDR_MODE_3F,
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CVI_WDR_MODE_DOL_2F,
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CVI_WDR_MODE_DOL_3F,
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CVI_WDR_MODE_DOL_BUTT
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};
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enum lvds_sync_mode_e {
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LVDS_SYNC_MODE_SOF = 0,
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LVDS_SYNC_MODE_SAV,
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LVDS_SYNC_MODE_BUTT
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};
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enum lvds_bit_endian {
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LVDS_ENDIAN_LITTLE = 0,
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LVDS_ENDIAN_BIG,
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LVDS_ENDIAN_BUTT
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};
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enum lvds_vsync_type_e {
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LVDS_VSYNC_NORMAL = 0,
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LVDS_VSYNC_SHARE,
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LVDS_VSYNC_HCONNECT,
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LVDS_VSYNC_BUTT
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};
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enum lvds_fid_type_e {
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LVDS_FID_NONE = 0,
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LVDS_FID_IN_SAV,
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LVDS_FID_BUTT
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};
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struct lvds_fid_type_s {
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enum lvds_fid_type_e fid;
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};
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struct lvds_vsync_type_s {
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enum lvds_vsync_type_e sync_type;
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unsigned short hblank1;
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unsigned short hblank2;
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};
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struct lvds_dev_attr_s {
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enum wdr_mode_e wdr_mode;
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enum lvds_sync_mode_e sync_mode;
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enum raw_data_type_e raw_data_type;
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enum lvds_bit_endian data_endian;
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enum lvds_bit_endian sync_code_endian;
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short lane_id[MIPI_LANE_NUM+1];
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short sync_code[MIPI_LANE_NUM][WDR_VC_NUM+1][SYNC_CODE_NUM];
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/*
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* sublvds:
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* sync_code[x][0][0] sync_code[x][0][1] sync_code[x][0][2] sync_code[x][0][3]
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* n0_lef_sav n0_lef_eav n1_lef_sav n1_lef_eav
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* sync_code[x][1][0] sync_code[x][1][1] sync_code[x][1][2] sync_code[x][1][3]
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* n0_sef_sav n0_sef_eav n1_sef_sav n1_sef_eav
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* sync_code[x][2][0] sync_code[x][2][1] sync_code[x][2][2] sync_code[x][2][3]
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* n0_lsef_sav n0_lsef_eav n1_lsef_sav n1_lsef_eav
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*
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* hispi:
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* sync_code[x][0][0] sync_code[x][0][1] sync_code[x][0][2] sync_code[x][0][3]
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* t1_sol tl_eol t1_sof t1_eof
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* sync_code[x][1][0] sync_code[x][1][1] sync_code[x][1][2] sync_code[x][1][3]
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* t2_sol t2_eol t2_sof t2_eof
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*/
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struct lvds_vsync_type_s vsync_type;
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struct lvds_fid_type_s fid_type;
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char pn_swap[MIPI_LANE_NUM+1];
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};
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struct mipi_demux_info_s {
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unsigned int demux_en;
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unsigned char vc_mapping[MIPI_DEMUX_NUM];
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};
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struct mipi_dev_attr_s {
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enum raw_data_type_e raw_data_type;
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short lane_id[MIPI_LANE_NUM+1];
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enum mipi_wdr_mode_e wdr_mode;
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short data_type[WDR_VC_NUM];
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char pn_swap[MIPI_LANE_NUM+1];
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struct dphy_s dphy;
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struct mipi_demux_info_s demux;
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};
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struct manual_wdr_attr_s {
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unsigned int manual_en;
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unsigned short l2s_distance;
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unsigned short lsef_length;
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unsigned int discard_padding_lines;
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unsigned int update;
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};
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enum ttl_pin_func_e {
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TTL_PIN_FUNC_VS,
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TTL_PIN_FUNC_HS,
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TTL_PIN_FUNC_VDE,
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TTL_PIN_FUNC_HDE,
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TTL_PIN_FUNC_D0,
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TTL_PIN_FUNC_D1,
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TTL_PIN_FUNC_D2,
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TTL_PIN_FUNC_D3,
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TTL_PIN_FUNC_D4,
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TTL_PIN_FUNC_D5,
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TTL_PIN_FUNC_D6,
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TTL_PIN_FUNC_D7,
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TTL_PIN_FUNC_D8,
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TTL_PIN_FUNC_D9,
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TTL_PIN_FUNC_D10,
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TTL_PIN_FUNC_D11,
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TTL_PIN_FUNC_D12,
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TTL_PIN_FUNC_D13,
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TTL_PIN_FUNC_D14,
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TTL_PIN_FUNC_D15,
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TTL_PIN_FUNC_NUM,
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};
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enum ttl_src_e {
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TTL_VI_SRC_VI0 = 0,
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TTL_VI_SRC_VI1,
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TTL_VI_SRC_VI2, /* BT demux */
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TTL_VI_SRC_NUM
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};
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enum ttl_fmt_e {
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TTL_SYNC_PAT = 0,
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TTL_VHS_11B,
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TTL_VHS_19B,
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TTL_VDE_11B,
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TTL_VDE_19B,
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TTL_VSDE_11B,
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TTL_VSDE_19B,
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};
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enum bt_demux_mode_e {
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BT_DEMUX_DISABLE = 0,
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BT_DEMUX_2,
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BT_DEMUX_3,
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BT_DEMUX_4,
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};
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struct bt_demux_sync_s {
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unsigned char sav_vld;
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unsigned char sav_blk;
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unsigned char eav_vld;
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unsigned char eav_blk;
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};
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struct bt_demux_attr_s {
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signed char func[TTL_PIN_FUNC_NUM];
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unsigned short v_fp;
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unsigned short h_fp;
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unsigned short v_bp;
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unsigned short h_bp;
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enum bt_demux_mode_e mode;
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unsigned char sync_code_part_A[3]; /* sync code 0~2 */
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struct bt_demux_sync_s sync_code_part_B[BT_DEMUX_NUM]; /* sync code 3 */
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char yc_exchg;
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};
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struct ttl_dev_attr_s {
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enum ttl_src_e vi;
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enum ttl_fmt_e ttl_fmt;
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enum raw_data_type_e raw_data_type;
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signed char func[TTL_PIN_FUNC_NUM];
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unsigned short v_bp;
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unsigned short h_bp;
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};
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struct combo_dev_attr_s {
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enum input_mode_e input_mode;
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enum rx_mac_clk_e mac_clk;
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struct mclk_pll_s mclk;
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union {
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struct mipi_dev_attr_s mipi_attr;
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struct lvds_dev_attr_s lvds_attr;
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struct ttl_dev_attr_s ttl_attr;
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struct bt_demux_attr_s bt_demux_attr;
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};
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unsigned int devno;
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struct img_size_s img_size;
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struct manual_wdr_attr_s wdr_manu;
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};
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enum clk_edge_e {
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CLK_UP_EDGE = 0,
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CLK_DOWN_EDGE,
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CLK_EDGE_BUTT
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};
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struct clk_edge_s {
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unsigned int devno;
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enum clk_edge_e edge;
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};
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enum output_msb_e {
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OUTPUT_NORM_MSB = 0,
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OUTPUT_REVERSE_MSB,
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OUTPUT_MSB_BUTT
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};
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struct msb_s {
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unsigned int devno;
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enum output_msb_e msb;
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};
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struct crop_top_s {
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unsigned int devno;
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unsigned int crop_top;
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unsigned int update;
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};
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struct manual_wdr_s {
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unsigned int devno;
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struct manual_wdr_attr_s attr;
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};
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struct vsync_gen_s {
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unsigned int devno;
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unsigned int distance_fp;
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};
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enum bt_fmt_out_e {
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BT_FMT_OUT_CBYCRY,
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BT_FMT_OUT_CRYCBY,
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BT_FMT_OUT_YCBYCR,
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BT_FMT_OUT_YCRYCB,
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};
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struct bt_fmt_out_s {
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unsigned int devno;
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enum bt_fmt_out_e fmt_out;
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};
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struct cif_crop_win_s {
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unsigned int devno;
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unsigned int enable;
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unsigned int x;
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unsigned int y;
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unsigned int w;
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unsigned int h;
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};
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struct cif_yuv_swap_s {
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unsigned int devno;
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unsigned int uv_swap;
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unsigned int yc_swap;
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};
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/* mipi_rx ioctl commands related definition */
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#define CVI_MIPI_IOC_MAGIC 'm'
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/* Support commands */
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#define CVI_MIPI_SET_DEV_ATTR _IOW(CVI_MIPI_IOC_MAGIC, \
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0x01, struct combo_dev_attr_s)
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#define CVI_MIPI_SET_OUTPUT_CLK_EDGE _IOW(CVI_MIPI_IOC_MAGIC, \
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0x02, struct clk_edge_s)
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#define CVI_MIPI_RESET_SENSOR _IOW(CVI_MIPI_IOC_MAGIC, \
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0x05, unsigned int)
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#define CVI_MIPI_UNRESET_SENSOR _IOW(CVI_MIPI_IOC_MAGIC, \
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0x06, unsigned int)
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#define CVI_MIPI_RESET_MIPI _IOW(CVI_MIPI_IOC_MAGIC, \
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0x07, unsigned int)
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#define CVI_MIPI_ENABLE_SENSOR_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
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0x10, unsigned int)
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#define CVI_MIPI_DISABLE_SENSOR_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
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0x11, unsigned int)
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#define CVI_MIPI_SET_CROP_TOP _IOW(CVI_MIPI_IOC_MAGIC, \
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0x20, struct crop_top_s)
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#define CVI_MIPI_SET_WDR_MANUAL _IOW(CVI_MIPI_IOC_MAGIC, \
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0x21, struct manual_wdr_s)
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#define CVI_MIPI_SET_LVDS_FP_VS _IOW(CVI_MIPI_IOC_MAGIC, \
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0x22, struct vsync_gen_s)
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#define CVI_MIPI_RESET_LVDS _IOW(CVI_MIPI_IOC_MAGIC, \
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0x23, unsigned int)
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#define CVI_MIPI_SET_BT_FMT_OUT _IOW(CVI_MIPI_IOC_MAGIC, \
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0x24, struct bt_fmt_out_s)
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#define CVI_MIPI_GET_CIF_ATTR _IOWR(CVI_MIPI_IOC_MAGIC, \
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0x25, struct cif_attr_s)
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#define CVI_MIPI_SET_SENSOR_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
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0x26, struct mclk_pll_s)
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#define CVI_MIPI_SET_MAX_MAC_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
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0x27, unsigned int)
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#define CVI_MIPI_SET_CROP_WINDOW _IOW(CVI_MIPI_IOC_MAGIC, \
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0x28, struct cif_crop_win_s)
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#define CVI_MIPI_SET_YUV_SWAP _IOW(CVI_MIPI_IOC_MAGIC, \
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0x29, struct cif_yuv_swap_s)
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/* Unsupport commands */
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#define CVI_MIPI_SET_PHY_CMVMODE _IOW(CVI_MIPI_IOC_MAGIC, \
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0x04, unsigned int)
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#define CVI_MIPI_UNRESET_MIPI _IOW(CVI_MIPI_IOC_MAGIC, \
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0x08, unsigned int)
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#define CVI_MIPI_RESET_SLVS _IOW(CVI_MIPI_IOC_MAGIC, \
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0x09, unsigned int)
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#define CVI_MIPI_UNRESET_SLVS _IOW(CVI_MIPI_IOC_MAGIC, \
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0x0A, unsigned int)
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#define CVI_MIPI_SET_HS_MODE _IOW(CVI_MIPI_IOC_MAGIC, \
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0x0B, unsigned int)
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#define CVI_MIPI_ENABLE_MIPI_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
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0x0C, unsigned int)
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#define CVI_MIPI_DISABLE_MIPI_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
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0x0D, unsigned int)
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#define CVI_MIPI_ENABLE_SLVS_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
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0x0E, unsigned int)
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#define CVI_MIPI_DISABLE_SLVS_CLOCK _IOW(CVI_MIPI_IOC_MAGIC, \
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0x0F, unsigned int)
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#endif // _U_CVI_VIP_CIF_H_
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