93f81bd490
repo: https://github.com/T-head-Semi/opensbi commit: 89182b257c8798e15e4c685c1af0c2862d528d2a Change-Id: I7b39d66729e0108661a6f4c9e28acbdb303684ea
71 lines
1.5 KiB
Plaintext
71 lines
1.5 KiB
Plaintext
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Damien Le Moal <damien.lemoal@wdc.com>
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "kendryte,k210";
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chosen {
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bootargs = "console=hvc0 earlycon=sbi";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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clock-frequency = <390000000>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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mmu-type = "none";
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reg = <0>;
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riscv,isa = "rv64imafdc";
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status = "okay";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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clock-frequency = <390000000>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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mmu-type = "none";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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status = "okay";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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memory@80000000 {
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/* Bank 0: 4 MB, Bank 1: 2 MB, AI chip SRAM: 2MB */
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x00800000>;
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};
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plic0: interrupt-controller@C000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended =
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<&cpu0_intc 11 &cpu0_intc 9
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&cpu1_intc 11 &cpu1_intc 9>;
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reg = <0x0 0xc000000 0x0 0x4000000>;
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};
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};
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