f8fc109960
repo: https://github.com/u-boot/u-boot commit: d80bb749fab53da72c4a0e09b8c2d2aaa3103c91 Change-Id: Ie6434426e1ec15bc08bb1832798e371f3fd5fb29
42 lines
951 B
ArmAsm
42 lines
951 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Utility functions for FEL mode.
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*
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* Copyright (c) 2015 Google, Inc
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/system.h>
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#include <linux/linkage.h>
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ENTRY(save_boot_params)
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ldr r0, =fel_stash
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str sp, [r0, #0]
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str lr, [r0, #4]
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mrs lr, cpsr @ Read CPSR
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str lr, [r0, #8]
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mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
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str lr, [r0, #12]
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mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
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str lr, [r0, #16]
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mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
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str lr, [r0, #20]
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b save_boot_params_ret
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ENDPROC(save_boot_params)
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ENTRY(return_to_fel)
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mov sp, r0
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mov lr, r1
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ldr r0, =fel_stash
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ldr r1, [r0, #20]
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mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
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ldr r1, [r0, #16]
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mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
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ldr r1, [r0, #12]
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mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
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ldr r1, [r0, #8]
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msr cpsr, r1 @ Write CPSR
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bx lr
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ENDPROC(return_to_fel)
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