f8fc109960
repo: https://github.com/u-boot/u-boot commit: d80bb749fab53da72c4a0e09b8c2d2aaa3103c91 Change-Id: Ie6434426e1ec15bc08bb1832798e371f3fd5fb29
17 lines
236 B
Plaintext
17 lines
236 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx CSE QSPI single DTS
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*
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* Copyright (C) 2015 - 2017 Xilinx, Inc.
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*/
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#include "zynq-cse-qspi.dtsi"
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/ {
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model = "Zynq CSE QSPI SINGLE Board";
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};
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&flash0 {
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spi-rx-bus-width = <4>;
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};
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