f8fc109960
repo: https://github.com/u-boot/u-boot commit: d80bb749fab53da72c4a0e09b8c2d2aaa3103c91 Change-Id: Ie6434426e1ec15bc08bb1832798e371f3fd5fb29
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Texas Instruments Keystone SerDes driver
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#ifndef __TI_KEYSTONE_SERDES_H__
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#define __TI_KEYSTONE_SERDES_H__
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/* SERDES Reference clock */
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enum ks2_serdes_clock {
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SERDES_CLOCK_100M, /* 100 MHz */
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SERDES_CLOCK_122P88M, /* 122.88 MHz */
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SERDES_CLOCK_125M, /* 125 MHz */
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SERDES_CLOCK_156P25M, /* 156.25 MHz */
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SERDES_CLOCK_312P5M, /* 312.5 MHz */
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};
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/* SERDES Lane Baud Rate */
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enum ks2_serdes_rate {
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SERDES_RATE_4P9152G, /* 4.9152 GBaud */
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SERDES_RATE_5G, /* 5 GBaud */
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SERDES_RATE_6P144G, /* 6.144 GBaud */
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SERDES_RATE_6P25G, /* 6.25 GBaud */
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SERDES_RATE_10p3125g, /* 10.3215 GBaud */
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SERDES_RATE_12p5g, /* 12.5 GBaud */
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};
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/* SERDES Lane Rate Mode */
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enum ks2_serdes_rate_mode {
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SERDES_FULL_RATE,
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SERDES_HALF_RATE,
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SERDES_QUARTER_RATE,
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};
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/* SERDES PHY TYPE */
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enum ks2_serdes_interface {
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SERDES_PHY_SGMII,
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SERDES_PHY_PCSR, /* XGE SERDES */
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};
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struct ks2_serdes {
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enum ks2_serdes_clock clk;
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enum ks2_serdes_rate rate;
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enum ks2_serdes_rate_mode rate_mode;
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enum ks2_serdes_interface intf;
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u32 loopback;
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};
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int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
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#endif /* __TI_KEYSTONE_SERDES_H__ */
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