f8fc109960
repo: https://github.com/u-boot/u-boot commit: d80bb749fab53da72c4a0e09b8c2d2aaa3103c91 Change-Id: Ie6434426e1ec15bc08bb1832798e371f3fd5fb29
44 lines
1.6 KiB
Plaintext
44 lines
1.6 KiB
Plaintext
Altera SOCFPGA Arria10 FPGA Manager
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Required properties:
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- compatible : should contain "altr,socfpga-a10-fpga-mgr"
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- reg : base address and size for memory mapped io.
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- The first index is for FPGA manager register access.
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- The second index is for writing FPGA configuration data.
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- resets : Phandle and reset specifier for the device's reset.
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- clocks : Clocks used by the device.
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- altr,bitstream : Fit image file name for both FPGA peripheral bitstream,
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FPGA core bitstream and full bitstream.
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Full bitstream, consist of peripheral bitstream and core
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bitstream.
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FPGA peripheral bitstream is used to initialize FPGA IOs,
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PLL, IO48 and DDR. This bitstream is required to get DDR up
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running.
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FPGA core bitstream contains FPGA design which is used to
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program FPGA CRAM and ERAM.
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Example: Bundles both peripheral bitstream and core bitstream into FIT image
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called fit_spl_fpga.itb. This FIT image can be created through running
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this command: tools/mkimage
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-E -p 400
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-f board/altera/arria10-socdk/fit_spl_fpga.its
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fit_spl_fpga.itb
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For details of describing structure and contents of the FIT image,
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please refer board/altera/arria10-socdk/fit_spl_fpga.its
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- Examples for booting with full release or booting with early IO release, then
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follow by entering early user mode:
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fpga_mgr: fpga-mgr@ffd03000 {
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compatible = "altr,socfpga-a10-fpga-mgr";
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reg = <0xffd03000 0x100
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0xffcfe400 0x20>;
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clocks = <&l4_mp_clk>;
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resets = <&rst FPGAMGR_RESET>;
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altr,bitstream = "fit_spl_fpga.itb";
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};
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