3a4bcfca2f
1. add cvitek folders to u-boot-2021.10 2. add cv183x/cv182x part 3. add cv181x/cv180x part Change-Id: I6dc2e5ff509dbab16bd60bfb3fd61852da5e01f6
673 lines
20 KiB
C
673 lines
20 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/sizes.h>
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#include <linux/libfdt.h>
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#include <reset.h>
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#include <mmc.h>
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#include <sdhci.h>
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#define MMC_TYPE_MMC 0 /* MMC card */
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#define MMC_TYPE_SD 1 /* SD card */
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#define MMC_TYPE_SDIO 2 /* SDIO card */
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#ifdef DEBUG
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#define pr_debug(fmt, ...) \
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printf(fmt, ##__VA_ARGS__)
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#endif
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struct cvi_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct cvi_sdhci_host {
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struct sdhci_host host;
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int pll_index;
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int pll_reg;
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int no_1_8_v;
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int is_64_addressing;
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int reset_tx_rx_phy;
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uint32_t mmc_fmax_freq;
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uint32_t mmc_fmin_freq;
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struct reset_ctl reset_ctl;
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};
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struct cvi_sdhci_driver_data {
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const struct sdhci_ops *ops;
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int index;
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};
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static void cvi_emmc_pad_setting(void)
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{
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mmio_clrsetbits_32(REG_EMMC_CLK_PAD_REG, REG_EMMC_PAD_CLR_MASK, REG_EMMC_CLK_PAD_VALUE << REG_EMMC_PAD_SHIFT);
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mmio_clrsetbits_32(REG_EMMC_RSTN_PAD_REG, REG_EMMC_PAD_CLR_MASK, REG_EMMC_RSTN_PAD_VALUE << REG_EMMC_PAD_SHIFT);
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mmio_clrsetbits_32(REG_EMMC_CMD_PAD_REG, REG_EMMC_PAD_CLR_MASK, REG_EMMC_CMD_PAD_VALUE << REG_EMMC_PAD_SHIFT);
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mmio_clrsetbits_32(REG_EMMC_DAT1_PAD_REG, REG_EMMC_PAD_CLR_MASK, REG_EMMC_DAT1_PAD_VALUE << REG_EMMC_PAD_SHIFT);
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mmio_clrsetbits_32(REG_EMMC_DAT0_PAD_REG, REG_EMMC_PAD_CLR_MASK, REG_EMMC_DAT0_PAD_VALUE << REG_EMMC_PAD_SHIFT);
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mmio_clrsetbits_32(REG_EMMC_DAT2_PAD_REG, REG_EMMC_PAD_CLR_MASK, REG_EMMC_DAT2_PAD_VALUE << REG_EMMC_PAD_SHIFT);
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mmio_clrsetbits_32(REG_EMMC_DAT3_PAD_REG, REG_EMMC_PAD_CLR_MASK, REG_EMMC_DAT3_PAD_VALUE << REG_EMMC_PAD_SHIFT);
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}
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static void cvi_sdio1_pad_setting(void)
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{
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mmio_clrsetbits_32(REG_SDIO1_CLK_PAD_REG, REG_SDIO1_PAD_CLR_MASK,
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REG_SDIO1_CLK_PAD_VALUE << REG_SDIO1_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO1_CMD_PAD_REG, REG_SDIO1_PAD_CLR_MASK,
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REG_SDIO1_CMD_PAD_VALUE << REG_SDIO1_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO1_DAT1_PAD_REG, REG_SDIO1_PAD_CLR_MASK,
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REG_SDIO1_DAT1_PAD_VALUE << REG_SDIO1_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO1_DAT0_PAD_REG, REG_SDIO1_PAD_CLR_MASK,
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REG_SDIO1_DAT0_PAD_VALUE << REG_SDIO1_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO1_DAT2_PAD_REG, REG_SDIO1_PAD_CLR_MASK,
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REG_SDIO1_DAT2_PAD_VALUE << REG_SDIO1_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO1_DAT3_PAD_REG, REG_SDIO1_PAD_CLR_MASK,
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REG_SDIO1_DAT3_PAD_VALUE << REG_SDIO1_PAD_SHIFT);
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}
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static void cvi_sdio0_pad_setting(bool reset)
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{
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if (reset) {
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mmio_clrsetbits_32(REG_SDIO0_PWR_EN_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_PWR_EN_PAD_RESET << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_CD_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_CD_PAD_RESET << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_CLK_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_CLK_PAD_RESET << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_CMD_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_CMD_PAD_RESET << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_DAT1_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_DAT1_PAD_RESET << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_DAT0_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_DAT0_PAD_RESET << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_DAT2_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_DAT2_PAD_RESET << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_DAT3_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_DAT3_PAD_RESET << REG_SDIO0_PAD_SHIFT);
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} else {
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mmio_clrsetbits_32(REG_SDIO0_PWR_EN_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_PWR_EN_PAD_VALUE << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_CD_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_CD_PAD_VALUE << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_CLK_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_CLK_PAD_VALUE << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_CMD_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_CMD_PAD_VALUE << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_DAT1_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_DAT1_PAD_VALUE << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_DAT0_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_DAT0_PAD_VALUE << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_DAT2_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_DAT2_PAD_VALUE << REG_SDIO0_PAD_SHIFT);
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mmio_clrsetbits_32(REG_SDIO0_DAT3_PAD_REG, REG_SDIO0_PAD_CLR_MASK,
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REG_SDIO0_DAT3_PAD_VALUE << REG_SDIO0_PAD_SHIFT);
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}
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}
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static void cvi_sdio0_pad_function(bool bunplug)
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{
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/* Name unplug plug
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* PAD_SDIO0_CD SDIO0 SDIO0
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* PAD_SDIO0_PWR_EN SDIO0 SDIO0
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* PAD_SDIO0_CLK XGPIO SDIO0
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* PAD_SDIO0_CMD XGPIO SDIO0
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* PAD_SDIO0_D0 XGPIO SDIO0
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* PAD_SDIO0_D1 XGPIO SDIO0
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* PAD_SDIO0_D2 XGPIO SDIO0
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* PAD_SDIO0_D3 XGPIO SDIO0
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* 0x0: SDIO0 function
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* 0x3: XGPIO function
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*/
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u8 val = (bunplug) ? 0x3 : 0x0;
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mmio_write_32(PAD_SDIO0_CD_REG, 0x0);
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mmio_write_32(PAD_SDIO0_PWR_EN_REG, 0x0);
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mmio_write_32(PAD_SDIO0_CLK_REG, val);
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mmio_write_32(PAD_SDIO0_CMD_REG, val);
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mmio_write_32(PAD_SDIO0_D0_REG, val);
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mmio_write_32(PAD_SDIO0_D1_REG, val);
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mmio_write_32(PAD_SDIO0_D2_REG, val);
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mmio_write_32(PAD_SDIO0_D3_REG, val);
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}
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static int cvi_ofdata_to_platdata(struct udevice *dev)
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{
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struct cvi_sdhci_host *cvi_host = dev_get_priv(dev);
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struct sdhci_host *host = &cvi_host->host;
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int node = dev_of_offset(dev);
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int rtc_sdio1 = fdtdec_get_uint(gd->fdt_blob, node, "rtc_sdio1", 0);
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host->name = strdup(dev->name);
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host->ioaddr = (void *)devfdt_get_addr(dev);
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host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4);
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host->max_clk = fdtdec_get_uint(gd->fdt_blob, node, "src-frequency", 0);
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cvi_host->mmc_fmin_freq = fdtdec_get_uint(gd->fdt_blob, node, "min-frequency", 200000);
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cvi_host->mmc_fmax_freq = fdtdec_get_uint(gd->fdt_blob, node, "max-frequency", 0);
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cvi_host->is_64_addressing = fdtdec_get_bool(gd->fdt_blob, node, "64_addressing");
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cvi_host->reset_tx_rx_phy = fdtdec_get_bool(gd->fdt_blob, node, "reset_tx_rx_phy");
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cvi_host->no_1_8_v = fdtdec_get_bool(gd->fdt_blob, node, "no-1-8-v");
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cvi_host->pll_index = fdtdec_get_uint(gd->fdt_blob, node, "pll_index", 0);
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cvi_host->pll_reg = fdtdec_get_uint(gd->fdt_blob, node, "pll_reg", 0);
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if (cvi_host->no_1_8_v)
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host->quirks |= SDHCI_QUIRK_NO_1_8_V;
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if (rtc_sdio1) {
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// set rtc sdio1 related register
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writel(0x1, (unsigned int *)0x03000248);
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writel(0x10, (unsigned int *)0x0502501c);
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writel(0xfffffffc, (unsigned int *)0x05025030);
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//writel(0x0, 0x0502507c);
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}
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if (host->ioaddr == (void *)FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static int cvi_sdhci_bind(struct udevice *dev)
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{
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struct cvi_sdhci_plat *plat = dev_get_plat(dev);
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pr_debug("[hq] %s\n", __func__);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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#ifdef CONFIG_MMC_SUPPORTS_TUNING
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static void cvi_mmc_set_tap(struct sdhci_host *host, u16 tap)
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{
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pr_debug("%s %d\n", __func__, tap);
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// Set sd_clk_en(0x2c[2]) to 0
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sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) & (~(BIT(2))), SDHCI_CLOCK_CONTROL);
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sdhci_writel(host,
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sdhci_readl(host, CVI_SDHCI_VENDOR_MSHC_CTRL_R) & (~(BIT(1))),
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CVI_SDHCI_VENDOR_MSHC_CTRL_R);
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sdhci_writel(host, BIT(8) | tap << 16, CVI_SDHCI_PHY_TX_RX_DLY);
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sdhci_writel(host, 0, CVI_SDHCI_PHY_CONFIG);
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// Set sd_clk_en(0x2c[2]) to 1
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sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) | BIT(2), SDHCI_CLOCK_CONTROL);
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}
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static inline uint32_t CHECK_MASK_BIT(void *_mask, uint32_t bit)
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{
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uint32_t w = bit / 8;
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uint32_t off = bit % 8;
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return ((uint8_t *)_mask)[w] & (1 << off);
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}
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static inline void SET_MASK_BIT(void *_mask, uint32_t bit)
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{
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uint32_t byte = bit / 8;
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uint32_t offset = bit % 8;
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((uint8_t *)_mask)[byte] |= (1 << offset);
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}
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static void reset_after_tuning_pass(struct sdhci_host *host)
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{
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pr_debug("tuning pass\n");
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/* Clear BUF_RD_READY intr */
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sdhci_writew(host, sdhci_readw(host, SDHCI_INT_STATUS) & (~(0x1 << 5)),
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SDHCI_INT_STATUS);
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/* Set SDHCI_SOFTWARE_RESET.SW_RST_DAT = 1 to clear buffered tuning block */
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sdhci_writeb(host, sdhci_readb(host, SDHCI_SOFTWARE_RESET) | (0x1 << 2), SDHCI_SOFTWARE_RESET);
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/* Set SDHCI_SOFTWARE_RESET.SW_RST_CMD = 1 */
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sdhci_writeb(host, sdhci_readb(host, SDHCI_SOFTWARE_RESET) | (0x1 << 1), SDHCI_SOFTWARE_RESET);
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while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & 0x3)
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;
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}
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int cvi_general_execute_tuning(struct mmc *mmc, u8 opcode)
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{
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u16 min = 0;
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u32 k = 0;
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s32 ret;
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u32 retry_cnt = 0;
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u32 tuning_result[4] = {0, 0, 0, 0};
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u32 rx_lead_lag_result[4] = {0, 0, 0, 0};
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char tuning_graph[TUNE_MAX_PHCODE + 1];
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char rx_lead_lag_graph[TUNE_MAX_PHCODE + 1];
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u32 reg = 0;
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u32 reg_rx_lead_lag = 0;
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s32 max_lead_lag_idx = -1;
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s32 max_window_idx = -1;
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s32 cur_window_idx = -1;
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u16 max_lead_lag_size = 0;
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u16 max_window_size = 0;
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u16 cur_window_size = 0;
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s32 rx_lead_lag_phase = -1;
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s32 final_tap = -1;
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u32 rate = 0;
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struct cvi_sdhci_host *cvi_host = dev_get_priv(mmc->dev);
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struct sdhci_host *host = &cvi_host->host;
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u32 norm_stat_en_b, err_stat_en_b;
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u32 norm_signal_en_b, ctl2;
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norm_stat_en_b = sdhci_readw(host, SDHCI_INT_ENABLE);
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err_stat_en_b = sdhci_readw(host, SDHCI_ERR_INT_STATUS_EN);
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norm_signal_en_b = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
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reg = sdhci_readw(host, SDHCI_ERR_INT_STATUS);
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pr_debug("mmc%d : SDHCI_ERR_INT_STATUS 0x%x\n", host->index, reg);
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reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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pr_debug("mmc%d : host ctrl2 0x%x\n", host->index, reg);
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/* Set Host_CTRL2_R.SAMPLE_CLK_SEL=0 */
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sdhci_writew(host,
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sdhci_readw(host, SDHCI_HOST_CONTROL2) & (~(0x1 << 7)),
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SDHCI_HOST_CONTROL2);
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sdhci_writew(host,
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sdhci_readw(host, SDHCI_HOST_CONTROL2) & (~(0x3 << 4)),
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SDHCI_HOST_CONTROL2);
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reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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pr_debug("mmc%d : host ctrl2 0x%x\n", host->index, reg);
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while (min < TUNE_MAX_PHCODE) {
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retry_cnt = 0;
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cvi_mmc_set_tap(host, min);
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reg_rx_lead_lag = sdhci_readw(host, CVI_SDHCI_PHY_DLY_STS) & BIT(1);
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retry_tuning:
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ret = mmc_send_tuning(host->mmc, opcode, NULL);
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if (!ret && retry_cnt < MAX_TUNING_CMD_RETRY_COUNT) {
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retry_cnt++;
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goto retry_tuning;
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}
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if (ret) {
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SET_MASK_BIT(tuning_result, min);
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}
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if (reg_rx_lead_lag) {
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SET_MASK_BIT(rx_lead_lag_result, min);
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}
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min++;
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}
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reset_after_tuning_pass(host);
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pr_debug("mmc%d : tuning result: 0x%08x 0x%08x 0x%08x 0x%08x\n", host->index,
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tuning_result[0], tuning_result[1],
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tuning_result[2], tuning_result[3]);
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pr_debug("mmc%d : rx_lead_lag result: 0x%08x 0x%08x 0x%08x 0x%08x\n", host->index,
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rx_lead_lag_result[0], rx_lead_lag_result[1],
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rx_lead_lag_result[2], rx_lead_lag_result[3]);
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for (k = 0; k < TUNE_MAX_PHCODE; k++) {
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if (CHECK_MASK_BIT(tuning_result, k) == 0)
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tuning_graph[k] = '-';
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else
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tuning_graph[k] = 'x';
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if (CHECK_MASK_BIT(rx_lead_lag_result, k) == 0)
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rx_lead_lag_graph[k] = '0';
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else
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rx_lead_lag_graph[k] = '1';
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}
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tuning_graph[TUNE_MAX_PHCODE] = '\0';
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rx_lead_lag_graph[TUNE_MAX_PHCODE] = '\0';
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pr_debug("mmc%d : tuning graph: %s\n", host->index, tuning_graph);
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pr_debug("mmc%d : rx_lead_lag graph: %s\n", host->index, rx_lead_lag_graph);
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// Find a final tap as median of maximum window
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for (k = 0; k < TUNE_MAX_PHCODE; k++) {
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if (CHECK_MASK_BIT(tuning_result, k) == 0) {
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if (-1 == cur_window_idx) {
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cur_window_idx = k;
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}
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cur_window_size++;
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if (cur_window_size > max_window_size) {
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max_window_size = cur_window_size;
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max_window_idx = cur_window_idx;
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if (max_window_size >= TAP_WINDOW_THLD)
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final_tap = cur_window_idx + (max_window_size / 2);
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}
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} else {
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cur_window_idx = -1;
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cur_window_size = 0;
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}
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}
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cur_window_idx = -1;
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cur_window_size = 0;
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for (k = 0; k < TUNE_MAX_PHCODE; k++) {
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if (CHECK_MASK_BIT(rx_lead_lag_result, k) == 0) {
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//from 1 to 0 and window_size already computed.
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if ((rx_lead_lag_phase == 1) && (cur_window_size > 0)) {
|
|
max_lead_lag_idx = cur_window_idx;
|
|
max_lead_lag_size = cur_window_size;
|
|
break;
|
|
}
|
|
if (cur_window_idx == -1) {
|
|
cur_window_idx = k;
|
|
}
|
|
cur_window_size++;
|
|
rx_lead_lag_phase = 0;
|
|
} else {
|
|
rx_lead_lag_phase = 1;
|
|
if ((cur_window_idx != -1) && (cur_window_size > 0)) {
|
|
cur_window_size++;
|
|
max_lead_lag_idx = cur_window_idx;
|
|
max_lead_lag_size = cur_window_size;
|
|
} else {
|
|
cur_window_size = 0;
|
|
}
|
|
}
|
|
}
|
|
rate = max_window_size * 100 / max_lead_lag_size;
|
|
pr_debug("mmc%d : MaxWindow[Idx, Width]:[%d,%u] Tuning Tap: %d\n", host->index, max_window_idx, max_window_size, final_tap);
|
|
pr_debug("mmc%d : RX_LeadLag[Idx, Width]:[%d,%u] rate = %d\n", host->index, max_lead_lag_idx, max_lead_lag_size, rate);
|
|
|
|
cvi_mmc_set_tap(host, final_tap);
|
|
//cvi_host->final_tap = final_tap;
|
|
ret = mmc_send_tuning(host->mmc, opcode, NULL);
|
|
printf("mmc%d : finished tuning, code:%d\n", host->index, final_tap);
|
|
|
|
ctl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
ctl2 &= ~SDHCI_CTRL_EXEC_TUNING;
|
|
sdhci_writew(host, ctl2, SDHCI_HOST_CONTROL2);
|
|
|
|
sdhci_writew(host, norm_stat_en_b, SDHCI_INT_ENABLE);
|
|
sdhci_writel(host, norm_signal_en_b, SDHCI_SIGNAL_ENABLE);
|
|
sdhci_writew(host, err_stat_en_b, SDHCI_ERR_INT_STATUS_EN);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static void cvi_general_reset(struct sdhci_host *host, u8 mask)
|
|
{
|
|
u16 ctrl_2;
|
|
|
|
if (host->index == MMC_TYPE_MMC) {
|
|
//reg_0x200[0] = 1 for mmc
|
|
sdhci_writel(host,
|
|
sdhci_readl(host, CVI_SDHCI_VENDOR_MSHC_CTRL_R) | BIT(0),
|
|
CVI_SDHCI_VENDOR_MSHC_CTRL_R);
|
|
}
|
|
|
|
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
pr_debug("%s-%d MMC%d : ctrl_2 = 0x%04x\n", __func__, __LINE__, host->index, ctrl_2);
|
|
|
|
ctrl_2 &= SDHCI_CTRL_UHS_MASK;
|
|
if (ctrl_2 == SDHCI_CTRL_UHS_SDR104) {
|
|
//reg_0x200[1] = 0
|
|
sdhci_writel(host,
|
|
sdhci_readl(host, CVI_SDHCI_VENDOR_MSHC_CTRL_R) & ~(BIT(1)),
|
|
CVI_SDHCI_VENDOR_MSHC_CTRL_R);
|
|
if (host->index == MMC_TYPE_SDIO) {
|
|
//reg_0x200[16] = 1 for sd1
|
|
sdhci_writel(host,
|
|
sdhci_readl(host, CVI_SDHCI_VENDOR_MSHC_CTRL_R) | BIT(16),
|
|
CVI_SDHCI_VENDOR_MSHC_CTRL_R);
|
|
}
|
|
//reg_0x24c[0] = 0
|
|
sdhci_writel(host,
|
|
sdhci_readl(host, CVI_SDHCI_PHY_CONFIG) & ~(BIT(0)),
|
|
CVI_SDHCI_PHY_CONFIG);
|
|
//reg_0x240[22:16] = tap reg_0x240[9:8] = 1 reg_0x240[6:0] = 0
|
|
sdhci_writel(host, (BIT(8) | ((0 & 0x7F) << 16)), CVI_SDHCI_PHY_TX_RX_DLY);
|
|
} else {
|
|
//Reset as DS/HS setting.
|
|
//reg_0x200[1] = 1
|
|
sdhci_writel(host,
|
|
sdhci_readl(host, CVI_SDHCI_VENDOR_MSHC_CTRL_R) | BIT(1),
|
|
CVI_SDHCI_VENDOR_MSHC_CTRL_R);
|
|
if (host->index == MMC_TYPE_SDIO) {
|
|
//reg_0x200[16] = 1 for sd1
|
|
sdhci_writel(host,
|
|
sdhci_readl(host, CVI_SDHCI_VENDOR_MSHC_CTRL_R) | BIT(16),
|
|
CVI_SDHCI_VENDOR_MSHC_CTRL_R);
|
|
}
|
|
//reg_0x24c[0] = 1
|
|
sdhci_writel(host,
|
|
sdhci_readl(host, CVI_SDHCI_PHY_CONFIG) | BIT(0),
|
|
CVI_SDHCI_PHY_CONFIG);
|
|
//reg_0x240[25:24] = 1 reg_0x240[22:16] = 0 reg_0x240[9:8] = 1 reg_0x240[6:0] = 0
|
|
sdhci_writel(host, 0x1000100, CVI_SDHCI_PHY_TX_RX_DLY);
|
|
}
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_MMC_UHS_SUPPORT
|
|
static void cvi_sd_voltage_switch(struct mmc *mmc)
|
|
{
|
|
pr_debug("%s-%d\n", __func__, __LINE__);
|
|
|
|
//enable SDIO0_CLK[7:5] to set CLK max strengh
|
|
mmio_setbits_32(REG_SDIO0_CLK_PAD_REG, BIT(7) | BIT(6) | BIT(5));
|
|
|
|
//Voltage switching flow (1.8v)
|
|
//reg_pwrsw_auto=1, reg_pwrsw_disc=0, pwrsw_vsel=1(1.8v), reg_en_pwrsw=1
|
|
mmio_write_32(TOP_BASE + REG_TOP_SD_PWRSW_CTRL, 0xB);
|
|
|
|
//wait 1ms
|
|
mdelay(1);
|
|
}
|
|
#endif
|
|
|
|
int cvi_get_cd(struct sdhci_host *host)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
|
|
pr_debug("%s reg = 0x08%x\n", __func__, reg);
|
|
if (reg & SDHCI_CARD_PRESENT) {
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int cvi_sdhci_probe(struct udevice *dev)
|
|
{
|
|
struct cvi_sdhci_driver_data *drv_data =
|
|
(struct cvi_sdhci_driver_data *)dev_get_driver_data(dev);
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct cvi_sdhci_plat *plat = dev_get_plat(dev);
|
|
struct cvi_sdhci_host *cvi_host = dev_get_priv(dev);
|
|
struct sdhci_host *host = &cvi_host->host;
|
|
int ret;
|
|
|
|
pr_debug("%s-%d: mmc%d probe\n", __func__, __LINE__, host->index);
|
|
ret = reset_get_by_name(dev, "sdhci", &cvi_host->reset_ctl);
|
|
if (ret) {
|
|
pr_debug("warning: reset_get_by_name failed\n");
|
|
} else {
|
|
// Try to solve 1.8 to 3.3v converter HW issue
|
|
ret = reset_assert(&cvi_host->reset_ctl);
|
|
if (ret) {
|
|
printf("%s failed assert reset\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
ret = reset_deassert(&cvi_host->reset_ctl);
|
|
if (ret) {
|
|
printf("%s failed deassert reset\n", __func__);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
upriv->mmc = &plat->mmc;
|
|
host->mmc = &plat->mmc;
|
|
host->mmc->priv = host;
|
|
host->mmc->dev = dev;
|
|
host->ops = drv_data->ops;
|
|
host->index = drv_data->index;
|
|
pr_debug("host %p, mmc %p, priv %p\n", host, host->mmc, host->mmc->priv);
|
|
|
|
ret = sdhci_setup_cfg(&plat->cfg, host, cvi_host->mmc_fmax_freq, cvi_host->mmc_fmin_freq);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
|
|
if (host->index == MMC_TYPE_MMC) {
|
|
cvi_emmc_pad_setting();
|
|
sdhci_writel(host, sdhci_readl(host, CVI_SDHCI_VENDOR_MSHC_CTRL_R) | BIT(0),
|
|
CVI_SDHCI_VENDOR_MSHC_CTRL_R);
|
|
} else if (host->index == MMC_TYPE_SD) {
|
|
if (host->ops && host->ops->get_cd) {
|
|
int present = host->ops->get_cd(host);
|
|
|
|
if (present == 1) {
|
|
//Voltage switching flow (3.3)
|
|
//(reg_pwrsw_auto=1, reg_pwrsw_disc=0, reg_pwrsw_vsel=0(3.0v), reg_en_pwrsw=1)
|
|
mmio_write_32(TOP_BASE + REG_TOP_SD_PWRSW_CTRL, 0x9);
|
|
cvi_sdio0_pad_function(false);
|
|
cvi_sdio0_pad_setting(false);
|
|
} else {
|
|
//Voltage close flow
|
|
//(reg_pwrsw_auto=1, reg_pwrsw_disc=1, reg_pwrsw_vsel=1(1.8v), reg_en_pwrsw=0)
|
|
mmio_write_32(TOP_BASE + REG_TOP_SD_PWRSW_CTRL, 0xE);
|
|
cvi_sdio0_pad_function(true);
|
|
cvi_sdio0_pad_setting(true);
|
|
}
|
|
}
|
|
} else if (host->index == MMC_TYPE_SDIO) {
|
|
cvi_sdio1_pad_setting();
|
|
} else {
|
|
printf("wrong host index : %d !!\n", host->index);
|
|
return -ENXIO;
|
|
}
|
|
|
|
ret = sdhci_probe(dev);
|
|
|
|
if (host->max_clk == MMC_MAX_CLOCK) {
|
|
pr_debug("set IP clock to 375Mhz\n");
|
|
mmio_write_32(cvi_host->pll_reg, MMC_MAX_CLOCK_DIV_VALUE);
|
|
|
|
pr_debug("Be sure to switch clock source to PLL\n");
|
|
mmio_clrbits_32(CLOCK_BYPASS_SELECT_REGISTER, BIT(cvi_host->pll_index));
|
|
pr_debug("XTAL->PLL reg = 0x%x\n", mmio_read_32(CLOCK_BYPASS_SELECT_REGISTER));
|
|
|
|
pr_debug("eMMC/SD CLK is %d in FPGA_ASIC\n", host->max_clk);
|
|
}
|
|
|
|
if (cvi_host->is_64_addressing) {
|
|
sdhci_writew(host, sdhci_readw(host, SDHCI_HOST_CONTROL2)
|
|
| SDHCI_HOST_VER4_ENABLE | SDHCI_HOST_ADDRESSING,
|
|
SDHCI_HOST_CONTROL2);
|
|
}
|
|
|
|
if (cvi_host->reset_tx_rx_phy) {
|
|
/* Default value */
|
|
sdhci_writel(host,
|
|
sdhci_readl(host, CVI_SDHCI_VENDOR_MSHC_CTRL_R) | BIT(1) | BIT(8) | BIT(9),
|
|
CVI_SDHCI_VENDOR_MSHC_CTRL_R);
|
|
sdhci_writel(host, 0x01000100, CVI_SDHCI_PHY_TX_RX_DLY);
|
|
sdhci_writel(host, 00000001, SDHCI_PHY_CONFIG);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
const struct sdhci_ops cvi_sdhci_emmc_ops = {
|
|
#ifdef CONFIG_MMC_SUPPORTS_TUNING
|
|
.platform_execute_tuning = cvi_general_execute_tuning,
|
|
#endif
|
|
.reset = cvi_general_reset,
|
|
};
|
|
|
|
const struct sdhci_ops cvi_sdhci_sd_ops = {
|
|
.get_cd = cvi_get_cd,
|
|
#ifdef CONFIG_MMC_SUPPORTS_TUNING
|
|
.platform_execute_tuning = cvi_general_execute_tuning,
|
|
#endif
|
|
#ifdef CONFIG_MMC_UHS_SUPPORT
|
|
.voltage_switch = cvi_sd_voltage_switch,
|
|
#endif
|
|
.reset = cvi_general_reset,
|
|
};
|
|
|
|
static const struct cvi_sdhci_driver_data sdhci_cvi_emmc_drvdata = {
|
|
.ops = &cvi_sdhci_emmc_ops,
|
|
.index = MMC_TYPE_MMC,
|
|
};
|
|
|
|
static const struct cvi_sdhci_driver_data sdhci_cvi_sd_drvdata = {
|
|
.ops = &cvi_sdhci_sd_ops,
|
|
.index = MMC_TYPE_SD,
|
|
};
|
|
|
|
static const struct cvi_sdhci_driver_data sdhci_cvi_sdio_drvdata = {
|
|
.ops = &cvi_sdhci_sd_ops,
|
|
.index = MMC_TYPE_SDIO,
|
|
};
|
|
|
|
static const struct udevice_id cvi_sdhci_match[] = {
|
|
{
|
|
.compatible = "cvitek,cv181x-emmc",
|
|
.data = (ulong)&sdhci_cvi_emmc_drvdata,
|
|
},
|
|
{
|
|
.compatible = "cvitek,cv181x-sd",
|
|
.data = (ulong)&sdhci_cvi_sd_drvdata,
|
|
},
|
|
{
|
|
.compatible = "cvitek,cv181x-sdio",
|
|
.data = (ulong)&sdhci_cvi_sdio_drvdata,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(cvi_sdhci) = {
|
|
.name = "cvi_sdhci",
|
|
.id = UCLASS_MMC,
|
|
.of_match = cvi_sdhci_match,
|
|
.of_to_plat = cvi_ofdata_to_platdata,
|
|
.bind = cvi_sdhci_bind,
|
|
.probe = cvi_sdhci_probe,
|
|
.priv_auto = sizeof(struct cvi_sdhci_host),
|
|
.plat_auto = sizeof(struct cvi_sdhci_plat),
|
|
.ops = &sdhci_ops,
|
|
};
|