5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
37 lines
1.0 KiB
Plaintext
37 lines
1.0 KiB
Plaintext
Altera FPGA/HPS Bridge Driver
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Required properties:
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- regs : base address and size for AXI bridge module
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- compatible : Should contain one of:
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"altr,socfpga-lwhps2fpga-bridge",
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"altr,socfpga-hps2fpga-bridge", or
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"altr,socfpga-fpga2hps-bridge"
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- resets : Phandle and reset specifier for this bridge's reset
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- clocks : Clocks used by this module.
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See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
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Example:
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fpga_bridge0: fpga-bridge@ff400000 {
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compatible = "altr,socfpga-lwhps2fpga-bridge";
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reg = <0xff400000 0x100000>;
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resets = <&rst LWHPS2FPGA_RESET>;
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clocks = <&l4_main_clk>;
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bridge-enable = <0>;
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};
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fpga_bridge1: fpga-bridge@ff500000 {
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compatible = "altr,socfpga-hps2fpga-bridge";
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reg = <0xff500000 0x10000>;
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resets = <&rst HPS2FPGA_RESET>;
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clocks = <&l4_main_clk>;
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bridge-enable = <1>;
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};
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fpga_bridge2: fpga-bridge@ff600000 {
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compatible = "altr,socfpga-fpga2hps-bridge";
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reg = <0xff600000 0x100000>;
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resets = <&rst FPGA2HPS_RESET>;
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clocks = <&l4_main_clk>;
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};
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