5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
13 lines
276 B
Plaintext
13 lines
276 B
Plaintext
Altera Arria10 Partial Reconfiguration IP
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Required properties:
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- compatible : should contain "altr,a10-pr-ip"
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- reg : base address and size for memory mapped io.
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Example:
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fpga_mgr: fpga-mgr@ff20c000 {
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compatible = "altr,a10-pr-ip";
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reg = <0xff20c000 0x10>;
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};
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