5c7dd7acc3
repo: https://github.com/T-head-Semi/linux commit: b1313fe517ca3703119dcc99ef3bbf75ab42bcfb Change-Id: I6cbb35294024ea3a66140e311f4bb705fd7fd626
29 lines
842 B
Plaintext
29 lines
842 B
Plaintext
Omap2/3 intc controller
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On TI omap2 and 3 the intc interrupt controller can provide
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96 or 128 IRQ signals to the ARM host depending on the SoC.
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Required Properties:
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- compatible: should be one of
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"ti,omap2-intc"
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"ti,omap3-intc"
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"ti,dm814-intc"
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"ti,dm816-intc"
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"ti,am33xx-intc"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode interrupt
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source, should be 1 for intc
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- interrupts: interrupt reference to primary interrupt controller
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Please refer to interrupts.txt in this directory for details of the common
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Interrupt Controllers bindings used by client devices.
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Example:
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intc: interrupt-controller@48200000 {
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compatible = "ti,omap3-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x48200000 0x1000>;
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};
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